CN111933693A - MOS transistor and method for manufacturing the same - Google Patents

Abstract

The present invention provides a MOS transistor and a method for fabricating the same, in which an inversion doped region of a second conductivity type is formed in a source/drain region of a first conductivity type, the source/drain region is laterally diffused to the point of contact with a gate electrode overlapping, the boundary of the lateral diffusion of the inversion doping region does not exceed the sidewall of the gate, the bottom boundary of the longitudinal diffusion and the bottom boundary of the source/drain region have a first vertical distance, the inversion doping region The top boundary of the vertical diffusion of the impurity region has a second vertical distance from the top boundary of the source/drain region, which can reduce the leakage current and increase the breakdown voltage of the transistor. The manufacturing method of the MOS transistor of the present invention has the advantages of simple process and low cost.

Description

MOS transistor and method of manufacturing the same

technical field

The invention relates to the technical field of fabrication of semiconductor devices, in particular to a MOS transistor and a fabrication method thereof.

Background technique

At present, Metal Oxide Semiconductor (MOS) field effect transistors can be divided into two categories: NMOS transistors and PMOS transistors. FIG. 1 is a schematic structural diagram of a MOS (Metal Oxide Semiconductor) transistor known in the art, an active/drain region 101 is formed in a substrate 100, and a gate oxide layer is formed on the surface of the substrate 100 102 . Gate 103 .

At high voltages, input-output circuits or high-power integrated circuits are required to have MOS transistors with high breakdown voltages. In order to enable the MOS transistor shown in FIG. 1 to be applied in a high-voltage environment and to operate safely under high-voltage, two common methods are usually adopted in the prior art, one is sacrificing the electrical performance or device area of the MOS transistor; the other One way is to use the charge balance method of RESURF technology or to improve the device structure, thereby increasing the breakdown voltage without sacrificing the electrical performance of the device.

Therefore, how to further improve the electrical performance of the MOS transistor has become one of the hot issues studied by those skilled in the art.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a MOS transistor, which can further improve the electrical characteristics of the MOS transistor.

Another object of the present invention is to provide a method for manufacturing a MOS transistor, which can obtain a MOS transistor with better electrical characteristics through a relatively simple process.

In order to solve the above technical problems, the present invention provides a MOS transistor, which includes a substrate and a gate formed on the substrate, and active/drain regions are formed in the substrate on both sides of the gate, and the source/drain is formed in the substrate on both sides of the gate. The drain region is laterally diffused to overlap with the gate; wherein, the MOS transistor further includes: an inversion doping region of the second conductivity type, the inversion doping region is formed on both sides of the gate In the source/drain region, the boundary of the lateral diffusion of the inversion doping region does not exceed the sidewall of the gate, and the bottom boundary of the longitudinal diffusion of the inversion doping region is separated from the bottom boundary of the source/drain region For a first vertical distance, the top boundary of the longitudinal diffusion of the inversion doping region is separated from the top boundary of the source/drain region by a second vertical distance, and both the first vertical distance and the second vertical distance are greater than 0.

Optionally, the source/drain region includes a heavily doped region of a first conductivity type and an extension region of the first conductivity type, the extension region surrounding the heavily doped region and having a top border with the heavily doped region The top boundary of the impurity region is flush, the lateral distance between the boundary of the heavily doped region facing the gate and the sidewall of the gate is greater than 0, and the extension region extends from the edge of the heavily doped region. The boundary extends below the bottom of the gate and overlaps the gate, and the first conductive type ion doping concentration of the extension extension region is lower than that of the heavily doped region. impurity concentration.

Optionally, the inversion doped region is formed in the extension region.

Optionally, the doping concentration of the second conductivity type ions of the inversion doped region is higher than the doping concentration of the first conductivity type ions of the heavily doped region.

Optionally, the first vertical distance is greater than or equal to the second vertical distance.

Optionally, the MOS transistor further includes a spacer on the sidewall of the gate and a gate oxide layer between the gate and the substrate; the inversion doped region is formed on the gate. in the source/drain regions at the bottom of the spacers.

Based on the same inventive concept, the present invention also provides a method for manufacturing a MOS transistor according to the present invention, comprising the following steps:

providing a substrate on which a gate is formed;

Perform source-drain ion implantation on the substrates on both sides of the gate using doping impurities of the first conductivity type, so as to form source-drain implantation regions in the substrates on both sides of the gate;

Perform inversion ion implantation on the source and drain doped regions by using doping impurities of the second conductivity type to form inversion implantation regions in the source and drain doped regions;

The substrate is annealed to form source/drain regions and inversion doped regions, the source/drain regions are laterally diffused to overlap the gate, and the inversion doped regions are laterally diffused The boundary does not exceed the sidewall of the gate, the bottom boundary of the longitudinal diffusion of the inversion doped region and the bottom boundary of the source/drain region have a first distance, and the top boundary of the longitudinal diffusion of the inversion doped region has a first distance There is a second distance from the top boundary of the source/drain region, and both the first distance and the second distance are greater than zero.

Optionally, source-drain ion implantation is performed on the substrate on both sides of the gate using a first inclination angle, and inversion ion implantation is performed on the source-drain doped region using a second inclination angle, the first inclination angle is and the second inclination angle are both the included angle between the ion implantation direction and the normal on the surface of the substrate, and the first inclination angle is greater than the second inclination angle.

Optionally, after the annealing process, the source/drain region includes a heavily doped region of the first conductivity type and an extension region of the first conductivity type, the extension region surrounding the heavily doped region and having a top border flush with the top boundary of the heavily doped region, the lateral distance between the boundary of the heavily doped region facing the gate and the sidewall of the gate is greater than 0, the extension region extends from the The boundary of the heavily doped region extends below the bottom of the gate and overlaps with the gate, and the first conductivity type ion doping concentration of the extended extension region is lower than that of the heavily doped region. A conductivity type ion doping concentration.

Optionally, after the gate is formed and before or after the source-drain ion implantation, spacers are also formed on the sidewalls of the gate.

Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

1. In the MOS transistor structure of the present invention, inversion doped regions of the second conductivity type are formed in the source/drain regions of the first conductivity type, and the source/drain regions are laterally diffused to overlap with the gate, so The boundary of the lateral diffusion of the inversion doping region does not exceed the sidewall of the gate, the bottom boundary of the longitudinal diffusion and the bottom boundary of the source/drain region have a first vertical distance, and the inversion doping region is longitudinally diffused The top boundary of the source/drain region has a second vertical distance from the top boundary of the source/drain region, which can reduce the leakage current of the transistor and increase its breakdown voltage.

2. In the manufacturing method of the MOS transistor of the present invention, through high-energy ion implantation, an inversion doped region for improving the electrical characteristics of the device can be formed in the source/drain region, the process is simple, and the cost is low.

Description of drawings

FIG. 1 is a schematic cross-sectional structure diagram of a conventional MOS transistor.

FIG. 2 is a schematic cross-sectional structure diagram of a MOS transistor according to an embodiment of the present invention.

FIG. 3 is a BVDss (source-drain breakdown voltage)-Idsat (saturated source-drain current) characteristic curve of the MOS transistor shown in FIGS. 1 and 2 .

FIG. 4 is an Ioff (drain current)-Idsat (saturated source-drain current) characteristic curve of the MOS transistor shown in FIGS. 1 and 2 .

FIG. 5 is a flowchart of a method for manufacturing a MOS transistor according to a specific embodiment of the present invention.

FIG. 6 to FIG. 9 are schematic cross-sectional structural diagrams of a device in a method for manufacturing a MOS transistor according to an embodiment of the present invention.

Among them, the reference numerals are as follows:

100-substrate, 101-source/drain region, 102-gate oxide layer, 103-gate;

200-substrate, 201-gate oxide, 202-gate, 203-spacer, 204-source/drain region, 204a-heavy doped region, 204b-extension region, 205-inversion doped region, 204 '-source-drain implantation region, 205'-inversion implantation region;

D1-first vertical distance, D2-second vertical distance, D3-lateral distance.

Detailed ways

The technical solution proposed by the present invention will be further described in detail below with reference to Fig. 2 to Fig. 9 and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

Referring to FIG. 2 , an embodiment of the present invention provides a MOS transistor including a substrate 200 , a gate oxide layer 201 , a gate 202 , a spacer 203 , a source/drain region 204 and an inversion doped region 205 .

The substrate 200 may be any suitable substrate material known to those skilled in the art, such as a bulk silicon substrate or a silicon-on-insulator substrate, which is not limited in this embodiment.

The gate oxide layer 201 and the gate electrode 202 are sequentially stacked on the surface of the substrate 200 to form a gate stack structure, and sidewall spacers 203 are formed on the sidewalls of the gate stack structure. The material of the gate oxide layer 201 may be silicon dioxide, and the material of the gate 202 may be doped polysilicon or the like.

Source/drain regions 204 of a first conductivity type (eg N-type) are formed in the substrate 200 on both sides of the gate stack structure, and the source/drain regions 204 on one side of the gate 202 serve as the source region of the MOS transistor , the source/drain region 204 on the other side serves as the drain region of the MOS transistor. The source/drain regions 204 on both sides of the gate 202 are laterally diffused to partially overlap the gate 203 . The greater the extent to which the source/drain regions 204 on both sides of the gate 202 extend toward the gate 203 (that is, the greater the area where the source/drain regions 204 and the gate 203 overlap), under the same gate voltage Vgate, the MOS transistor The greater the drain current Idrain of , and the same drain voltage Vdrain, the greater the drain current Idrain of the MOS transistor.

The inversion-doped region 205 is of the second conductivity type (eg, P-type), and its conductivity type is opposite to that of the source/drain regions 204 . The inversion doped regions 205 are formed in the source/drain regions 204 on both sides of the gate 202, and the lateral diffusion boundaries of the inversion doped regions 205 on both sides of the gate 202 do not exceed the For the sidewall of the gate 202, as an example, there is a lateral distance D3 between the boundary where the inversion doped region 205 laterally diffuses toward the gate 202 and the sidewall of the gate 202, and D3 is greater than 0.

In the direction of diffusion toward the bottom of the substrate 200 , the bottom boundary of the longitudinal diffusion of the inversion doped region 205 and the bottom boundary of the source/drain region 204 are separated by a first vertical distance D1 , and the bottom boundary of the inversion doped region 205 is diffused toward the top of the substrate 200 In the direction of , the top boundary of the longitudinal diffusion of the inversion doping region 205 is separated from the top boundary of the source/drain region 204 by a second vertical distance D2, the first vertical distance D1 and the second vertical distance D2 are greater than 0. Optionally, the first vertical distance D1 is greater than or equal to the second vertical distance D2, which is conducive to forming a shallower junction and improving the electrical characteristics of the device.

In addition, the larger the proportion of the inversion doped region 205 in the source/drain region 204, the larger the drain current Idrain of the MOS transistor under the same gate voltage Vgate, and the same drain voltage Under Vdrain, the drain current Idrain of the MOS transistor is larger. Therefore, it is optimal to control the inversion doped regions 205 in the source/drain regions 204 to be the smallest inversion doped regions allowed by the process.

Optionally, the source/drain region 204 includes a heavily doped region 204a of the first conductivity type and an extension region 204b of the first conductivity type, the extension region 204b surrounding the sidewall of the heavily doped region 204a and the bottom wall, and the top boundary of the extension region 204b is flush with the top boundary of the heavily doped region 204a, and together constitute the top boundary of the source/drain region 204 . There is a lateral distance D4 greater than 0 between the boundary of the heavily doped region 204a facing the gate 202 and the sidewall of the gate 202, and the extension region 204b extends from the boundary of the heavily doped region 204a extending below the bottom of the gate electrode 202 and overlapping the gate electrode 202 , the first conductivity type ion doping concentration of the extension extension region 204b is lower than that of the heavily doped region 204a Type ion doping concentration. The inversion doped region 205 is formed in the extension region 204b at the bottom of the spacer 203, so D3 is smaller than D4.

Optionally, the ion doping concentration of the second conductivity type of the inversion doped region 205 is higher than the doping concentration of the first conductivity type ions of the heavily doped region 204a.

As an example, the MOS transistor is a PMOS transistor, the substrate 200 is a P-type semiconductor substrate, the source/drain regions 204 are N-type doped regions, the inverse-type doped regions 205 are P-type doped regions, and the inverse-type doped regions are The P ion doping concentration in the region 205 is greater than the P ion doping concentration in the channel region (ie, the substrate) at the bottom of the gate 202 , and also greater than the N-type ion doping concentration in the heavily doped region 204 a of the source/drain region 204 . doping concentration. For example, the P ion doping concentration in the channel region (ie the substrate) at the bottom of the gate 202 is in the order of 10 ¹² /cm ² , and the ion doping concentration in the source/drain regions 204 is in the order of 10 ¹³ -10 ¹⁴ /cm ² , the ion doping concentration of the inversion doping region 205 is not lower than 10 ¹⁵ /cm ² .

Optionally, the source/drain regions 204 on both sides of the gate 202 are symmetrically distributed, and the inversion doped regions 205 on both sides of the gate 202 are also symmetrically distributed.

Due to the existence of the inversion doped region 205, a depletion region can be formed in the source/drain region 204 by using the impurity compensation effect, which increases the width of the depletion region, reduces the source/drain junction capacitance of the transistor, and improves the The electric field distribution in the source/drain region 204 is reduced, the leakage current of the source/drain junction is reduced, the source-drain breakdown voltage is increased, and the electrical characteristics of the MOS transistor are further improved. In addition, since the upper and lower boundaries (ie, the top and bottom boundaries) of the inversion doped region 205 and the boundary facing the channel are at a distance from the corresponding boundaries of the source/drain regions 204, the inversion doped region can be avoided The addition of 205 adversely affects the channel.

In order to verify the performance of the MOS transistor in this embodiment, the performance test of the MOS transistor shown in FIG. 1 to FIG. 2 is carried out. Among the two MOS transistors, the MOS transistor shown in FIG. Only inversion doped regions 205 are added to the source/drain regions 204 . The test results are shown in Figures 3 and 4. In Figures 3 and 4, "Prior Art" indicates the test results of the MOS transistor shown in Figure 1, and "Invention" indicates the MOS transistor shown in Figure 2. Transistor test results.

It can be seen from FIG. 3 that under the condition of the same saturated source-drain current Idsat, the MOS transistor of the present invention has a higher breakdown voltage BVDss, that is, compared with the prior art, the MOS transistor of the present invention has better The BVDss-Idsat characteristic shows that the inversion doping region 205 added in the present invention can improve the BVDss-Idsat characteristic of the MOS transistor and increase the breakdown voltage of the device.

It can be seen from FIG. 4 that under the condition of the same saturated source-drain current Idsat, the MOS transistor of the present invention has a lower leakage current Ioff than the prior art, that is, the MOS transistor of the present invention has a lower leakage current Ioff than the prior art. It has better Ioff-Idsat characteristics and can reduce device leakage current.

Based on the above test results, it can be seen that in the MOS transistor structure of this embodiment, inversion doped regions of the second conductivity type are formed in the source/drain regions of the first conductivity type, which can reduce the occupied area of the MOS transistor without sacrificing conduction. The BVDss-Idsat electrical characteristics and the Ioff-Idsat electrical characteristics of the MOS transistor are significantly improved under the condition of passing current and without affecting other electrical properties of the device.

It should be noted that the above embodiments only list part of the structure of the MOS transistor of the present invention, and the technical solution of the present invention is not limited to this. In other embodiments of the present invention, the MOS transistor may also have other structures, such as shallow trench isolation structures, etc.

Please refer to FIG. 5 , an embodiment of the present invention further provides a method for manufacturing the above-mentioned MOS transistor, including the following steps:

S1, providing a substrate, and forming a gate on the substrate;

S2, using doping impurities of the first conductivity type to perform source-drain ion implantation on the substrates on both sides of the gate to form source-drain implantation regions in the substrates on both sides of the gate;

S3, performing inversion ion implantation on the source and drain doped regions by using doping impurities of the second conductivity type to form inversion implantation regions in the source and drain doped regions;

S4, annealing the substrate to form source/drain regions and inversion doping regions, the source/drain regions are laterally diffused to overlap the gate, and the inversion doping regions are laterally diffused The boundary of the diffusion does not exceed the sidewall of the gate, the bottom boundary of the longitudinal diffusion of the inversion doping region and the bottom boundary of the source/drain region have a first distance, and the longitudinal diffusion of the inversion doping region has a first distance. The top boundary has a second distance from the top boundary of the source/drain regions, and both the first distance and the second distance are greater than zero.

In step S1, first, referring to FIG. 6, a substrate 200 is provided, and the substrate 200 may be any suitable substrate material known to those skilled in the art, such as bulk silicon substrate, silicon-on-insulator substrate , silicon germanium substrate, etc.; then through thermal oxidation or chemical vapor deposition process, the gate oxide layer 201 is formed on the substrate 200, and further through a series of processes such as polysilicon deposition, photolithography and etching, to remove excess polysilicon and A gate oxide layer 201 is formed to form a gate electrode 202 on the substrate 200, and the gate electrode 202 and the gate oxide layer 201 below the gate oxide layer 201 are stacked to form a gate stack structure.

Optionally, after the gate 202 is formed, the spacer 203 is formed by depositing an insulating dielectric material and etching the spacer, and the spacer 203 covers the gate 202 and the sidewall of the gate oxide layer 201 under the gate 202 , the material of the sidewall 203 may be a single-layer structure such as silicon oxide or silicon nitride, or a composite structure formed by stacking multiple film layers such as silicon oxide and silicon nitride.

Referring to FIG. 7 , in step S2 , the gate stack structure and the spacers 203 are used as masks, and the first inclination angle A, the first implantation energy and the first implantation dose per unit area are used to inject the gate 203 to both sides of the gate. The first conductive type ions, such as N-type ions such as phosphorus ions, arsenic ions, or antimony ions, are implanted into the substrate 200, so that part of the first conductive type ions can be implanted into the substrate 200 under the bottom of the gate 202, and a part of the first conductive type ions can be implanted into the substrate 200 under the bottom of the gate 202 Ions of the first conductivity type can be implanted into the substrate 200 outside the gate 202 to form a source-drain implant region 204 ′ partially overlapping the gate 202 .

Please refer to FIG. 8 , in step S3 , the gate stack structure and the sidewall spacers 203 are used as masks, and the second inclination angle B, the second implantation energy and the second implantation dose per unit area are used to implant the source and drain into the source-drain. Second conductivity type ions, such as boron ions, boron difluoride ions, etc., are implanted into the region 204' to form an inversion implantation region 205'.

Wherein, please refer to FIG. 7 and FIG. 8 , the first inclination angle A and the second inclination angle B are both the angle between the ion implantation direction and the normal on the surface of the substrate 200 , and the first inclination angle B The inclination angle A is greater than the second inclination angle B, and the second inclination angle B may be 0-30°, so that the implantation depth of the inversion implantation region 205' in the lateral direction is shallower than that of the source-drain implantation region 204', and the inversion implantation region 204' 205' does not overlap with the gate 202, and further, the inversion implantation region 205' may be located at the bottom of the spacer 203; the second implantation energy is smaller than the first implantation energy, thereby making the inversion implantation region 205' in the longitudinal direction. The implantation depth is shallower than that of the source-drain implantation region 204'; the second implantation dose per unit area is greater than the first implantation dose per unit area, so that the inversion implantation region 205' can not only neutralize the source-drain implantation region 204' The first conductivity type ions in this region can also form a second conductivity type ion doped region with a required doping concentration.

In addition, in this embodiment, the sidewall spacers 203 can play a role of limiting the lateral implantation depth of the inversion implantation region 205' toward the gate 202. In other embodiments of the present invention, in step S1, the sidewall spacer 203 may not be fabricated first, and in step S2, the gate stack structure may be directly used as a mask to perform source-drain ion implantation to form a source-drain with a required lateral implantation depth In the implanted region 204', in step S3, the sidewall spacers 203 are first formed, and then inversion ion implantation is performed using the sidewall spacers 203 and the gate stack structure as a mask to form an inversion implanted region 205' with a required lateral extension depth. Obviously, in this embodiment, since the sidewall spacers 203 are formed after the source-drain implantation region 204' is formed, the lateral implantation depth of the inversion implantation region 205' is smaller than the lateral implantation depth of the source-drain implantation region 204'.

Referring to FIG. 9, in step S4, the substrate 200 is annealed by a rapid annealing process, so that the ions in the source and drain implanted regions 204' continue to diffuse in the lateral and vertical directions, and the inversion implanted regions 205' are in the lateral direction. and continue to spread vertically. Therefore, the source-drain implantation region 204' is diffused to form a heavily doped region 204a and an extension region 204b surrounding the heavily doped region 204a. The doping concentration of the heavily doped region 204a is higher than that of the extension region 204b. The implanted region 205 ′ is diffused and ion-neutralized to form an inversion doped region 205 . Wherein, during the annealing process, on the one hand, due to the existence of the inversion implantation region 205', the extension of the source and drain implantation region 204' in the lateral and vertical directions will be affected by the impurity compensation effect of the inversion implantation region 205'. , so that a shallower junction can be formed under the gate 202, and a depletion region can be formed in the extension extension region 204b; The impurity compensation effect of the implanted region 204 ′ is affected, so the proportion of the inversion doping region 205 in the source/drain region 204 can be controlled, thereby preventing the inversion doping region 205 from diffusing and extending below the gate 202 .

Therefore, during the annealing process, the two implanted regions with opposite doping types, the inversion implanted region 205' and the source-drain implanted region 204', interact with each other, which ultimately improves the electric field distribution in the source/drain regions 204 and reduces the The source/drain junction leakage current is reduced, the source-drain breakdown voltage is increased, and the electrical characteristics of the MOS transistor are further improved, and the upper and lower boundaries of the inversion doping region 205 and the boundary facing the channel can be guaranteed to be the same as the source/drain region 204. There is a distance between the corresponding boundaries of , so that the addition of the inversion doping region 205 can avoid adverse effects on the channel.

In the method for manufacturing a MOS transistor in this embodiment, an inversion doped region for improving the electrical characteristics of the device can be formed in the source/drain region through a high-energy ion implantation process, thereby manufacturing a high-performance MOS transistor. Simple and low cost.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention according to the above disclosure belong to the scope of the technical solutions of the present invention.

Claims (10)

1. A MOS transistor comprising a substrate and a gate formed on the substrate, wherein source/drain regions are formed in the substrate on both sides of the gate, and the source/drain regions are laterally diffused to overlap the gate, the MOS transistor further comprising: the inversion type doping region is formed in the source/drain region on two sides of the grid electrode, the boundary of the inversion type doping region in transverse diffusion does not exceed the side wall of the grid electrode, the bottom boundary of the inversion type doping region in longitudinal diffusion and the bottom boundary of the source/drain region are separated by a first vertical distance, the top boundary of the inversion type doping region in longitudinal diffusion and the top boundary of the source/drain region are separated by a second vertical distance, and the first vertical distance and the second vertical distance are both larger than 0.

2. The MOS transistor of claim 1, wherein the source/drain region comprises a heavily doped region of the first conductivity type and an extended extension region of the first conductivity type surrounding the heavily doped region with a top boundary flush with a top boundary of the heavily doped region, a lateral distance between a boundary of the heavily doped region facing the gate and a sidewall of the gate is greater than 0, the extended extension region extends from the boundary of the heavily doped region to below a bottom of the gate and overlaps the gate, and a first conductivity type ion doping concentration of the extended extension region is lower than the first conductivity type ion doping concentration of the heavily doped region.

3. The MOS transistor of claim 2, wherein the inversion-doped region is formed in the extended extension region.

4. The MOS transistor of claim 2, wherein the inversion-doped region has a higher doping concentration of ions of the second conductivity type than the doping concentration of ions of the first conductivity type of the heavily doped region.

5. The MOS transistor of claim 1, wherein the first vertical distance is equal to or greater than the second vertical distance.

6. The MOS transistor of claim 1, further comprising spacers on sidewalls of the gate and a gate oxide layer between the gate and the substrate; the inversion doping region is formed in the source/drain region at the bottom of the side wall.

7. A method of manufacturing a MOS transistor according to any of claims 1 to 6, comprising:

providing a substrate, and forming a grid electrode on the substrate;

performing source-drain ion implantation on the substrates on two sides of the grid by adopting doping impurities of a first conduction type so as to form source-drain implantation regions in the substrates on two sides of the grid;

performing inversion ion implantation on the source-drain doped region by using doping impurities of a second conductivity type to form an inversion implantation region in the source-drain doped region;

and annealing the substrate to form a source/drain region and an inversion doping region, wherein the source/drain region is laterally diffused to be overlapped with the grid electrode, the laterally diffused boundary of the inversion doping region does not exceed the side wall of the grid electrode, a first distance is reserved between the longitudinally diffused bottom boundary of the inversion doping region and the bottom boundary of the source/drain region, a second distance is reserved between the longitudinally diffused top boundary of the inversion doping region and the top boundary of the source/drain region, and the first distance and the second distance are both larger than 0.

8. The method of manufacturing the MOS transistor according to claim 7, wherein source-drain ion implantation is performed on the substrate on both sides of the gate with a first inclination angle, inversion ion implantation is performed on the source-drain doped region with a second inclination angle, the first inclination angle and the second inclination angle are both included angles between an ion implantation direction and a normal line on the surface of the substrate, and the first inclination angle is larger than the second inclination angle.

9. The method of claim 7, wherein after the annealing process, the source/drain region comprises a heavily doped region of the first conductivity type and an extended extension region of the first conductivity type, the extended extension region surrounds the heavily doped region and has a top boundary flush with a top boundary of the heavily doped region, a lateral distance between a boundary of the heavily doped region facing the gate and a sidewall of the gate is greater than 0, the extended extension region extends from the boundary of the heavily doped region to below a bottom of the gate and overlaps the gate, and a first conductivity type ion doping concentration of the extended extension region is lower than a first conductivity type ion doping concentration of the heavily doped region.

10. The method for manufacturing the MOS transistor according to claim 7, wherein a sidewall is further formed on a sidewall of the gate after the gate is formed and before or after source-drain ion implantation is performed.

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