CN111952250A - Fabrication method of array substrate and array substrate - Google Patents

Abstract

The invention provides a manufacturing method of an array substrate and an array substrate, wherein a first insulating layer covering a first metal layer and an active layer thin film are sequentially formed on the substrate, wherein the etching rate of the active layer thin film is greater than that of the first insulating layer, Moreover, the active layer thin film and the first insulating layer are stacked on top of each other, and the active layer thin film is used as the guide layer of the first insulating layer when the holes are opened. Opening a hole can form a first contact hole that penetrates the active layer film and the first insulating layer from top to bottom. Guide, while avoiding the undercut problem of the first insulating layer below, a good taper angle can be obtained at the position of the first contact hole, so that the second metal layer subsequently filled into the first contact hole avoids the risk of wire breakage , effectively improve the yield of the product, and do not need to use a new mask, saving costs.

Description

Fabrication method of array substrate and array substrate

technical field

The present invention relates to the field of display technology, and in particular, to a manufacturing method of an array substrate and an array substrate.

Background technique

The liquid crystal display device has the advantages of good picture quality, small size, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost. In electronic devices such as personal digital assistants (PDAs), digital cameras, computer screens or laptop screens. The liquid crystal display device includes an opposing color filter substrate (Color Filter, CF) and a thin film transistor array (TFT array) substrate, and a liquid crystal layer (LC layer) sandwiched therebetween.

以上，此时因生产能力的局限性容易出现开孔异常的状况，造成接触不佳的问题，产生底切可能会导致后续层别的膜层填充在孔内时导致断线，进而影响显示面板的显示功能。In the traditional manufacturing process of thin film transistor array substrates, it is sometimes necessary to make through holes on the insulating layer. The insulating layer includes a composite single layer or a multilayer structure independently stacked. The tapered film is trimmed and the density of the upper part and the lower part are inconsistent, so the undercut phenomenon will occur at the opening of the insulating layer during etching, and the tape on the sidewall of the insulating layer is arc-shaped (ie curved ) or at a right angle, the side walls of the insulating layer are prone to sharp corners, and the thickness of the insulating layer is thick, such as reaching

As mentioned above, at this time, due to the limitation of production capacity, abnormal openings are prone to occur, resulting in poor contact problems. Undercutting may lead to disconnection when other layers of film are filled in the holes, which in turn affects the display panel. display function.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a manufacturing method of an array substrate and an array substrate, which can improve the undercut condition of the insulating layer and prevent the film layers of the subsequent layers from being disconnected.

The present invention provides a method for fabricating an array substrate, the method comprising:

providing a substrate including a display area and a non-display area peripheral to the display area;

forming a first metal layer on the substrate, and patterning the first metal layer in the non-display area to form first leads;

forming a first insulating layer covering the first metal layer on the substrate;

An active layer thin film covering the first insulating layer is formed on the first insulating layer, and a first contact hole penetrating the active layer thin film and the first insulating layer is formed, and the first contact hole is located at Above the first lead, the etching rate of the active layer film is greater than the etching rate of the first insulating layer;

A second metal layer is formed on the first insulating layer, and the second metal layer in the non-display area is patterned to form a second lead, and the second lead is filled into the first contact The hole is electrically connected with the first lead.

Further, after the step of forming the first contact hole penetrating the active layer thin film and the first insulating layer, patterning the active layer thin film to form the first contact hole located in the display area. Silicon islands, the active layer thin film is removed corresponding to the regions other than the silicon islands.

Further, before the step of forming a first contact hole penetrating the active layer thin film and the first insulating layer, patterning the active layer thin film to form silicon in the display area an island, and an etching guide portion is formed in the non-display area, and the etching guide portion corresponds to the position of the first contact hole.

Further, patterning is performed on the etching guide portion and the first insulating layer below the etching guide portion to form the first contact hole penetrating the etching guide portion and the first insulating layer.

Further, the second lead covers the etching guide portion, and the facing area of the second lead on the substrate is larger than the facing area of the etching guide portion on the substrate.

Further, the first insulating layer is formed by a chemical vapor deposition method, and the reactive gases used in the chemical vapor deposition method include silane, ammonia and nitrogen.

Further, the first insulating layer controls the flow rate of the silane to be in the range of 1860-2100 sccm in the high-speed film formation state, and the flow rate of the ammonia gas is in the range of 15400-17300 sccm; the control is performed in the low-speed film formation state. The flow rate of the silane is in the range of 600-700 sccm, and the flow rate of the ammonia gas is in the range of 7600-9000 sccm.

Further, the first contact hole is formed by an etching process, and when the active layer film is etched at a position corresponding to the first contact hole, the incoming gas of the etching process includes sulfur hexafluoride gas, helium gas and chlorine, the flow rate range of the sulfur hexafluoride is 310sccm-500sccm, the flow rate of the helium is 100sccm-300sccm, the flow rate of the chlorine gas is 2100sccm-2200sccm, the etching process The range of pressure used is 40-50mTorr, and the range of power used in the etching process is 5000-6000W; when etching the first insulating layer at the position corresponding to the first contact hole, the etching process The feeding gas includes sulfur hexafluoride gas, oxygen and helium, the flow rate of the sulfur hexafluoride is in the range of 510sccm-600sccm, the flow rate of the helium is in the range of 600sccm to 1000sccm, and the etching process adopts The pressure range of 160-170mTorr.

Further, the method further includes: before the step of forming the first metal layer on the substrate, forming a third metal layer on the substrate, and for the third metal layer in the non-display area The metal layer is patterned to form a third lead;

forming a second insulating layer covering the third lead on the substrate, the third lead and the second insulating layer being formed between the first metal layer and the substrate;

The first insulating layer and the active layer thin film are formed on the second insulating layer, and the active layer thin film, the first insulating layer and the second thin film in the non-display area are The insulating layer is patterned to form a second contact hole penetrating the active layer thin film, the first insulating layer and the second insulating layer, and the etching rate of the second insulating layer is less than or equal to the first insulating layer. an etch rate of the insulating layer;

The second lead is filled in the second contact hole and is electrically connected to the third lead.

The present invention also provides an array substrate, which is fabricated by the above-mentioned fabrication method of an array substrate.

In the method for manufacturing an array substrate and the array substrate provided by the present invention, a first insulating layer covering a first metal layer and an active layer film are sequentially formed on the substrate, wherein the etching rate of the active layer film is higher than that of the first insulating layer, and The active layer thin film and the first insulating layer are stacked on top of each other, and the active layer thin film is used as the guide layer of the first insulating layer when the hole is opened, and the active layer thin film and the first insulating layer are opened at the position corresponding to the first contact hole. The hole can form a first contact hole that penetrates the active layer film and the first insulating layer from top to bottom. Due to the different etching rates of the active layer film and the first insulating layer, the active layer film is guided when opening the hole. , while avoiding the problem of undercutting of the first insulating layer below, a good taper angle can be obtained at the position of the first contact hole, so that the second metal layer subsequently filled into the first contact hole avoids the risk of wire breakage, The yield of the product is effectively improved, and a new mask is not required, thereby saving costs.

Description of drawings

FIG. 1 is a schematic plan view of an array substrate in Embodiment 1 of the present invention;

2 is a schematic structural diagram of a first contact hole of an array substrate in Embodiment 1 of the present invention;

3a to 3l are schematic diagrams of the fabrication process of the array substrate in the first embodiment of the present invention;

4 is a schematic structural diagram of a second contact hole of the array substrate in Embodiment 1 of the present invention;

FIG. 5a to FIG. 5l are schematic diagrams of the manufacturing process of the array substrate in the second embodiment of the present invention.

Detailed ways

The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. The following examples are intended to illustrate the present invention, but not to limit the scope of the present invention.

Example 1

The manufacturing method of the array substrate according to the first embodiment of the present invention includes: as shown in FIG. 1 to FIG. 31 ,

A substrate 10 is provided. The substrate 10 includes a display area 101 and a non-display area 102 at the periphery of the display area 101 . The array substrate is fabricated on the substrate 10 at the same time. Specifically, the substrate 10 is a transparent substrate 10, for example, made of glass.

A first metal layer (not shown) is formed on the substrate 10, and the first metal layer is patterned to form a gate electrode 111 and a scan line (not shown) located in the display area 101, and a non-display area is formed. The first lead 113 of the area 102 is electrically connected to the scan line. Specifically, the material of the first metal layer is made of stacked Mo (molybdenum), Al (aluminum), and Mo (molybdenum). The first metal layer is exposed, developed and etched, thereby forming the gate 111, scanning wire and first lead 113 .

A first insulating layer 12 covering the first metal layer is formed on the substrate 10 , that is, the first insulating layer 12 covers the gate electrode 111 , the scan line and the first lead 113 .

An active layer thin film 13 covering the first insulating layer 12 is formed on the first insulating layer 12 , and the active layer thin film 13 and the first insulating layer 12 are stacked on top of each other to form a composite structure layer. The active layer thin film 13 is, for example, an amorphous silicon (a-Si) layer, but not limited thereto.

The active layer thin film 13 and the first insulating layer 12 in the non-display area 102 are patterned to form a first contact hole 120 penetrating the active layer thin film 13 and the first insulating layer 12, and the first contact hole 120 is located at the Above the first lead 113 , the first lead 113 is exposed from the first contact hole 120 , and the etching rate (ER, Etch Rate) of the active layer thin film 13 is greater than that of the first insulating layer 12 . The active layer thin film 13 is the upper layer of the first insulating layer 12, and the active layer thin film 13 is used as the guide layer of the first insulating layer 12 when the hole is opened. Opening a hole with the first insulating layer 12 can form a first contact hole 120 penetrating the active layer thin film 13 and the first insulating layer 12 from top to bottom.

Specifically, the step of forming the first contact hole 120 penetrating the active layer thin film 13 and the first insulating layer 12 includes:

As shown in FIG. 3 a , a first photoresist layer 21 is formed on the active layer thin film 13 .

As shown in FIG. 3b, the first photoresist layer 21 is exposed and developed through a mask to form a patterned photoresist layer. The first photoresist layer 21 includes an opaque area and a translucent area other than the opaque area. The opaque area is the remaining photoresist material, the light transmitting area is the area where the photoresist material is removed after development, the light transmitting area corresponds to the position where the active layer film 13 and the first insulating layer 12 need to be removed, the active layer film 13 is exposed from the light-transmitting area.

As shown in FIG. 3c, the active layer thin film 13 and the first insulating layer 12 under the light-transmitting region are removed by etching. Specifically, dry etching is used in this etching, and the thickness of the active layer thin film 13 is smaller than that of the first insulating layer 12. When the active layer thin film 13 is etched through, the first insulating layer 12 is exposed from the active layer thin film 13, Immediately thereafter, the etching of the first insulating layer 12 is started.

It should be noted that the etching is anisotropic, and the etching strength in the longitudinal direction on the substrate 10 is greater than the etching strength in the lateral direction. Since the etching rates of the active layer film 13 and the first insulating layer 12 are different, the etching rate of the active layer film 13 is relatively fast. After the active layer film 13 is etched through, the first contact hole 120 is initially reserved for At the etching position, the sidewall of the corresponding hole in the active layer film 13 acts as a guide or transition for etching the first insulating layer 12, and then when the first insulating layer 12 is etched, the upper active layer film 13 is also gradually retreating, using The film with a lower etching rate acts as a guide layer, which makes up for the lateral etching strength.

And the compactness of the first insulating layer 12 is relatively high, so the etching time of the first exposed part is relatively long, and the upper surface of the first insulating layer 12 is in contact with the active layer film 13, making it difficult for the etching gas to The upper surface of the insulating layer 12 reacts. With the gradual retreat of the active layer film 13 and the further etching of the first insulating layer 12, the etching gas can only be etched obliquely downward under the guidance of the sidewall of the active layer film 13. , thus forming the first contact hole 120 penetrating the active layer film 13 and the first insulating layer 12 , the sidewall of the first insulating layer 12 corresponding to the first contact hole 120 has a gentle slope, showing a good taper angle (the inclination of the cross section after etching), and there is no undercut phenomenon.

As shown in FIG. 3d , an ashing process is used to remove the opaque area of the first photoresist layer 21 .

Further, the purpose of increasing the etching rate of the active layer thin film 13 or reducing the etching rate of the first insulating layer 12 can be achieved by changing the film formation and etching parameters. Specifically, the first insulating layer 12 is made of silicon nitride (SiNx) material, and is formed by chemical vapor deposition (CVD). The reactive gases used in the chemical vapor deposition include silane (SH4), ammonia (NH3) and nitrogen (N2). ), the reactive gases used in the active layer thin film 13 include silane, hydrogen and phosphine (PH3).

Wherein, the first insulating layer 12 controls the flow rate of silane in the range of 1860-2100sccm (milliliter/min under standard conditions) in the high-speed film formation state, and the flow rate of ammonia gas in the range of 15400-17300sccm; in the low-speed film formation state The flow rate of silane is controlled in the range of 600-700 sccm, and the flow rate of ammonia gas is in the range of 7600-9000 sccm, which effectively reduces the etching rate of the first insulating layer 12, and this range does not cause electrical changes. For the flow rates of other related gases, reference may be made to the prior art, and details are not described herein again. Specifically, in this embodiment, the flow rate of silane is 1860 sccm and the flow rate of ammonia gas is 17300 sccm in the high-speed film forming state; the flow rate of silane is 600 sccm and the flow rate of ammonia gas is 9000 sccm in the low-speed film forming state.

For a good etching effect, the ECCP mode is used to etch the active layer thin film 13 . When the active layer thin film 13 is etched through, the first insulating layer 12 is etched in the RIE mode immediately.

When the active layer film 13 is etched at the position corresponding to the first contact hole 120, the feeding gas of the etching process includes sulfur hexafluoride (SF6) gas, helium (He) and chlorine gas (Cl2), and the flow rate of sulfur hexafluoride The value range is 310sccm-500sccm, the value range of the flow rate of helium is 100sccm-300sccm, which effectively increases the uniformity of plasma (plasma), the value range of the flow rate of chlorine gas is 2100sccm-2200sccm, and the pressure used in the etching process is the value The range is 40-50mTorr (millitorr), and the power used in the etching process ranges from 5000-6000W. Since the ECCP uses dual power supplies, the power used is also dual power, which effectively improves the active layer thin film 13. The etching rate. In this embodiment, the specific parameters of the etching process are, for example, the pressure is 50mTorr, the power is 6000W+6000W, the flow rate of sulfur hexafluoride is 500sccm, the flow rate of helium gas is 300sccm, and the flow rate of chlorine gas is 2200sccm.

When the first insulating layer 12 is etched at the position corresponding to the first contact hole 120, the feeding gas of the etching process includes sulfur hexafluoride gas, oxygen gas and helium gas. The gas flow rate ranges from 600 sccm to 1000 sccm, which effectively increases the uniformity of the plasma, and the pressure used in the etching process ranges from 160 to 170 mTorr. In this embodiment, the specific parameters of the etching process, for example, the pressure is 170 mTorr, the flow rate of sulfur hexafluoride is 600 sccm, and the flow rate of helium gas is 1000 sccm.

Preferably, after the first contact hole 120 penetrating the active layer thin film 13 and the first insulating layer 12 is etched, the taper angle on both sides of the first insulating layer 12 can be controlled to be about 30°, or even lower than 30°, and The average CD bias after the active layer thin film 13 and the first insulating layer 12 are co-etched is about 0.37um, which proves that the second etching of the first insulating layer 12 has a relatively small effect on the line width.

In this embodiment, as shown in FIG. 3e to FIG. 3g, after the step of forming the first contact hole 120 penetrating the active layer film 13 and the first insulating layer 12, a second light is applied on the active layer film The resist layer 22 exposes, develops and etches the active layer thin film 13 to form silicon islands 131 in the display area 101 , and the active layer thin film 13 corresponding to areas other than the silicon islands 131 is removed. As shown in FIG. 3h, the second photoresist layer 22 is removed.

Further, as shown in FIGS. 3i to 3l, a second metal layer 14 is formed on the first insulating layer 12 and the silicon island 131, a third photoresist layer 23 is coated on the second metal layer 14, and the second The metal layer 14 is exposed, developed and etched to form a source electrode 141, a drain electrode 142 and a data line (not shown) in the display area 101, and a second lead 143 located in the non-display area 102. The second lead 143 is filled into the first contact hole 120 to be electrically connected to the first lead 113 to achieve conduction. Since the sidewall of the first insulating layer 12 and the second lead 143 in contact with the sidewall is a smooth slope, the second lead 143 will not be broken. line risk. The third photoresist layer 23 is removed.

It is worth mentioning that, as shown in FIG. 4 , in order to obtain a narrower limit frame, the method further includes forming a third metal layer on the substrate 10 before the step of forming the first metal layer on the substrate 10 , namely, A third metal layer is disposed under the first metal layer, and the third metal layer in the non-display area 102 is patterned to form a third lead 151 . The third lead 151 is connected to an external circuit to realize signal transmission.

A second insulating layer 16 covering the third lead 151 is formed on the substrate 10, the third lead 151 and the second insulating layer 16 are formed between the first metal layer and the substrate 10, the first metal layer and the third metal layer They are separated by a second insulating layer 16 .

A first insulating layer 12 and an active layer film 13 are formed on the second insulating layer 16, and the active layer film 13, the first insulating layer 12 and the second insulating layer 16 in the non-display area 102 are patterned, A second contact hole 160 is formed through the active layer thin film 13, the first insulating layer 12, and the second insulating layer 16, and the etching rate of the second insulating layer 16 is less than or equal to that of the first insulating layer 12 to form a smooth For the formation principle of the first contact hole 120 and the second contact hole 160 on the sidewall, reference may be made to the aforementioned first contact hole 120 . It can be understood that after forming the first contact hole 120 and the second contact hole 160 , the active layer film 13 above the contact holes needs to be removed, and only the silicon island 131 in the display area 101 remains, but not limited thereto.

The second lead 143 is filled in the second contact hole 160 to be electrically connected to the third lead 151 .

After the patterning of the second metal layer 14 is completed, the subsequent processes, such as the formation of the common electrode (not shown) and the pixel electrode (not shown), can be referred to in the prior art, which will not be repeated here.

Embodiment 2

The parts of this embodiment are the same as those of the first implementation, and the same parts will not be repeated here. The difference is: as shown in FIG. 5a to FIG. Before step 120 , the active layer thin film 13 is patterned, silicon islands 131 are formed in the display area 101 , and etching guides 132 are formed in the non-display area 102 , and the etching guides 132 correspond to the positions of the first contact holes 120 .

Specifically, as shown in FIGS. 5 a to 5 c , a fourth photoresist layer 24 is coated on the active layer film 13 , and after exposure, development and etching, part of the active layer remains at the position where the first contact hole 120 is formed. The layer film 13 is used as a guide or transition for the subsequent etching, that is, the etching guide 132 . As shown in FIG. 5d, the fourth photoresist layer 24 is removed.

As shown in FIG. 5e, the fifth photoresist layer 25 is then coated on the etching guide portion 132, and after exposure and development, the photoresist layer is removed at the place corresponding to the first contact hole 120 to expose the etching guide portion 132; As shown in 5f, the etching guide portion 132 and the first insulating layer 12 under the etching guide portion 132 are etched to form a first contact hole 120 penetrating the etching guide portion 132 and the first insulating layer 12, and the first contact hole 120 has The smooth sidewall, that is, the taper angle is good, and the specific implementation can refer to the description of the first embodiment. As shown in FIG. 5g, the fifth photoresist layer 25 is removed.

Further, as shown in FIG. 5h , a second metal layer 14 covering the etching guide portion 132 and the silicon island 131 is formed on the substrate 10 .

As shown in FIG. 5 i , a sixth photoresist layer 26 is coated on the second metal layer 14 , and the photoresist layer is retained above the corresponding first contact holes 120 and on the silicon islands 131 through exposure and development.

After a wet etching process, as shown in FIG. 5j , a second lead 143 covering the etching guide portion 132 is formed in the non-display area 102 , and the second lead 143 is filled into the first contact hole 120 to be electrically connected to the first lead 113 , a source electrode 141 and a drain electrode 142 which are insulated from each other and spaced apart are formed in the display region 101 . It can be understood that, as shown in FIG. 5k, the silicon island 131 can also be etched continuously, and the doped amorphous silicon layer on the silicon island 131 can be etched away to form a channel.

As shown in FIG. 51, the sixth photoresist layer 26 is removed.

In this embodiment, the second lead 143 covers the etching guide portion 132 , and the edge of the second lead 143 is much larger than the edge of the etching guide portion 132 , that is, the facing area of the second lead 143 on the substrate 10 is larger than that of the etching guide portion 132 In the facing area on the substrate 10, the edge of the second lead 143 will not be undercut due to channel etching, which will cause leakage during acid etching in the subsequent layer, so that the first lead 113 will be missing.

After the patterning of the second metal layer 14 is completed, the subsequent processes, such as the formation of the common electrode and the pixel electrode, can be referred to in the prior art, which will not be repeated here.

The present invention also provides an array substrate, which is formed by the above-mentioned manufacturing method of the array substrate.

In the method for manufacturing an array substrate and the array substrate provided by the present invention, a first insulating layer 12 covering a first metal layer and an active layer thin film 13 are sequentially formed on the substrate 10, wherein the etching rate of the active layer thin film 13 is greater than that of the first metal layer. The insulating layer 12, and the active layer thin film 13 and the first insulating layer 12 are stacked on top of each other, and the active layer thin film 13 is used as the guide layer of the first insulating layer 12 when the hole is opened. The active layer film 13 and the first insulating layer 12 are opened to form a first contact hole 120 that penetrates the active layer film 13 and the first insulating layer 12 from top to bottom. Since the active layer film 13 and the first insulating layer The etching rate of 12 is different. When the hole is opened, it is guided by the active layer film 13, which avoids the problem of undercutting the first insulating layer 12 below. At the same time, a good taper angle can be obtained at the position of the first contact hole 120. Even if the structure of the third metal layer and the second insulating layer 16 is added under the first metal layer, the second insulating layer 16 having a good taper angle and penetrating the active layer thin film 13 , the first insulating layer 12 and the second insulating layer 16 can be formed. contact holes, so that the second metal layer 14 subsequently filled into the first contact holes 120 and/or the second contact holes avoids the risk of disconnection, effectively improving the yield of the product, and the existing light is used when forming the contact holes. A mask can be used, no need to modify or produce a new mask, which saves costs.

As used herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, in addition to those elements listed, but also other elements not expressly listed.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (10)

1. A method of fabricating an array substrate, wherein the method comprises: providing a substrate including a display area and a non-display area peripheral to the display area; forming a first metal layer on the substrate, and patterning the first metal layer in the non-display area to form first leads; forming a first insulating layer covering the first metal layer on the substrate; An active layer thin film covering the first insulating layer is formed on the first insulating layer, and a first contact hole penetrating the active layer thin film and the first insulating layer is formed, and the first contact hole is located at Above the first lead, the etching rate of the active layer film is greater than the etching rate of the first insulating layer; A second metal layer is formed on the first insulating layer, and the second metal layer in the non-display area is patterned to form a second lead, and the second lead is filled into the first contact The hole is electrically connected with the first lead. 2 . The method for fabricating an array substrate according to claim 1 , wherein after the step of forming the first contact hole penetrating the active layer thin film and the first insulating layer, The active layer thin film is patterned to form silicon islands in the display area, and the active layer thin film is removed corresponding to areas other than the silicon islands. 3. The method for fabricating an array substrate according to claim 1, wherein before the step of forming the first contact hole penetrating the active layer thin film and the first insulating layer, The source layer film is patterned to form a silicon island in the display area, and an etching guide portion is formed in the non-display area, and the etching guide portion corresponds to the position of the first contact hole. 4 . The method for fabricating an array substrate according to claim 3 , wherein the etching guide portion and the first insulating layer under the etching guide portion are patterned to form through the etching guide portion. 5 . part and the first contact hole of the first insulating layer. 5 . The method for fabricating an array substrate according to claim 4 , wherein the second lead covers the etching guide portion, and the facing area of the second lead on the substrate is larger than the etching area. 6 . The facing area of the guide portion on the substrate. 6 . The manufacturing method of the array substrate according to claim 1 , wherein the first insulating layer is formed by chemical vapor deposition, and the reactive gases used in the chemical vapor deposition include silane, ammonia and nitrogen. 7 . 7 . The method for fabricating an array substrate according to claim 6 , wherein the first insulating layer controls the flow rate of the silane to be in the range of 1860-2100 sccm in a high-speed film formation state, and the ammonia gas has a flow rate of 1860-2100 sccm. The value range of the flow rate is 15400-17300sccm; the value range of the flow rate of the silane is controlled to be 600-700sccm under the state of low-speed film formation, and the value range of the flow rate of the ammonia gas is 7600-9000sccm. 8 . The manufacturing method of the array substrate according to claim 1 , wherein the first contact hole is formed by an etching process, and when the active layer thin film is etched at a position corresponding to the first contact hole, the The feeding gas of the etching process includes sulfur hexafluoride gas, helium gas and chlorine gas. The flow rate of the chlorine gas is in the range of 2100sccm-2200sccm, the pressure in the etching process is in the range of 40-50mTorr, and the power in the etching process is in the range of 5000-6000W; in the corresponding first contact hole When the first insulating layer is etched at the position of the first insulating layer, the feeding gas of the etching process includes sulfur hexafluoride gas, oxygen and helium gas, and the flow rate of the sulfur hexafluoride ranges from 510 sccm to 600 sccm, and the helium The gas flow rate ranges from 600 sccm to 1000 sccm, and the pressure used in the etching process ranges from 160 to 170 mTorr. 9. The method for fabricating an array substrate according to any one of claims 1 to 8, wherein the method further comprises: Before the step of forming the first metal layer on the substrate, a third metal layer is formed on the substrate, and the third metal layer in the non-display area is patterned to form a third metal layer. lead; forming a second insulating layer covering the third lead on the substrate, the third lead and the second insulating layer being formed between the first metal layer and the substrate; The first insulating layer and the active layer thin film are formed on the second insulating layer, and the active layer thin film, the first insulating layer and the second thin film in the non-display area are The insulating layer is patterned to form a second contact hole penetrating the active layer thin film, the first insulating layer and the second insulating layer, and the etching rate of the second insulating layer is less than or equal to the first insulating layer. an etch rate of the insulating layer; The second lead is filled in the second contact hole and is electrically connected to the third lead. 10 . An array substrate, wherein the array substrate is formed by the method for fabricating an array substrate according to any one of claims 1 to 9 .

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