CN111987044A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Abstract

The present invention relates to a manufacturing method of a semiconductor device and a semiconductor device. The manufacturing method includes: obtaining a substrate on which an isolation structure for isolating an active region is formed; forming a P-type well region on the substrate; forming an active region on the P-type well region; A first side at the boundary of the structure and a second side opposite to the first side form a threshold voltage compensation region; a gate is formed; wherein the active region includes a source region and a drain region formed in the P-type well region; the first The connection line between one side and the second side is perpendicular to the conductive channel direction of the active region, and the hole concentration of the threshold voltage compensation region is greater than that of the P-type well region. By arranging threshold voltage compensation regions with higher hole concentration on opposite sides of the junction of the active region and the isolation structure, the negative charges induced by radiation in the region can be neutralized, forming a multi-threshold channel structure, which can avoid After the device is exposed to radiation, there are problems such as circuit leakage, setting the device to be turned on by mistake, and the circuit turning over by mistake.

Description

Manufacturing method of semiconductor device and semiconductor device

technical field

The present invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a semiconductor device and a semiconductor device.

Background technique

For integrated circuits used in ion radiation environments, such as in space, nuclear power plants, environmental detection and other fields, radiation will cause verification damage to integrated circuits. Therefore, it is necessary to strengthen the process of semiconductor devices to improve the radiation resistance of integrated circuits.

At present, the mainstream integrated circuits use CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) architecture. CMOS mainly has two types: NMOS and PMOS; and the ionization damage caused by radiation mainly forms ionized positive charges, so for PMOS , it will only cause the speed of the integrated circuit to slow down instantaneously, and will not produce destructive results, and it will self-recover as the compounding time lengthens. For NMOS, destructive damage will be formed on the integrated circuit.

The chips manufactured by the traditional standard CMOS integrated circuit manufacturing technology do not have the ability to resist radiation. The main reason is that the instantaneous threshold voltage shift caused by radiation will cause leakage of integrated circuits, or even mis-opening of devices and mis-turning of circuits.

SUMMARY OF THE INVENTION

Based on this, it is necessary to provide a new method for manufacturing a semiconductor device and a semiconductor device in response to the above-mentioned problems.

A method of manufacturing a semiconductor device, comprising:

A substrate is obtained, on which an isolation structure for isolating an active region is formed.

An active region is formed on the P-type well region.

A threshold voltage compensation region is formed at a first side at the boundary of the active region and the isolation structure and a second side opposite the first side.

A gate is formed over the region between the source and drain regions.

The active region includes a source region and a drain region formed in the P-type well region; the connection between the first side and the second side is perpendicular to the direction of the conductive channel of the active region, and the threshold voltage compensation region is The hole concentration is greater than that of the P-type well region.

In one embodiment, the gate includes a gate oxide layer formed on the substrate and a polysilicon gate formed on the gate oxide layer, and the step of forming the gate includes forming the gate oxide layer using a chemical vapor deposition process.

In one of the embodiments, the process temperature of chemical vapor deposition is greater than or equal to 450 degrees Celsius and less than or equal to 800 degrees Celsius.

In one of the embodiments, the chemical vapor deposition process gas includes dichlorine monoxide and dichlorosilane.

In one embodiment, the step of forming the gate oxide layer is subsequent to the step of forming the threshold voltage compensation region.

In one of the embodiments, the threshold voltage compensation region is formed by an ion implantation process, and the implantation material for the ion implantation includes at least one of boron, boron difluoride, and indium.

A semiconductor device, comprising:

A substrate, the substrate includes an active region, the active region includes a source region and a drain region.

A P-type well region is located on the substrate.

The isolation structure is used to isolate the active area.

The threshold voltage compensation region is arranged on the first side and the second side opposite to the first side at the boundary between the active region and the isolation structure, and the connection between the first side and the second side is perpendicular to the direction of the conductive channel of the active region , the hole concentration of the threshold voltage compensation region is greater than that of the P-type well region.

The gate is disposed over the region between the source region and the drain region.

In one of the embodiments, the isolation structure is a shallow trench isolation structure.

In one of the embodiments, the active region is surrounded in cross-section by the isolation structure to form a closed pattern, and the first side and the second side are opposite sides of the closed pattern.

In one of the embodiments, the semiconductor device is a complementary metal oxide semiconductor device.

The above-mentioned semiconductor device and its manufacturing method can neutralize the negative charge induced by radiation in the region by arranging the threshold voltage compensation region with higher hole concentration on the opposite sides of the junction of the active region and the isolation structure. The multi-threshold channel structure can avoid problems such as circuit leakage after the device is exposed to radiation, setting the device to be turned on by mistake, and the circuit turning over by mistake.

Description of drawings

Fig. 1 is the plane layout of NMOS;

FIG. 2 is a cross-sectional view of the NMOS of FIG. 1;

Fig. 3 is the sectional schematic diagram along X-X line in Fig. 1;

Fig. 4 is a schematic cross-sectional view along line Y-Y in Fig. 1;

5 is a flowchart of a method for manufacturing a semiconductor device in one embodiment;

FIG. 6 is a flow chart of forming an isolation structure in one embodiment;

7 is a schematic diagram of a threshold voltage compensation region in an embodiment;

FIG. 8 is a plan layout corresponding to the structure shown in FIG. 7 .

Detailed ways

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the related drawings. Preferred embodiments of the invention are shown in the accompanying drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown may be expected due to, for example, manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

The semiconductor field vocabulary used in this paper is the technical vocabulary commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, the P+ type represents the heavily doped P-type, and the P-type represents the medium P-type with doping concentration, P-type representing P-type with light doping concentration, N+-type representing N-type with heavy doping concentration, N-type representing N-type with medium doping concentration, N-type representing lightly doping concentration Type N.

The chips manufactured by the traditional standard CMOS integrated circuit manufacturing technology do not have the ability to resist radiation. The main reason is that the instantaneous threshold voltage shift caused by radiation will cause leakage of integrated circuits, or even mis-opening of devices and mis-turning of circuits. The planar layout of the conventional NMOS is shown in FIG. 1 , and the cross-sectional view thereof is shown in FIG. 2 .

The structure in FIGS. 1-2 includes P-well region 102, active region 104, drain region 106, source region 108, gate region 110, contact hole 112, polysilicon gate 114, gate oxide 116, substrate 118 and Shallow trench isolation (STI) 120, wherein the polysilicon gate 114 and the gate oxide layer 116 together form the gate region 110 of the device.

In the radiation environment, the filler-silicon dioxide medium in the shallow trench isolation will generate electron-hole pairs, because the electrons can escape across the barrier of silicon dioxide and silicon when they obtain a certain activation energy, thus A positive charge is left in the STI silicon dioxide dielectric, and the excess positive charge will invert the adjacent silicon surface to form a leakage channel (see the direction of the arrow in Figure 1), causing the lateral and vertical STI isolation of the device to fail. Since the shallow trench isolation oxide layer mainly generates additional positive charges in the radiation environment, which induces negative charges on the silicon surface, the threshold voltage of the device in the boundary region of the active region is greatly reduced, forming a leakage path, isolation failure, and device misoperation. .

The radiation affected area is mainly the boundary area between the active area and the isolation structure. FIG. 3 is a schematic cross-sectional view along the X-X line in FIG. The isolation structures 306 generate additional positive charges in the radiation environment. 4 is a schematic cross-sectional view along the line Y-Y in FIG. 1, including a polysilicon gate 402, a gate oxide layer 404, a source region 406, a drain region 408, a shallow trench isolation structure 410 and a radiation affected region 412; since CMOS is a planar device, it works The current flows laterally, so only the communication (gate area coverage) area will have an effect on the threshold voltage, so the leakage path is limited to the area indicated by the arrow in Figure 1.

As shown in Figure 5, the present invention provides a method for manufacturing a semiconductor device, comprising:

S102, obtaining a substrate on which an isolation structure for isolating an active region is formed.

S104, a P-type well region is formed on the substrate.

S106, forming an active region on the P-type well region.

S108, forming a threshold voltage compensation region.

A threshold voltage compensation region is formed at a first side at the boundary of the active region and the isolation structure and a second side opposite the first side.

S110, forming a gate over a region between the source region and the drain region.

In one embodiment, the structure after step S110 is completed may refer to FIG. 7 , and FIG. 8 is a plan layout corresponding to the structure shown in FIG. 7 . The active region includes a source region 705 and a drain region 707 formed in the P-type well region 703 . The threshold voltage compensation region 708 is formed on the first side and the second side opposite to the first side at the boundary between the active region and the isolation structure 710, and the connection between the first side and the second side is perpendicular to the conductive channel of the active region In the direction, the hole concentration of the threshold voltage compensation region 708 is greater than that of the P-type well region 703 , and the threshold voltage compensation region 708 is formed on both sides of the normal threshold voltage region 706 . A gate is formed over the region between the source and drain regions. In the embodiments shown in FIGS. 7 and 8 , the gate includes a gate oxide layer 704 formed on the substrate and a polysilicon gate 702 formed on the gate oxide layer 704 .

The above-mentioned manufacturing method of a semiconductor device can neutralize the damage caused in the region by adding a threshold voltage compensation region with a higher hole concentration on the first side at the boundary between the active region and the isolation structure and on the second side opposite to the first side. The negative charge induced by the radiation forms a multi-threshold channel structure, which can avoid problems such as circuit leakage after the device is exposed to radiation, setting the device to be turned on by mistake, and the circuit turning over by mistake.

In one embodiment, the threshold voltage compensation region is formed by an ion implantation process. In one embodiment, the implantation material for ion implantation includes at least one of P-type implantation materials such as boron, boron difluoride, and indium.

As shown in FIG. 6 , in one embodiment, the isolation structure is a shallow trench isolation structure, and the formation of the isolation structure includes the following process steps:

S202, forming an isolation oxide layer.

S204, depositing to form a nitride protective layer.

S206, the shallow trench isolation trench is formed by photolithography and etching.

S208, forming trench oxide.

S210, removing the nitride protective layer.

In one embodiment, the step of forming the gate electrode in step S110 includes forming the gate oxide layer 704 using a chemical vapor deposition process.

In the corresponding embodiments of the present application, the gate oxide manufacturing process is improved, and the chemical vapor deposition (CVD, Chemical Vapor Deposition) process is used to replace the conventional furnace gate oxide manufacturing process in the current device manufacturing process, so as to obtain a low thermal budget lining No consumed gate oxide at the bottom.

In some embodiments, step S108 is to add additional P-type to the first side at the boundary between the active region and the isolation structure and the second side opposite to the first side (ie, the region 708 in FIG. 7 ) through an ion implantation process Doping to form a threshold voltage compensation region with a higher hole concentration, then for the embodiment in which the step of forming the gate oxide layer is after the step of forming the threshold voltage compensation region, the high temperature process in the gate oxide manufacturing process (low temperature film formation defect density is high , poor compactness and cannot be used as a gate oxide dielectric layer) will affect the distribution of doped ions, making the highly doped region diffuse to the channel region, on the one hand, reducing the impurity concentration of the highly doped region and causing doping failure, on the other hand On the one hand, the channel doping in the normal threshold voltage region is uneven, and the threshold voltage is unstable. The gate oxide is fabricated by chemical vapor deposition, which can reduce the negative impact of the gate oxide process on the doping profile because the process can use a lower process temperature than the furnace gate oxide fabrication process (ie, thermal oxidation).

Table 1

As shown in Table 1, it is a comparison table between the conventional furnace tube gate oxide manufacturing process and the chemical vapor deposition gate oxide manufacturing process. It can be seen from the comparison table that compared with the chemical vapor deposition process, the conventional furnace tube process has a very high manufacturing thermal budget, and The conventional furnace tube process has poor film forming density and many defects. The inherent strong adsorption capacity of silicon dioxide to substrate impurities will seriously affect the multi-threshold channel distribution. At the same time, the furnace tube process needs to consume the silicon substrate when manufacturing the oxide layer, increasing the number of steps The difficulty of forming multiple threshold voltages in S108 is overcome by the chemical vapor deposition process.

Due to the high defect density and poor compactness of the chemical vapor deposition gate oxide manufacturing process at low temperature, it is generally not used as a gate oxide dielectric layer. In one embodiment, the process temperature of the chemical vapor deposition gate oxide manufacturing process is greater than or equal to 450 degrees Celsius and less than or equal to 800 degrees Celsius, and preferably the process temperature is 780 degrees Celsius; in the actual process, the chemical vapor deposition gate oxide can be adjusted according to product requirements. The process temperature of the manufacturing process, such as 500 degrees Celsius, 600 degrees Celsius, etc. The process gas of chemical vapor deposition includes dichlorine monoxide and dichlorodihydrogen silicon, wherein the volume flow ratio per unit time of dichlorine monoxide and dichlorodihydrogen silicon in the deposition step is greater than or equal to 1.8:1 and less than or equal to 3.5:1 .

The present invention also provides a semiconductor device, comprising:

a substrate, the substrate includes an active region, the active region includes a source region and a drain region;

P-type well region, located on the substrate;

an isolation structure for isolating the active region;

a threshold voltage compensation region, disposed on a first side and a second side opposite to the first side at the boundary between the active region and the isolation structure, and the connection line between the first side and the second side is perpendicular to the The conductive channel direction of the active region, the hole concentration of the threshold voltage compensation region is greater than the hole concentration of the P-type well region;

a gate disposed above the region between the source region and the drain region.

The above-mentioned semiconductor device and its manufacturing method can neutralize the negative charge induced by radiation in the region by arranging the threshold voltage compensation region with higher hole concentration on the opposite sides of the junction of the active region and the isolation structure. The multi-threshold channel structure can avoid problems such as circuit leakage after the device is exposed to radiation, setting the device to be turned on by mistake, and the circuit turning over by mistake.

In one embodiment, the isolation structure is a shallow trench isolation structure.

In one embodiment, the active region is surrounded in cross-section by the isolation structure to form a closed pattern, and the first and second sides are opposite sides of the closed pattern.

In one embodiment, the semiconductor device is a complementary metal oxide semiconductor device.

In one embodiment, the structure of the semiconductor device of the present application can be referred to FIG. 7 and FIG. 8 .

The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above-described embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be regarded as the scope described in this specification.

The above-mentioned embodiments only represent several embodiments of the present invention, and the descriptions thereof are specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be noted that, for those skilled in the art, without departing from the concept of the present invention, several modifications and improvements can be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims (10)

1. A method for manufacturing a semiconductor device, comprising: obtaining a substrate on which an isolation structure for isolating an active region is formed; forming a P-type well region on the substrate; forming an active region on the P-type well region; forming a threshold voltage compensation region on a first side at the boundary of the active region and the isolation structure and a second side opposite the first side; forming a gate over the region between the source region and the drain region; Wherein, the active region includes the source region and the drain region formed in the P-type well region; the connection between the first side and the second side is perpendicular to the conductive channel of the active region In the channel direction, the hole concentration of the threshold voltage compensation region is greater than that of the P-type well region. 2 . The method according to claim 1 , wherein the gate electrode comprises a gate oxide layer formed on a substrate and a polysilicon gate formed on the gate oxide layer, and the step of forming the gate electrode comprises: 3 . The gate oxide layer is formed using a chemical vapor deposition process. 3 . The method according to claim 2 , wherein the process temperature of the chemical vapor deposition is greater than or equal to 450 degrees Celsius and less than or equal to 800 degrees Celsius. 4 . 4. The method of claim 2, wherein the chemical vapor deposition process gas comprises dichlorine monoxide and dichlorosilane. 5 . The method of claim 2 , wherein the step of forming a gate oxide layer is after the step of forming a threshold voltage compensation region. 6 . 6 . The method according to claim 1 , wherein the threshold voltage compensation region is formed by an ion implantation process, and the implantation material of the ion implantation comprises at least one of boron, boron difluoride, and indium. 7 . 7. A semiconductor device comprising: a substrate, the substrate includes an active region, the active region includes a source region and a drain region; P-type well region, located on the substrate; an isolation structure for isolating the active region; a threshold voltage compensation region, disposed on a first side and a second side opposite to the first side at the boundary between the active region and the isolation structure, and the connection line between the first side and the second side is perpendicular to the The conductive channel direction of the active region, the hole concentration of the threshold voltage compensation region is greater than the hole concentration of the P-type well region; a gate disposed above the region between the source region and the drain region. 8. The device of claim 7, wherein the isolation structure is a shallow trench isolation structure. 9 . The device of claim 7 , wherein the active region is surrounded by the isolation structure in cross-section to form a closed pattern, and the first and second sides are of the closed pattern. 10 . opposite sides. 10. The device of claim 7, wherein the semiconductor device is a complementary metal oxide semiconductor device.

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