CN112036106B - Signal processing method, device, platform, storage medium and electronic equipment - Google Patents
Signal processing method, device, platform, storage medium and electronic equipment Download PDFInfo
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Abstract
The application provides a signal processing method, a signal processing device, a signal processing platform, a storage medium and an electronic device. The method comprises the following steps: obtaining relevant parameters of a reference clock simulation signal belonging to a clock domain; automatically generating a test clock simulation signal which belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal according to the related parameters; and stimulating the simulation circuit in the simulation platform by using the test clock simulation signal so as to enable the simulation circuit to work in the clock domain, wherein the simulation circuit is also in communication connection with other simulation circuits working in other clock domains in the simulation platform. It can be understood that, because the test clock simulation signal which belongs to the same clock domain as the reference clock simulation signal and has different waveform characteristics is automatically generated in the simulation environment, the waveform characteristics do not need to be adjusted manually, and therefore, the loss analysis of the signal synchronizer can be efficiently performed in the early stage of circuit design.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a signal processing method, an apparatus, a platform, a storage medium, and an electronic device.
Background
With the increasing complexity of integrated circuits, the number of clock signals in a single chip is increasing, some clock signals belong to the same clock domain, some clock signals belong to different clock domains, and the clock signals crossing the clock domains respectively excite corresponding circuits. For these energized circuits, the tester needs to analyze the absence of the signal synchronizer, i.e. analyze the signals crossing the clock domain between these circuits, and add the signal synchronizer to these signals to ensure that these circuits can interact normally.
Currently, there are two analysis methods for loss of signal synchronizer:
1. the analysis was performed using existing tools.
For example, the circuit analysis function provided by an EDA (Electronic design automation) tool may be used to statically analyze the signal synchronizer condition between each design circuit across clock domains, so as to obtain an analysis report. Since all suspected signals that require the addition of the signal synchronizer are indicated in the analysis report, the tester needs to perform further screening based on the analysis report.
It can be understood that the analysis using the EDA tool is premised on that the design of each design circuit is nearly completed, and at the later stage of the project, once a problem is screened, the time for project casting is likely to be affected, and the analysis report from the EDA tool is usually very tedious, and the designer needs to screen the signal path with the real synchronizer missing from the lengthy report, and the efficiency and accuracy of manual screening are very low.
2. And analyzing by utilizing a simulation environment.
For example, in the simulation link of circuit design, a tester is required to test the simulation circuits of the circuits so as to analyze the loss of the signal synchronizer; for example, a clock simulation signal belonging to a clock domain A is used for exciting an A simulation circuit a, a clock simulation signal belonging to a clock domain B different from the clock domain A is used for exciting a simulation circuit B, and software is used for analyzing whether the simulation circuit a and the simulation circuit B communicate according to a set protocol or rule; if the simulation circuit a and the simulation circuit b cannot communicate according to a predetermined protocol or rule, an interaction error is indicated, and a signal synchronizer is likely to be added to a signal corresponding to the error.
It can be understood that the problem of the loss of the signal synchronizer can be analyzed in the early stage of circuit design through simulation analysis, and the problem found in the later stage is avoided. However, in order to analyze each signal across the clock domains, it needs to use the clock signals with various waveform characteristics to perform testing, so that the tester needs to adjust the clock signal of the same clock domain to each waveform characteristic for testing, which results in an increase in workload of the tester and also a low efficiency.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a signal processing method, a signal processing apparatus, a signal processing platform, a signal processing storage medium, and an electronic device, which are capable of efficiently analyzing a signal synchronizer deficiency in an early stage of circuit design.
In a first aspect, an embodiment of the present application provides a signal processing method, where the method includes: obtaining relevant parameters of a reference clock simulation signal belonging to a clock domain; automatically generating a test clock simulation signal which belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal according to the related parameters; and stimulating the simulation circuit in the simulation platform by using the test clock simulation signal so as to enable the simulation circuit to work in the clock domain, wherein the simulation circuit is also in communication connection with other simulation circuits working in other clock domains in the simulation platform.
In the embodiment of the application, because the test clock simulation signal which belongs to the same clock domain as the reference clock simulation signal and has different waveform characteristics is automatically generated in the simulation environment, the waveform characteristics do not need to be adjusted manually, and the loss analysis of the signal synchronizer can be efficiently carried out at the early stage of circuit design.
With reference to the first aspect, in a first possible implementation manner, the related parameters include: the frequency of the reference clock simulation signal automatically generates a test clock simulation signal which belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal according to the relevant parameters, and the method comprises the following steps: shifting the frequency up or down by a preset value to obtain the shifted frequency; and generating the test clock simulation signal according to the frequency after the offset.
In the embodiment of the application, the waveform characteristics can be conveniently adjusted through frequency offset so as to conveniently generate the test clock simulation signal.
With reference to the first aspect, in a second possible implementation manner, the related parameters include: the frequency of the reference clock simulation signal automatically generates a test clock simulation signal which belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal according to the relevant parameters, and the method comprises the following steps: sequentially shifting the frequency by a preset first numerical value and a preset second numerical value by taking each preset period as a unit to obtain the shifted frequency of each period, wherein the first numerical value is different from the second numerical value; and generating the test clock simulation signal according to the frequency after the offset.
In the embodiment of the application, the test clock simulation signal is generated at the frequency after each period is shifted, so that the frequency of the test clock simulation signal is different in different periods, the randomness of waveform characteristic change is increased, and whether a signal synchronizer is lacked between the simulation circuit and other simulation circuits can be tested more quickly.
With reference to the first aspect, in a third possible implementation manner, the related parameters include: the method for automatically generating the test clock simulation signal which belongs to the clock domain and has the waveform characteristics different from that of the reference clock simulation signal according to the relevant parameters at the arrival time point of the clock edge of the reference clock simulation signal in each clock cycle comprises the following steps: adjusting the arrival time point through dithering to obtain an adjusted arrival time point; and generating the test clock simulation signal according to the adjusted arrival time point.
In the embodiment of the application, since the jitter is characterized by changing the arrival time point of the clock edge, the waveform characteristics can be changed conveniently, so as to realize the convenient generation of the test clock simulation signal.
With reference to the first aspect, in a fourth possible implementation manner, the related parameters include: the frequency of the reference clock simulation signal automatically generates a test clock simulation signal which belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal according to the relevant parameters, and the method comprises the following steps: shifting the frequency up or down by a preset value to obtain the shifted frequency; adjusting the arrival time point of the clock edge in each clock period corresponding to the shifted frequency through dithering to obtain the adjusted arrival time point; and generating the test clock simulation signal according to the adjusted arrival time point.
In the embodiment of the application, on the basis of frequency deviation, jitter is added, the waveform characteristic change can be increased, and therefore whether a signal synchronizer is lacked between the simulation circuit and other simulation circuits or not can be tested more quickly.
With reference to the first aspect, in a fifth possible implementation manner, the related parameters include: the frequency of the reference clock simulation signal automatically generates a test clock simulation signal which belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal according to the relevant parameters, and the method comprises the following steps: sequentially shifting the frequency by a preset first numerical value and a preset second numerical value by taking each preset period as a unit to obtain the shifted frequency of each period, wherein the first numerical value is different from the second numerical value; adjusting the arrival time point of the clock edge in each clock period corresponding to the shifted frequency through dithering to obtain the adjusted arrival time point; and generating the test clock simulation signal according to the adjusted arrival time point.
In the embodiment of the application, on the basis of shifting the frequency in each period, the jitter is also added, which can further increase the randomness of the waveform characteristic variation, so that whether a signal synchronizer is lacked between the simulation circuit and other simulation circuits can be tested more quickly.
With reference to the first aspect, in a sixth possible implementation manner, the method applied to a clock generation model to obtain relevant parameters of a reference clock simulation signal belonging to a clock domain includes: detecting an output interface of a phase-locked loop of a clock generation simulation circuit in the simulation platform, and acquiring the frequency of a high-frequency simulation clock signal output by the phase-locked loop; detecting the configuration of the clock generation simulation circuit, and acquiring the frequency dividing ratio of the clock generation simulation circuit and the arrival time point of the clock edge of the reference clock simulation signal in each clock cycle; and determining the frequency of the reference clock simulation signal according to the frequency dividing ratio and the frequency of the high-frequency simulation clock signal.
In the embodiment of the application, the test clock simulation signal is generated by detecting the frequency division input interface and the simulation configuration of the clock generation simulation circuit through the clock generation model, the original simulation test framework is basically not required to be adjusted, the plugging performance is very strong, and the practical application is convenient.
With reference to the sixth possible implementation manner of the first aspect, in a seventh possible implementation manner, stimulating a simulation circuit in a simulation platform by using the test clock simulation signal includes: and forcing the test clock simulation signal to the output of the clock generation simulation circuit to replace the original output of the clock generation simulation circuit, so that the test clock simulation signal is output to the simulation circuit in the simulation platform through the clock generation simulation circuit.
In the embodiment of the application, the test clock simulation signal is excited in a mode of forcing the clock generation simulation circuit, in other words, when the test clock simulation signal needs to be output, the test clock simulation signal is output to the simulation circuit through the output of the forced clock generation simulation circuit, and when the test clock simulation signal does not need to be output, the test clock simulation signal is not forced, so that the clock generation simulation circuit outputs the generated reference clock simulation signal, the flexible switching of the output signal is realized, and the practical application is more convenient.
With reference to the seventh possible implementation manner of the first aspect, in an eighth possible implementation manner, the forcing the test clock simulation signal to the output of the clock generation simulation circuit includes: forcing the test clock emulation signal onto the output of the clock generation emulation circuit in response to a user-performed signal input operation.
In the embodiment of the application, whether forced output is needed or not is controlled in an artificial mode, so that the forced output is more controllable.
With reference to the first aspect, in a ninth possible implementation manner, the method is applied to a clock generation model, and when a simulation circuit in a simulation platform is stimulated by using the test clock simulation signal, the method further includes: and controlling the other simulation circuits to work in the other clock domains.
In the embodiment of the application, the clock generation model can be applied to one simulation circuit working in the corresponding clock domain and can also be applied to other simulation circuits working in the corresponding other clock domains, so that the one-to-many application of the model is realized, and the test efficiency is further improved.
With reference to the ninth possible implementation manner of the first aspect, in a tenth possible implementation manner, obtaining other relevant parameters of other reference clock simulation signals belonging to other clock domains; generating other test clock simulation signals which belong to other clock domains and have waveform characteristics different from those of the other reference clock simulation signals according to the other related parameters; and exciting the other simulation circuits by using the other test clock simulation signals.
In the embodiment of the application, because the other simulation circuits are excited by the other test clock simulation signals with random waveform characteristics, the difference of the waveform characteristics of the signals of the excitation simulation circuit and the other simulation circuits is further increased, and whether the signal synchronizer is lacked between the simulation circuit and the other simulation circuits can be tested more quickly.
In a second aspect, an embodiment of the present application provides a signal processing apparatus, including: the parameter acquisition module is used for acquiring related parameters of a clock simulation signal belonging to a clock domain; the signal processing module is used for automatically generating a test clock simulation signal which belongs to the clock domain and has different waveform characteristics from the reference clock simulation signal according to the related parameters; and stimulating the simulation circuit in the simulation platform by using the test clock simulation signal so as to enable the simulation circuit to work in the clock domain, wherein the simulation circuit is also in communication connection with other simulation circuits working in other clock domains in the simulation platform.
With reference to the second aspect, in a first possible implementation manner, the related parameters include: the frequency of the reference clock simulation signal, the signal processing module is used for shifting the frequency up or down by a preset value to obtain the shifted frequency; and generating the test clock simulation signal according to the frequency after the offset.
With reference to the second aspect, in a second possible implementation manner, the related parameters include: the frequency of the reference clock simulation signal, the signal processing module, configured to offset the frequency sequentially by a preset first numerical value and a preset second numerical value with each preset period as a unit, to obtain the offset frequency of each period, where the first numerical value is different from the second numerical value; and generating the test clock simulation signal according to the frequency after the offset.
With reference to the second aspect, in a third possible implementation manner, the related parameters include: the signal processing module is configured to automatically generate, according to the relevant parameter, a test clock simulation signal that belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal, and includes: adjusting the arrival time point through dithering to obtain an adjusted arrival time point; and generating the test clock simulation signal according to the adjusted arrival time point.
With reference to the second aspect, in a fourth possible implementation manner, the related parameters include: the frequency of the reference clock simulation signal, the signal processing module is used for shifting the frequency up or down by a preset value to obtain the shifted frequency; adjusting the arrival time point of the clock edge in each clock period corresponding to the shifted frequency through dithering to obtain the adjusted arrival time point; and generating the test clock simulation signal according to the adjusted arrival time point.
With reference to the second aspect, in a fifth possible implementation manner, the related parameters include: the signal processing module is configured to sequentially shift the frequency by a preset first numerical value and a preset second numerical value by taking each preset period as a unit, and obtain a shifted frequency of each period, where the first numerical value is different from the second numerical value; adjusting the arrival time point of the clock edge in each clock period corresponding to the shifted frequency through dithering to obtain the adjusted arrival time point; and generating the test clock simulation signal according to the adjusted arrival time point.
With reference to the second aspect, in a sixth possible implementation manner, the apparatus is applied to a clock generation model, and the parameter obtaining module is configured to detect an output interface of a phase-locked loop of a clock generation simulation circuit in the simulation platform, and obtain a frequency of a high-frequency simulation clock signal output by the phase-locked loop; detecting the configuration of the clock generation simulation circuit, and acquiring the frequency dividing ratio of the clock generation simulation circuit and the arrival time point of the clock edge of the reference clock simulation signal in each clock cycle; and determining the frequency of the reference clock simulation signal according to the frequency dividing ratio and the frequency of the high-frequency simulation clock signal.
With reference to the sixth possible implementation manner of the second aspect, in a seventh possible implementation manner, the signal processing module is configured to force the test clock simulation signal to the output of the clock generation simulation circuit to replace an original output of the clock generation simulation circuit, so that the test clock simulation signal is output to a simulation circuit in the simulation platform through the clock generation simulation circuit.
With reference to the seventh possible implementation manner of the second aspect, in an eighth possible implementation manner, the signal processing module is configured to force the test clock simulation signal to the output of the clock generation simulation circuit in response to a signal input operation performed by a user.
With reference to the second aspect, in a ninth possible implementation manner, the apparatus is applied to a clock generation model, and when the signal processing module excites a simulation circuit in a simulation platform with the test clock simulation signal, the signal processing module is further configured to control the other simulation circuit to operate in the other clock domain.
With reference to the ninth possible implementation manner of the second aspect, in a tenth possible implementation manner, the signal processing module is configured to obtain other relevant parameters of other reference clock simulation signals belonging to other clock domains; generating other test clock simulation signals which belong to other clock domains and have waveform characteristics different from those of the other reference clock simulation signals according to the other related parameters; and exciting the other simulation circuits by using the other test clock simulation signals.
In a third aspect, an embodiment of the present application provides a simulation platform, where the platform includes: the simulation circuit comprises a simulation circuit, a clock generation simulation circuit connected with the simulation circuit, a clock generation model connected with the clock generation simulation circuit, and other simulation circuits connected with the simulation circuit, wherein the other simulation circuits are in other clock domains; wherein the clock generation model is configured to perform the signal processing method according to the first aspect or any one of the possible implementation manners of the first aspect.
With reference to the third aspect, in a first possible implementation manner, the clock generation model is connected to the clock generation simulation circuit by way of instantiation.
In the embodiment of the application, the deployment and connection of the clock generation model can be rapidly realized through an instantiation mode.
In a fourth aspect, the present application provides a computer-readable storage medium having a computer-executable non-volatile program code, where the program code causes the computer to execute the signal processing method according to the first aspect or any one of the possible implementation manners of the first aspect.
In a fifth aspect, an embodiment of the present application provides an electronic device, including: a memory for storing a program; a bus; a processor connected to the memory through the bus, the processor being configured to run the program to perform the signal processing method according to the first aspect or any one of the possible implementations of the first aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for a person having ordinary skill in the art to obtain other related drawings without creative efforts.
Fig. 1 is a first structural block diagram of a simulation platform according to an embodiment of the present disclosure;
fig. 2 is a second structural block diagram of a simulation platform according to an embodiment of the present disclosure;
fig. 3 is a flowchart of a signal processing method according to an embodiment of the present application;
fig. 4 is a block diagram of a signal processing apparatus according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
Referring to fig. 1, an embodiment of the present application provides a simulation platform 10, where the simulation platform 10 may be deployed on an electronic device or a plurality of electronic devices, and the electronic device may be a terminal or a server, where the terminal may be a mobile phone, a tablet computer, a Personal Digital Assistant (PDA), a Point of Sales (POS), or the like; the server may be a single server or a server group (the server group may be centralized or distributed).
For example, the simulation platform 10 may include: a plurality of clock generation simulation circuits 12 and a plurality of simulation circuits 11 under test, the plurality of simulation circuits 11 being communicatively connected to each other, and further comprising: the clock generation model 13.
In this embodiment, a tester may configure the simulation platform 10 according to actual test requirements.
Specifically, for the simulation circuit 11:
the tester can establish the simulation circuit 11 corresponding to each design circuit under the design index according to the design index preset in practice, so that each simulation circuit 11 can simulate the actual design circuit, and the rule is carried out according to the communication interaction under the design index.
For the clock generation simulation circuit 12:
the tester can configure a corresponding number of the clock generation simulation circuits 12 according to the number of the simulation circuits 11, where the configuration of each clock generation simulation circuit 12 is to configure the frequency of the simulation signal input to the clock generation simulation circuit 12, the frequency of the high-frequency simulation clock signal output by the phase-locked loop in the clock generation simulation circuit 12, the frequency division ratio of the clock generation simulation circuit 12, and the arrival time point of the clock edge of the reference clock simulation signal that needs to be generated by the clock generation simulation circuit 12 in each clock cycle. And, the tester also configures each clock generation simulation circuit 12 to be connected with a corresponding simulation circuit 11 according to actual test requirements, so that each clock generation simulation circuit 12 can generate a reference clock simulation signal belonging to a corresponding clock domain according to its own configuration, and input the generated reference clock simulation signal to a corresponding connected simulation circuit 11 to excite the simulation circuit 11 under the condition that no clock generation model 13 is connected (the condition that the clock generation model 13 is connected will be described later).
For the clock generation model 13:
in the configuration phase of the simulation platform 10, the clock generation model 13 is only deployed in the simulation platform 10, but has no connection relationship with each clock generation simulation circuit 12 in the simulation platform 10, and cannot interact with each clock generation simulation circuit 12. Therefore, in the configuration phase of the simulation platform 10, a tester may establish a connection with the corresponding clock generation simulation circuit 12 in the simulation platform 10 by instantiating the clock generation model 13, for example, the tester may initiate instantiation of the clock generation model 13 in a macro-defined manner according to the test requirement of the simulation circuit to be tested, so as to correspondingly generate an instantiated module connected with the clock generation simulation circuit 12 in the simulation test platform. In other words, the subsequent testing of the simulation circuit 11 is realized by instantiating the clock generation model 13.
It should be noted that, according to actual test requirements, a tester may configure instantiated modules for at least a portion of the clock generation simulation circuits 12 in the simulation platform 10. For these clock generation simulation circuits 12, which require the configuration of instantiated modules, the instantiated modules are typically in a one-to-one relationship with these clock generation simulation circuits 12, i.e., each instantiated module is connected to a corresponding one of the clock generation simulation circuits 12.
After the configuration of the simulation platform 10 is completed, the simulation platform 10 can be put into practical operation. In the actual operation stage, on one hand, if the simulation platform 10 has the simulation circuit 11 excited by the clock generation simulation circuit 12, the simulation circuit 11 operates under the excitation of the reference clock simulation signal generated by the clock generation simulation circuit 12 corresponding to the simulation platform 11; on the other hand, since the configuration of the instantiated module corresponding to the test requirement can be generated in the instantiation process, the instantiated module can obtain the corresponding related parameters from the corresponding clock generation simulation circuit 12 by using the configuration, generate the test clock simulation signal which belongs to the same clock domain as the reference clock simulation signal and has different waveform characteristics, and excite the corresponding simulation circuit 11 by using the test clock simulation signal, wherein the related parameters are the parameters of the reference clock simulation signal which the clock generation simulation circuit 12 needs to generate.
It should be noted that, the clock generation simulation circuit 12 and the simulation circuit 11 in the simulation platform 10 are both the current conventional simulation circuit 11, in other words, before the clock generation model 13 is deployed, the simulation platform 10 is a conventional platform architecture, which can use the conventional reference clock simulation signal generated by each clock generation simulation circuit 12, and although it can test whether there is a signal synchronizer missing between each simulation circuit 11 to some extent, because the parameter of the reference clock simulation signal is relatively fixed, the probability of detecting the signal synchronizer missing is very low. By deploying the clock generation model 13 into the simulation platform 10, the test clock simulation signals with various waveform characteristics perform the signal synchronizer missing test on each simulation circuit 11. Therefore, this implementation does not require adjustment of the conventional simulation platform 10, facilitating practical large-scale applications.
Of course, the above-mentioned implementation of testing by using the instantiated module of the deployed clock generation model 13 is only an exemplary manner of this embodiment, and is not limited, for example, as shown in fig. 2, it may also be implemented by modifying the conventional clock generation simulation circuit 12, so that the modified clock generation simulation circuit 12 itself can generate a corresponding test clock simulation signal based on the relevant parameter, and excite the corresponding simulation circuit 11 by using the test clock simulation signal.
The details of how the clock generation model 13 achieves the acquisition of the relevant parameters, the generation of the test clock simulation signal, and the activation of the simulation circuit 11 will be described below by way of method embodiments.
Referring to fig. 3, the embodiment of the present application provides a signal processing method, wherein the signal processing method may be executed by an instantiated module of the clock generation model 13 when the test is implemented by deploying the clock generation model 13, and the signal processing method may be executed by the improved clock generation simulation circuit 12 when the test is implemented by deploying the improved clock generation simulation circuit 12.
For example, the flow of the signal processing method may include:
step S100: obtaining relevant parameters of a reference clock simulation signal belonging to a clock domain;
step S200: automatically generating a test clock simulation signal which belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal according to the related parameters;
step S300: and stimulating the simulation circuit in the simulation platform by using the test clock simulation signal so as to enable the simulation circuit to work in the clock domain, wherein the simulation circuit is also in communication connection with other simulation circuits working in other clock domains in the simulation platform.
It is understood that the principle of the method performed by the instantiated module of the clock generation model 13 is substantially the same as that performed by the modified clock generation simulation circuit 12, and for convenience of description, the instantiated module of the clock generation model 13 is taken as an example to perform the method in the following of the present embodiment, and the principle is described in detail.
It should be noted that the other simulation circuit 11 may be excited by the reference clock simulation signal generated by the clock generation simulation circuit 12 to operate in other clock domains. Since this excitation method is relatively conventional, the present embodiment will not be described in detail to avoid the problem of the description. In addition, the other simulation circuits 11 may be excited by other test clock simulation signals generated by new instantiation modules of the clock generation model 13, that is, the clock generation model 13 obtains other relevant parameters of other reference clock simulation signals belonging to other clock domains; and then automatically generating other test clock simulation signals which belong to other clock domains and have waveform characteristics different from those of other reference clock simulation signals according to other related parameters, and finally exciting the other simulation circuits 11 by using the other test clock simulation signals so as to enable the other simulation circuits to work in the other clock domains. Also, since the principle of this method is the same as that of the clock generation model 13 exciting the simulation circuit 11, the present embodiment will not be described in detail to avoid the description.
Step S100: the relevant parameters of a reference clock simulation signal belonging to a clock domain are obtained.
As a first way, if the instantiated module of the clock generation model 13 needs to generate the test clock simulation signal by frequency offset, the instantiated module of the clock generation model 13 can detect the output interface of the phase-locked loop in the clock generation simulation circuit 12 and the configuration in the clock generation simulation circuit 12 connected correspondingly based on its own configuration. So as to obtain the frequency of the high-frequency simulation clock signal output by the phase-locked loop in the clock generation simulation circuit 12 through the detection output interface, and obtain the frequency dividing ratio of the clock generation simulation circuit 12 through detecting the configuration in the clock generation simulation circuit 12.
Further, after the instantiation module of the clock generation model 13 obtains the frequency and the frequency dividing ratio of the high-frequency simulation clock signal, the instantiation module of the clock generation model 13 may determine the frequency of the reference clock simulation signal that needs to be generated by the instantiation module of the clock generation simulation circuit 12 based on the frequency and the frequency dividing ratio of the high-frequency simulation clock signal, where the frequency of the reference clock simulation signal is a relevant parameter of the reference clock simulation signal.
As a second way, if the instantiated module of the clock generation model 13 needs to generate the test clock simulation signal by jitter, the instantiated module of the clock generation model 13 can detect the configuration in the corresponding connected clock generation simulation circuit 12 based on its own configuration. The arrival time point of the clock edge of the reference clock simulation signal required to be generated by the clock generation simulation circuit 12 in each clock cycle is obtained by detecting the configuration in the clock generation simulation circuit 12, wherein the arrival time point of the clock edge of the reference clock simulation signal in each clock cycle is the relevant parameter of the reference clock simulation signal.
As a third way, if the instantiated module of the clock generation model 13 needs to generate the test clock simulation signal through jitter + frequency offset, the instantiated module of the clock generation model 13 can detect the output interface of the phase-locked loop in the clock generation simulation circuit 12 and the configuration in the clock generation simulation circuit 12, which are connected correspondingly, based on its own configuration. So as to acquire the frequency and the frequency dividing ratio of the high-frequency simulation clock signal by detecting the output interface and by detecting the configuration in the clock generation simulation circuit 12.
Further, after the instantiation module of the clock generation model 13 obtains the frequency and the frequency dividing ratio of the high-frequency simulation clock signal, the instantiation module of the clock generation model 13 also determines the frequency of the reference clock simulation signal that needs to be generated by the clock generation simulation circuit 12 based on the frequency and the frequency dividing ratio of the high-frequency simulation clock signal, so that the frequency of the reference clock simulation signal and the arrival time point of the clock edge of the reference clock simulation signal in each clock cycle are the relevant parameters of the reference clock simulation signal.
After the instantiation module of the clock generation model 13 obtains the relevant parameters, the instantiation module of the clock generation model 13 may execute step S200.
Step S200: and generating a test clock simulation signal which belongs to the clock domain and has random waveform characteristics according to the relevant parameters.
In this embodiment, as can be seen from the foregoing, the instantiation modules of the clock generation model 13 collect different relevant parameters, and the manner of generating the test clock simulation signal is also different, which will be described below.
As a way of generating the test clock simulation signal by frequency shifting, the instantiated module of the clock generation model 13 may perform frequency shifting in a constant manner if the instantiated module of the clock generation model 13 needs to generate the test clock simulation signal by frequency shifting.
Specifically, the instantiation module of the clock generation model 13 may shift the frequency of the reference clock simulation signal up or down by a preset value according to a preset processing policy, obtain a shifted frequency, and generate the test clock simulation signal according to the shifted frequency.
It should be noted that the processing policy defines a preset value corresponding to each test of the instantiation module of the clock generation model 13, and the preset values corresponding to each test may be the same or different. For example, the processing policy may define that the preset range of the offset is-10 MHz to +10MHz, and each instantiation module of the test clock generation model 13 determines the preset value of the test from the range, where the mode of determining the preset value may be random selection or may be regular sequential increase or decrease. Thus, for the same simulation circuit 11, the instantiation module of the clock generation model 13 may excite the same simulation circuit 11 with the test clock simulation signals belonging to the same clock domain but having different waveform characteristics, so that the simulation circuit 11 is continuously excited by the test clock simulation signals with various changes, and the working condition of the simulation circuit 11 can be made to be close to the working condition of the actual circuit, and therefore, it is easier and faster to test whether a signal synchronizer is missing between the simulation circuit 11 and other simulation circuits 11.
It should be noted that the preset value of the frequency up-shift or down-shift can be set according to the frequency of the reference clock simulation signal. For example, when the frequency of the reference clock simulation signal is 10000MHz, the preset value may be set to +10, so that the frequency after the upper offset is 10010MHz, or the preset value may be set to-10, so that the frequency after the lower offset is 9990 MHz.
Alternatively, the instantiated modules of the clock generation model 13 may be frequency shifted in a periodic manner.
Specifically, the instantiation module of the clock generation model 13 may sequentially shift the frequency by a preset first numerical value and a preset second numerical value in units of each preset period according to a preset processing policy, to obtain a shifted frequency of each preset period, where the first numerical value is different from the second numerical value; and generating a test clock simulation signal according to the shifted frequency, so that the frequencies of the test clock simulation signal in every two adjacent preset periods are different.
It should be noted that the processing policy also defines that the instantiated module of the clock generation model 13 tests the corresponding first value and second value each time, and at least one of the first value and the second value is different for each test. For example, the processing policy defines that the preset range of the offset is-10 MHz to +10MHz, and then the instantiation module of the test clock generation model 13 determines the first value and the second value of the current test from the range each time, and the manner of determining the first value and the second value may be random selection or sequentially increasing or decreasing according to a rule, so as to ensure that the first value and the second value corresponding to each test are different. In this way, for the same simulation circuit 11, the instantiation module of the clock generation model 13 may also excite the same simulation circuit 11 with each test clock simulation signal belonging to the same clock domain but having different waveform characteristics, so that the simulation circuit 11 is continuously excited by the test clock simulation signals with various changes, and the working condition of the simulation circuit 11 can be made to be close to the working condition of the actual circuit, and therefore, it can be more easily and more quickly tested whether a signal synchronizer is missing between the simulation circuit 11 and other simulation circuits 11.
In this embodiment, the first value and the second value may also be set according to the test requirement. For example, the first value and the second value may be set to have opposite signs, so that the number of clock edges generated every two adjacent preset periods of the signals is different; for example, when the frequency of the reference clock simulation signal is 10000Hz, the preset period is 1 second, the two periods are sequentially shifted by setting the first value to be +10 and the second value to be-10, the frequency after the first preset period shift is 10010Hz, the frequency after the second preset period shift is 9990Hz, the frequency after the third preset period shift is 10010Hz, and so on. It can be understood that, after the offset is performed sequentially with the first value being +10 and the second value being-10, the frequency is measured with the predetermined period (1s), the frequency of the test clock simulation signal is shifted, but the frequency is measured with twice the predetermined period (2s), and the frequency of the test clock simulation signal is not changed, in other words, when the frequency is measured with the manner and with twice the predetermined period (2s), the frequency is still 10000Hz, but the waveform characteristic of the test clock simulation signal is changed compared with the waveform characteristic of the reference clock simulation signal.
For example, the first value and the second value may have the same positive and negative, so that the number of clock edges generated in every two adjacent cycles is different; for example, when the frequency of the reference clock simulation signal is 10000Hz, the preset period is 1 second, the preset first value is +10 and the second value is +20, the frequency obtained after the first preset period is offset is 10010Hz, the frequency obtained after the second preset period is offset is 10020Hz, the frequency obtained after the third preset period is offset is 10010Hz, and so on. Thus, when generating a test clock simulation signal according to each preset frequency after period offset, a test clock simulation signal including 10010 clock edges can be generated in a first preset period according to the first preset frequency 10010Hz after period offset, then a test clock simulation signal including 10020 clock edges can be generated in a second preset period according to the second preset frequency 10020Hz after period offset, then a test clock simulation signal including 10010 clock edges can be generated in a third preset period according to the third preset frequency 10010Hz after period offset, and so on.
In addition, it should be noted that, in the above embodiments, sequentially shifting the frequency twice in a preset periodic manner is only an exemplary manner of the present application, and is not limited thereto. For example, the frequency may be shifted twice or more in a predetermined period, for example, the frequency is shifted by a first value in a first predetermined period, the frequency is shifted by a second value in a second predetermined period, the frequency is shifted by a third value in a third predetermined period, the frequency is shifted by the first value in a fourth predetermined period, and so on.
Returning to this embodiment, if the instantiation module of the clock generation model 13 needs to generate the test clock simulation signal by dithering, the instantiation module of the clock generation model 13 adjusts the arrival time point of the reference clock simulation signal at the clock edge in each clock cycle by dithering according to a preset processing strategy, so as to obtain each adjusted arrival time point. Because the adjustment is to advance or retard the arrival time point of the clock edge in each clock cycle randomly or regularly, it is ensured that the waveform characteristics of the test clock simulation signal generated according to each test are different, and therefore, it is also realized that the simulation circuit 11 can be tested by the test clock simulation signal with different waveform characteristics every time, so that the simulation circuit 11 is continuously excited by the test clock simulation signal with various changes, the working condition of the simulation circuit 11 can be made to be close to the working condition of the circuit in practice, and therefore, whether a signal synchronizer is missing between the simulation circuit 11 and other simulation circuits 11 can be tested more easily and more quickly.
In this embodiment, if the instantiated module of the clock generation model 13 needs to generate the test clock simulation signal by jitter + frequency offset, as one mode, the instantiated module of the clock generation model 13 can generate the test clock simulation signal by jitter + frequency constant offset.
Specifically, the instantiation module of the clock generation model 13 may also shift the frequency of the reference clock simulation signal up or down by a preset value according to a preset processing policy, so as to obtain the shifted frequency. After the offset frequency is determined, the instantiated module of the clock generation model 13 may generate a preliminary clock simulation signal at the offset frequency to determine the arrival time point of the preliminary clock simulation signal at the clock edge in each clock cycle. Furthermore, the instantiated module of the clock generation model 13 may adjust the arrival time point of the clock edge of the preliminary clock simulation signal in each clock cycle by means of jitter, so as to obtain the adjusted arrival time point. In this way, the instantiated module of the clock generation model 13 may also generate the test clock simulation signal according to the adjusted arrival time point.
It will be appreciated that the constant frequency offset + jitter approach can further increase the randomness of the waveform characteristics, so that the test clock simulation signals can be more easily and quickly tested for the absence of signal synchronizers between the simulation circuit 11 and other simulation circuits 11.
Alternatively, instantiated modules of clock generation model 13 may generate test clock simulation signals by dithering + frequency period offset.
Specifically, the instantiation module of the clock generation model 13 may also sequentially shift the frequency of the reference clock simulation signal by a preset first numerical value and a preset second numerical value in each preset period as a unit according to a preset processing policy, so as to obtain the shifted frequency of each preset period. After the frequency after each predetermined period offset is determined, the instantiated module of the clock generation model 13 may generate a preliminary clock simulation signal at each predetermined period offset, thereby determining the arrival time point of the preliminary clock simulation signal at the clock edge in each clock cycle. Furthermore, the instantiated module of the clock generation model 13 adjusts the arrival time point of the clock edge of the preliminary clock simulation signal in each clock cycle by means of dithering, so as to obtain the adjusted arrival time point. In this way, the instantiated module of the clock generation model 13 may also generate the test clock simulation signal according to the adjusted arrival time point.
It is understood that the periodic frequency offset + jitter mode can further increase the randomness of the waveform characteristics, so that the test clock simulation signal can be tested more easily and also can be tested more quickly whether there is a signal synchronizer between the simulation circuit 11 and other simulation circuits 11.
After generating the test clock emulation signal, step S300 may be further performed.
Step S300: and exciting the simulation circuit in the simulation platform by using the test clock simulation signal so as to enable the simulation circuit to work in the clock domain. The simulation circuit is also in communication connection with other simulation circuits working in other clock domains in the simulation platform.
In this embodiment, the instantiation module of the clock generation model 13 is also configured with a policy of forced output in advance, so that the generated test clock simulation signal is forced to the output of the simulated circuit 11 by executing the policy of forced output, thereby replacing the original output of the clock generation simulation circuit 12.
Of course, the enforcement of the policy of forcing the output by the instantiated modules of the clock generation model 13 may also be controlled by the tester. For example, if a user needs to excite the corresponding simulation circuit 11 with a test clock simulation signal, a tester may perform a signal input operation, such as a macro-defined operation, and the instantiation module of the clock generation model 13 may perform the policy of forced output by responding to the operation, so as to force the generated test clock simulation signal to the output of the simulated circuit 11; if the user does not need to use the test clock simulation signal to activate the corresponding simulation circuit 11, the tester may perform a signal termination operation such as performing an operation that does not define the macro, and the clock generation model 13 also stops performing the policy of forcing the output by the operation, so that the simulation circuit 11 still receives the signal output of the clock generation simulation circuit 12.
Referring to fig. 4, based on the same inventive concept, an embodiment of the present application further provides a signal processing apparatus 100, where the signal processing apparatus 100 may be applied to the clock generation model 13 or may also be applied to the improved clock generation simulation circuit 12, and the signal processing apparatus 100 may include:
a parameter obtaining module 110, configured to obtain a parameter related to a clock simulation signal belonging to a clock domain;
a signal processing module 120, configured to automatically generate, according to the relevant parameter, a test clock simulation signal that belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal; and stimulating the simulation circuit 11 in the simulation platform 10 by using the test clock simulation signal so as to enable the simulation circuit 11 to work in the clock domain, wherein the simulation circuit 11 is also in communication connection with other simulation circuits 11 in the simulation platform 10 working in other clock domains.
It should be noted that, as those skilled in the art can clearly understand, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The embodiments of the present application also provide a computer-readable storage medium of a non-volatile program code executable by a computer, where the storage medium can be a general-purpose storage medium, such as a removable disk, a hard disk, and the like, and the computer-readable storage medium has a program code stored thereon, and when the program code is executed by a computer, the computer executes the steps of the signal processing method according to any one of the above embodiments.
The program code product of the signal processing method provided in the embodiment of the present application includes a computer-readable storage medium storing the program code, and instructions included in the program code may be used to execute the method in the foregoing method embodiment, and specific implementation may refer to the method embodiment, which is not described herein again.
In summary, since the test clock simulation signal having the same clock domain as the reference clock simulation signal and different waveform characteristics is automatically generated in the simulation environment, it is not necessary to manually adjust the waveform characteristics, so that the loss of the signal synchronizer can be efficiently analyzed at an early stage of circuit design.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described apparatus embodiments are merely illustrative. For example, the division of the elements into only one logical division may be implemented in a different manner, and for example, multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and it is obvious to those skilled in the art that various modifications and variations can be made in the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (15)
1. A method of signal processing, the method comprising:
obtaining relevant parameters of a reference clock simulation signal belonging to a clock domain;
automatically generating a test clock simulation signal which belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal according to the related parameters;
stimulating a simulation circuit in a simulation platform by using the test clock simulation signal so as to enable the simulation circuit to work in the clock domain, wherein the simulation circuit is also in communication connection with other simulation circuits in the simulation platform which work in other clock domains;
wherein the method is applied to a clock generation model;
the stimulating a simulation circuit in a simulation platform by using the test clock simulation signal comprises:
and forcing the test clock simulation signal to the output of a clock generation simulation circuit in the simulation platform to replace the original output of the clock generation simulation circuit, so that the test clock simulation signal is output to the simulation circuit in the simulation platform through the clock generation simulation circuit.
2. The signal processing method of claim 1, wherein the correlation parameters comprise: the frequency of the reference clock simulation signal automatically generates a test clock simulation signal which belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal according to the relevant parameters, and the method comprises the following steps:
shifting the frequency up or down by a preset value to obtain the shifted frequency;
and generating the test clock simulation signal according to the frequency after the offset.
3. The signal processing method of claim 1, wherein the correlation parameters comprise: the frequency of the reference clock simulation signal automatically generates a test clock simulation signal which belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal according to the relevant parameters, and the method comprises the following steps:
sequentially shifting the frequency by a preset first numerical value and a preset second numerical value by taking each preset period as a unit to obtain the shifted frequency of each period, wherein the first numerical value is different from the second numerical value;
and generating the test clock simulation signal according to the frequency after the offset.
4. The signal processing method of claim 1, wherein the correlation parameters comprise: the method for automatically generating the test clock simulation signal which belongs to the clock domain and has the waveform characteristics different from that of the reference clock simulation signal according to the relevant parameters at the arrival time point of the clock edge of the reference clock simulation signal in each clock cycle comprises the following steps:
adjusting the arrival time point through dithering to obtain an adjusted arrival time point;
and generating the test clock simulation signal according to the adjusted arrival time point.
5. The signal processing method of claim 1, wherein the correlation parameters comprise: the frequency of the reference clock simulation signal automatically generates a test clock simulation signal which belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal according to the relevant parameters, and the method comprises the following steps:
shifting the frequency up or down by a preset value to obtain the shifted frequency;
adjusting the arrival time point of the clock edge in each clock period corresponding to the shifted frequency through dithering to obtain the adjusted arrival time point;
and generating the test clock simulation signal according to the adjusted arrival time point.
6. The signal processing method of claim 1, wherein the correlation parameters comprise: the frequency of the reference clock simulation signal automatically generates a test clock simulation signal which belongs to the clock domain and has a waveform characteristic different from that of the reference clock simulation signal according to the relevant parameters, and the method comprises the following steps:
sequentially shifting the frequency by a preset first numerical value and a preset second numerical value by taking each preset period as a unit to obtain the shifted frequency of each period, wherein the first numerical value is different from the second numerical value;
adjusting the arrival time point of the clock edge in each clock period corresponding to the shifted frequency through dithering to obtain the adjusted arrival time point;
and generating the test clock simulation signal according to the adjusted arrival time point.
7. The signal processing method of claim 1, wherein obtaining the relevant parameters of the reference clock emulation signal belonging to a clock domain comprises:
detecting an output interface of a phase-locked loop of a clock generation simulation circuit in the simulation platform, and acquiring the frequency of a high-frequency simulation clock signal output by the phase-locked loop;
detecting the configuration of the clock generation simulation circuit, and acquiring the frequency dividing ratio of the clock generation simulation circuit and the arrival time point of the clock edge of the reference clock simulation signal in each clock cycle;
and determining the frequency of the reference clock simulation signal according to the frequency dividing ratio and the frequency of the high-frequency simulation clock signal.
8. The signal processing method of claim 1, wherein forcing the test clock emulation signal onto the output of the clock generation emulation circuit comprises:
forcing the test clock emulation signal onto the output of the clock generation emulation circuit in response to a user-performed signal input operation.
9. The signal processing method of claim 1, wherein the method is applied to a clock generation model, and when the test clock simulation signal is used to stimulate a simulation circuit in a simulation platform, the method further comprises:
and controlling the other simulation circuits to work in the other clock domains.
10. The signal processing method of claim 9, wherein controlling the other emulation circuit to operate in the other clock domain comprises:
obtaining other relevant parameters of other reference clock simulation signals belonging to the other clock domains;
generating other test clock simulation signals which belong to other clock domains and have waveform characteristics different from those of the other reference clock simulation signals according to the other related parameters;
and exciting the other simulation circuits by using the other test clock simulation signals.
11. A signal processing apparatus, characterized in that the apparatus comprises:
the parameter acquisition module is used for acquiring related parameters of a reference clock simulation signal belonging to a clock domain;
the signal processing module is used for automatically generating a test clock simulation signal which belongs to the clock domain and has different waveform characteristics from the reference clock simulation signal according to the related parameters; stimulating a simulation circuit in a simulation platform by using the test clock simulation signal so as to enable the simulation circuit to work in the clock domain, wherein the simulation circuit is also in communication connection with other simulation circuits in the simulation platform which work in other clock domains;
wherein the signal processing means is applied to a clock generation model;
the signal processing module is used for: and forcing the test clock simulation signal to the output of a clock generation simulation circuit in the simulation platform to replace the original output of the clock generation simulation circuit, so that the test clock simulation signal is output to the simulation circuit in the simulation platform through the clock generation simulation circuit.
12. A simulation platform, the platform comprising: the simulation circuit comprises a simulation circuit, a clock generation simulation circuit connected with the simulation circuit, a clock generation model connected with the clock generation simulation circuit, and other simulation circuits connected with the simulation circuit, wherein the other simulation circuits are in other clock domains;
wherein the clock generation model is configured to perform the signal processing method according to any one of claims 1 to 10.
13. The simulation platform of claim 12,
the clock generation model is connected with the clock generation simulation circuit in an instantiation mode.
14. A computer-readable storage medium having computer-executable nonvolatile program code, characterized in that the program code causes the computer to execute the signal processing method according to any one of claims 1 to 10.
15. An electronic device, comprising: a memory for storing a program; a bus; a processor connected to the memory through the bus, the processor being configured to execute the program to perform the signal processing method according to any one of claims 1 to 10.
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| CN113607992B (en) * | 2021-09-08 | 2023-07-21 | 广东电网有限责任公司 | A detection wave generation method and related devices for a DC power distribution protection device |
| CN114860029B (en) * | 2022-04-22 | 2024-01-26 | 芯华章科技股份有限公司 | Clock generation method, device and storage medium for multi-clock domain digital simulation circuit |
| CN115171767A (en) * | 2022-07-05 | 2022-10-11 | 长鑫存储技术有限公司 | Chip testing method, device, equipment and medium |
| CN116108803B (en) * | 2023-04-12 | 2024-03-22 | 北京紫光青藤微系统有限公司 | Method and apparatus for generating an irregular clock signal |
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