CN112117242B - Chip package structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises a base island, packaging materials, a first chip attached to the upper surface of the base island and a second chip arranged far away from the upper surface of the base island compared with the first chip, and is characterized by further comprising a base film layer arranged on the lower surface of the second chip and a plurality of connecting columns, wherein the upper ends of the connecting columns are planted on the base film layer, the lower ends of the connecting columns are welded to the upper surface of the base island, and the packaging materials encapsulate the first chip and the second chip and are filled between the base island and the second chip. Through the arrangement of the substrate film layer and the planting of the connecting column, the packaging material can wrap around the connecting column and fill in a gap between the second chip and the base island, so that smooth discharge of gas in the wrapping process is facilitated, and the void phenomenon is avoided; and, the upper end of spliced pole is planted and is established in the basement rete and its lower extreme welds to the base island on for the spliced pole steadiness is strong, avoids the spliced pole to drop or shift.

Description

Chip package structure and manufacturing method thereof

technical field

The invention belongs to the technical field of chip packaging, and relates to a chip packaging structure and a manufacturing method thereof.

Background technique

With the rapid development of modern electronic information technology, electronic products are developing in the direction of miniaturization, portability and multi-function, which drives the development trend of miniaturization of semiconductor packaging products, which requires packaging design to maximize the use of packaging space and reduce the size of semiconductor packaging products size of.

In the existing packaging structure, when there are multiple chips, it usually occurs that another chip is stacked on top of one chip. In order to stagger the wiring path and avoid the bad problem caused by the lead wire touching the wire, usually the previous chip will appear The phenomenon of partial suspension, in order to avoid chip breakage and breakage in the suspension area during wiring, it is necessary to set up a gasket under the suspension area of the chip to support and elevate the suspended chip. Taking the package structure 200 with two chips (chip 211 and chip 212) shown in Figure 1 and Figure 2 as an example, the package structure 200 also includes a lead frame and a plurality of leads 230, and the lead frame specifically includes a base island 221 and a The pins 222 and the base island 221 are used to fix and support the chip 211 and the chip 212 . Wherein, two of the chip 211 , the chip 212 , and the pin 222 can be electrically connected through the wire 230 . As mentioned above, the chip 212 is elevated by the spacer 250 , and the chip 212 is broken or broken when the wire is bonded in the suspended area.

However, in the existing packaging structure, as shown in the figure, after the chip 212 is elevated by the spacer 250, there is usually a certain slit S between the spacer 250 and the chip 211 located on the lower layer. During the encapsulation process of the manufacturing process, the package The material 240 needs to be wrapped back into the slit S from the two ends S1 and S2 of the slit S, which often results in gas residues in the slit S because the gas cannot be discharged normally, resulting in voids and affecting product quality.

Contents of the invention

In order to solve the problem of voids caused by gas residues in the prior art when the chip is elevated and packaged, the purpose of the present invention is to provide a chip packaging structure and a manufacturing method thereof, which can avoid the occurrence of voids while the chip is elevated .

In order to achieve one of the objectives of the above invention, an embodiment of the present invention provides a chip packaging structure, including a base island, a packaging material, a first chip mounted on the upper surface of the base island, and a The second chip arranged away from the upper surface of the base island, the chip packaging structure also includes a base film layer and a plurality of connecting posts, the base film layer is arranged on the lower surface of the second chip, and the connecting posts The upper end is planted on the base film layer and the lower end is welded on the upper surface of the base island, the encapsulation material encapsulates the first chip and the second chip and fills the base island and the between the second chips.

As a further improvement of an embodiment of the present invention, any two connecting posts are separated from each other and do not contact each other.

As a further improvement in one embodiment of the present invention, the base film layer is set as a sputtered metal film;

The connection post includes a metal post and a bump planted on the lower end of the metal post, and the connection post is welded to the upper surface of the base island through the bump.

As a further improvement of an embodiment of the present invention, the upper surface of the second chip is an electrical signal functional surface; the upper surface of the first chip is an electrical signal functional surface;

The packaging structure further includes pins, and any two of the second chip, the pins, and the first chip are electrically connected through wires;

The encapsulation compound also encapsulates the leads and covers the upper surface of the pins.

As a further improvement of an embodiment of the present invention, the first chip is mounted on the upper surface of the base island by a die-mount adhesive;

A part of the second chip and a part of the first chip are overlapped up and down, and a mounting glue is filled between the two.

In order to achieve one of the purposes of the above invention, an embodiment of the present invention also provides a method for manufacturing a chip packaging structure, including:

forming a base film layer on the first surface of the second chip;

planting a plurality of connection posts on the basement membrane layer;

mounting the first chip on the upper surface of the base island;

welding the connection post to the upper surface of the base island, so that the second chip is fixed to the base island;

Encapsulating with an encapsulating material to obtain a chip encapsulating structure.

As a further improvement in one embodiment of the present invention, the step "forming a base film layer on the first surface of the second chip" includes:

Attaching a protective film on the second surface of the second chip, the second surface is opposite to the first surface and is the electrical signal functional surface of the second chip;

grinding and ultrasonically cleaning the first surface of the second chip;

A base film layer is formed by sputtering on the first surface of the second chip.

As a further improvement of one embodiment of the present invention, the step "implanting a plurality of connecting posts on the basement membrane layer" includes:

Laying a photosensitive dry film on the base film layer;

Partial exposure and development of the photosensitive dry film, so that the photosensitive dry film is patterned to form a plurality of pillar openings exposing the base film layer;

successively planting metal posts and bumps at the openings of the planting posts to obtain connecting posts;

removing the photosensitive dry film from the basement film layer planted with the connecting posts.

As a further improvement of an embodiment of the present invention, any two connecting posts are separated from each other and do not contact each other.

As a further improvement of an embodiment of the present invention, before encapsulating with the encapsulation compound, at least two of the first chip, the second chip, and the pins are electrically connected through wires;

In the step "forming a base film layer on the first surface of the second chip" and the step "planting a plurality of connection posts on the base film layer", multiple second chips are integrated on the same wafer and performed simultaneously in batches; and Slicing a plurality of the second chips from the wafer before the step of "soldering the connection posts to the upper surface of the base island so that the second chips are fixed to the base island" separated.

Compared with the prior art, the beneficial effect of the present invention is that: by setting the base film layer and planting a plurality of the connecting posts, the chip (the second chip) that needs to be elevated can be fixed through the connecting posts. mounted on the base island, so that the encapsulation material can cover and fill into the gap between the second chip and the base island along the connecting column, avoiding the two ends of the prior art Backpacking causes the gas to be difficult to discharge, thereby avoiding the void phenomenon and ensuring product quality; in addition, the upper end of the connecting column is planted on the base film layer and its lower end is welded to the base island, so that the The connections between the connection posts and the second chip and the base island are strong, which prevents the connection posts from falling off or shifting, and further ensures product quality.

Description of drawings

Fig. 1 is a top view of a packaging structure with a partial perspective effect in the prior art;

Fig. 2 is a schematic cross-sectional view of a package structure in the prior art, and its cross-section is shown along A-A in Fig. 1;

Fig. 3 is a top view of a chip package structure with a partial perspective effect according to an embodiment of the present invention;

Fig. 4a is a schematic cross-sectional view of a chip package structure according to an embodiment of the present invention, and its cross-section is shown along B-B in Fig. 3;

Figure 4b is an enlarged view of area C in Figure 4a;

5 is a flowchart of a manufacturing method of a chip packaging structure according to an embodiment of the present invention;

6 is a schematic diagram of attaching a protective film to the electrical signal functional surface of the second chip;

Fig. 7 is a schematic diagram of grinding and cleaning the non-electric signal functional surface of the second chip;

8 is a schematic diagram of forming a base film layer on the non-electrical signal functional surface of the second chip;

Fig. 9 is a schematic diagram of coating a photosensitive dry film on the base film layer;

Figure 10a is a schematic diagram of the patterning of the photosensitive dry film after exposure and development;

Figure 10b is a top view of patterning of the photosensitive dry film after exposure and development;

Fig. 11 is a schematic diagram of planting a connecting column at the opening of the planting column;

Figure 12 is a schematic diagram of peeling off the photosensitive dry film;

Fig. 13 is a schematic diagram of attaching the first chip to the base island;

Fig. 14 is a schematic diagram of the second chip being mounted on the base island;

Fig. 15 is a schematic diagram of connecting leads between the first chip, the second chip, and pins;

FIG. 16 is a schematic diagram of a chip package structure formed after encapsulation;

FIG. 17 is a schematic diagram of cutting a wafer into a plurality of second chips in another embodiment of the present invention.

Detailed ways

The present invention will be described in detail below in conjunction with specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, method, or functional changes made by those skilled in the art according to these embodiments are included in the protection scope of the present invention.

It should be noted that terms such as "upper" and "upper" used herein to indicate spatial orientation are based on the positional relationship in the diagram, which describes a unit or feature as shown in the drawings relative to Relationship to another unit or feature; terms of spatial relative position may be intended to cover different orientations of a product in use or operation than that shown in the drawings, for example, if a product in a drawing is turned over, it is described as being located in another A unit that is "below" or "below" a unit or feature will be located "above" another unit or feature.

Referring to Fig. 3, Fig. 4a and Fig. 4b, a chip packaging structure 100 provided by an embodiment of the present invention is schematically shown in the form of two chips (first chip 10 and second chip 20) in the drawings, but The number of chips is not limited thereto, and can be set to any number of two or more. Moreover, for the convenience of description, the perspective effect of the second chip 20 is illustrated in FIG. 3 .

Specifically, the chip packaging structure 100 includes a first chip 10 , a second chip 20 , a lead frame, several leads 70 and a package material 60 .

The lead frame includes a base island 30 and several pins 40 surrounding the base island 30 .

Wherein, the base island 30 plays a role of fixing and supporting the first chip 10 and the second chip 20 .

Specifically, the first chip 10 is mounted on the upper surface of the base island 30 . In this embodiment, the first chip 10 is closely pasted and fixed on the upper surface of the base island 30 by the die-mounting adhesive 80. On the one hand, the die-mounting adhesive 80 can make there be no assembly seam between the first chip 10 and the base island 30. On the one hand, there is an area around the edge of the base island 11 for the overflow of the sheet glue 80 . Wherein, the mounting glue 80 is preferably set as silver glue.

The lower surface of the first chip 10 is a non-electric signal function surface, and the lower surface of the first chip 10 is pasted and fixed on the upper surface of the base island 30 .

Correspondingly, the upper surface of the first chip 10 is an electrical signal function surface, that is, the upper surface of the first chip 10 may be provided with aluminum pads/other terminals for power supply signal transmission. Leads 70 are welded on the upper surface of the first chip 10 , so that an electrical signal transmission circuit is formed between the first chip 10 and other components (such as the second chip 20 , pins 40 , etc.).

The second chip 20 is also relatively fixedly connected to the upper surface of the base island 30 , which is farther away from the upper surface of the base island 30 than the first chip 10 . That is to say, both the second chip 20 and the first chip 10 are located above the base island 30, and the second chip 20 is elevated, and the distance between the lower surface of the second chip 20 and the upper surface of the base island 30 is greater than that of the first chip. The distance between the lower surface of 10 and the upper surface of base island 30. In this way, in the vertical direction, the layout of the second chip 20 and the first chip 10 is layered, thereby avoiding the problem of line collision as mentioned in the background art.

At least two of the pins 40 , the first chip 10 , and the second chip 20 are electrically connected by wires 70 , so as to form an electrical signal transmission circuit required by the chip package structure 10 . In this embodiment, any two of the pins 40 , the first chip 10 , and the second chip 20 are electrically connected by wires 70 .

Specifically, the upper surface of the pin 40 has a conductive film layer 41 , and the wire 70 is soldered to the conductive film layer 41 to electrically connect the pin 40 to the first chip 10 and the pin 40 to the second chip 20 . Preferably, in this embodiment, the conductive film layer 41 is set as a silver-plated film layer, but of course it is not limited thereto.

The packaging material 60 is used to encapsulate the first chip 10 , the second chip 20 and the leads 70 to protect the first chip 10 , the second chip 20 and the leads 70 . Preferably, the encapsulant 60 also covers the entire upper area of the lead frame, and its lower end surface is flush with the lower surface of the lead frame, so that the encapsulant 60 encapsulates the first chip 10, the second chip 20 and the leads. 70 , and cover the upper surface of the base island 30 and the upper surface of the pin 30 at the same time, and the lower surface of the base island 30 and the lower surface of the pin 30 are exposed outside the packaging compound 60 .

In the present invention, the chip packaging structure 100 further includes a base film layer 52 and a connecting post 51 .

The base film layer 52 is disposed on the lower surface of the second chip 20 and is firmly connected to the lower surface of the second chip 20 . In a specific implementation, the base film layer 52 can be arranged on the entire area of the lower surface of the second chip 20, and can also be arranged on a local area of the lower surface of the second chip 20 as required, and none of these embodiments deviates from the technical aspects of the present invention. purpose.

The number of connecting columns 51 is set to multiple, which can be any number of 3 or more, and is illustrated as 9 in the accompanying drawings, but is not limited thereto; and, in the following description in conjunction with the accompanying drawings, any The two connecting posts 51 are exemplified with substantially the same structure, but not limited thereto, and some or all of the connecting posts 51 may be configured to have different structures from each other, provided that the implementation effect is not affected.

The upper end of the connecting column 51 is planted on the base film layer 52, the connection strength is high, and the structure is stable and not easy to fall off/break. The lower end is welded to the upper surface of the base island 30, that is, the lower end of the connecting column 51 and the upper surface of the base island 30 are fixedly connected by welding, and the connection strength is also high, and the structure is stable and not easy to fall off/break.

In this way, by setting the base film layer 52 and planting a plurality of connecting pillars 51, the second chip 20 can be fixed to the base island 30 through the connecting pillars 51 while elevating, and then the packaging material 60 can be wrapped in the connecting pillars 51. surrounding, and can be filled into the gap S0 between the second chip 20 and the base island 30, which is beneficial to the smooth discharge of the gas in the gap S0 during the encapsulation process, avoiding the occurrence of voids, and ensuring product quality; in addition, the connecting column 51 It can be stably connected with the second chip 20 and the base island 30 to avoid falling off or displacement of the connecting column 51 and further ensure product quality.

Preferably, in one embodiment of the present invention, any two connecting posts 51 are separated from each other and do not contact each other, so that the entire area of the gap S0 between the second chip 20 and the base island 30 is connected and integrated, which can further ensure that the During the encapsulation process, the encapsulation material 60 can effectively fill the gap S0 between the second chip 20 and the base island 30 , avoiding the cavity problem caused by the inability to discharge the gas.

Further, the upper surface of the second chip 20 is an electrical signal function surface, that is, the upper surface of the second chip 20 may be provided with aluminum pads/other terminals for power supply signal transmission. Leads 70 are welded on the upper surface of the second chip 20 , so that an electrical signal transmission circuit is formed between the second chip 20 and other components (such as the first chip 10 , pins 40 , etc.).

Correspondingly, the lower surface of the second chip 20 is a non-electrical signal function surface, and the lower surface of the second chip 20 forms the base film layer 52 through a sputtering process. In other words, in this embodiment, the base film layer 52 is set For sputtering a metal film, specifically, it can be sputtering a copper film.

Further, the connection post 51 includes a metal post 511 and a bump 512 .

Among them, the metal post 511 plays the role of support and fixation, which constitutes the upper end of the connecting post 51, and can be planted on the base film layer 52 by electroplating, evaporation, sputtering, deposition and other processes; in this embodiment, the metal The post 511 may be configured as a copper post.

The bump 512 is planted on the lower end of the metal pillar 511, which constitutes the lower end of the connecting pillar 51, and the connecting pillar 51 is soldered to the upper surface of the base island 30 through the bump 512; in this embodiment, the bump 512 is set as a solder ball.

Further, the distance between the lower surface of the second chip 20 and the upper surface of the base island 30 is not smaller than the distance between the upper surface of the first chip 10 and the upper surface of the base island 30 . In other words, the second chip 20 is located above the first chip 10, a part of the second chip 20 overlaps with a part of the first chip 10 up and down and a chip mounting glue 80 (such as silver glue) is filled between the two, so that The second chip 20 and the first chip 10 are fixedly assembled to each other and avoid assembly gaps.

Further, an embodiment of the present invention also provides a method for manufacturing a chip package structure, which can be used to generate and manufacture the aforementioned chip package structure 100. Of course, in a variable implementation situation, the manufactured The chip package structure product may not be limited to the aforementioned chip package structure 100 . Below, with reference to accompanying drawing 5, described manufacturing method comprises the following steps:

forming a base film layer on the first surface of the second chip;

planting a plurality of connection posts on the basement membrane layer;

mounting the first chip on the upper surface of the base island;

welding the connection post to the upper surface of the base island, so that the second chip is fixed to the base island;

Encapsulating with an encapsulating material to obtain a chip encapsulating structure.

In this way, by setting the base film layer and planting a plurality of the connection posts, the chip (the second chip) that needs to be elevated is fixed on the base island through the connection posts, so that the The encapsulation compound can cover and fill into the gap between the second chip and the base island along the connecting post, so that the gas in the space around the connecting post can be discharged smoothly during the encapsulation process, and then Avoid voids and ensure product quality; in addition, the upper end of the connecting post is planted on the base film layer and its lower end is welded to the base island, so that the connecting post is connected to the second chip, the base The connection stability of the island is strong, which prevents the connection column from falling off or shifting, and further ensures the product quality.

It should be noted that, in the manufacturing method, unless there is a necessary dependency relationship, the execution order of the steps is not limited to the above word order: for example, the step "attach the first chip on the upper surface of the base island" although In the descriptive sequence, it is after the step "form the base film layer on the first surface of the second chip", but the step "attach the first chip on the upper surface of the base island" is not limited to be later than the step "on the second Forming a base film layer on the first surface of the chip" is implemented.

Next, taking the chip packaging structure 100 as an example, the various steps of the manufacturing method will be introduced in combination with the embodiments shown in FIGS. 6 to 16 .

Step (1), forming a base film layer 52 on the first surface 201 of the second chip 20 .

Regarding step (1), the second chip 20 includes a first surface 201 and a second surface oppositely arranged, and the first surface 201 corresponds to the lower surface of the second chip 201 in the chip packaging structure 100, preferably the non-surface of the second chip 20. Electrical signal functional surface; correspondingly, the second surface of the second chip 20 corresponds to the upper surface of the second chip 201 in the chip packaging structure 100, preferably the electrical signal functional surface of the second chip 20, that is, the Aluminum pads/other terminals for power supply signal transmission can be provided on the second surface for welding with the leads 70 .

Specifically, step (1) includes the following sub-steps:

Sub-step S1, film

Referring to Fig. 6, a protective film 1 is pasted on the second surface of the second chip 20, so that the second surface can be protected by the protective film 1, so as to avoid aluminum pads, Electrical signal functional parts such as terminals are damaged in subsequent steps.

Sub-step S2, surface cleaning

Referring to Fig. 7, after attaching the protective film 1, on the one hand, the first surface 201 of the second chip 20 is ground to make the first plane 201 flat and reach the required chip thickness; on the other hand, the second chip is cleaned by ultrasonic waves. 20 on the first surface 201 of the first surface 20 to remove impurities and foreign matter on the first surface 201, so that it can be prepared for the subsequent formation of the base film layer 52 on the first surface 201 to ensure the molding effect and stability of the base film layer 52 ; Among them, preferably ultrasonic cleaning can be implemented after the grinding is completed, so as to clean the residue during grinding.

Sub-step S3, coating

Referring to FIG. 8 , after the surface cleaning of the first surface 201 of the second chip 20 is completed, a base film layer 52 is plated on the first surface 201, and the second chip 20 can be stably connected to the plated base film layer 52. The first surface 201 is used as the base of the subsequent column planting, which can increase the strength of the connection structure.

Preferably, the base film layer 52 can be formed on the first surface 201 by sputtering, the specific process is: filling argon gas in a high vacuum state, ionizing the argon gas under the action of a strong electric field to generate positive argon ions, and Accelerated and formed high-energy ion flow bombards the surface of the target, so that the target atoms are detached from the surface and sputtered (deposited) onto the first surface 201 of the second chip 20 to form the base film layer 52 .

Further preferably, the base film layer 52 is a sputtered metal film, especially a sputtered copper film.

In addition, preferably, as in this embodiment, the base film layer 52 is arranged on almost the entire area of the first surface 201 of the second chip 20. Of course, in a variant embodiment, the base film layer 52 can also be arranged on the second chip 20 as required. A local area of the first surface 201 .

Step (2), planting a plurality of connection pillars 51 on the basement membrane layer 52 .

Regarding step (2), the number of connecting columns 51 is set to be multiple, and it can be specifically any number of 3 or more than 3, exemplified as 9 in the accompanying drawings, but not limited thereto; and, hereinafter in conjunction with the attached In the description of the figure, any two connecting columns 51 are exemplified with approximately the same structure, but not limited thereto, and some or all of the connecting columns 51 may be configured to have different structures from each other without affecting the implementation effect.

Specifically, step (2) includes the following sub-steps:

Sub-step S4, cover dry film

9, a photosensitive dry film 2 is provided on the base film layer 52, and the photosensitive dry film 2 can be formed on the base film layer 52 by a coating process; it can be understood that the photosensitive dry film 2 is located on the base film layer 52 away from the second One side of the chip 20 , that is, the base film layer 52 is located between the photosensitive dry film 2 and the second chip 20 .

Preferably, the photosensitive dry film 2 completely covers the entire base film layer 52 .

Sub-step S5, patterning

Referring to Fig. 10a and Fig. 10b, the photosensitive dry film 2 is subjected to partition exposure and development, so that the photosensitive dry film 2 is patterned to form a plurality of pillar openings T exposing the base film layer 52; that is, through the partition exposure and development technology, the photosensitive dry film The film 2 is patterned, and the patterned photosensitive dry film 2 has a plurality of stud-planted openings T, and the stud-planted openings T expose the base film layer 52, while the remaining photosensitive dry film 2 except the stud-planted openings T still covers and shields Basement membrane layer 52 .

Specifically, the detailed process of patterning can be as follows: drawing a figure on a photoresist plate, placing the photoresist plate on one side of the photosensitive dry film 2, the photoreticle can block a part of the photosensitive dry film 2 and expose the photosensitive dry film 2. The remaining area of the film 2 (that is, the area where the pillar opening T needs to be formed); it is exposed to high-intensity light, and then developed, so that the photosensitive dry film 2 is exposed to the light. The area of the opening T) is removed, so as to realize the patterning of the photosensitive dry film 2 .

Sub-step S6, planting pillars

Referring to FIG. 11 , metal pillars 511 and bumps 512 are successively planted at the opening T of the pillar planting. Specifically, the metal post 511 can be first planted at the opening T of the post by electroplating, vapor deposition, sputtering, deposition, etc., and the metal post 511 is preferably a copper post; after that, at the end of the metal post 511 (corresponding to The lower end of the metal post 511 in the chip packaging structure 100 is implanted with bumps 512, and the bumps 512 are preferably solder balls.

It can be understood that before the metal post 511 is planted, the opening T of the post planting can be cleaned to remove oxides and residues on the rear surface, so that the surface of the base film layer 52 exposed at the opening T of the post planting can be cleaned. , so as to meet the requirements of subsequent pillar planting and ensure the connection strength between the metal pillar 511 and the base film layer 52 .

Sub-step S7, remove dry film

Referring to FIG. 12 , after the pillar planting is completed, the photosensitive dry film 2 attached to the base film layer 52 is removed, specifically by mechanical peeling or cleaning.

After the above step (1) and step (2), the second chip 20 carrying the base film layer 52, the connection post 51 and the protective film 1 can be obtained for later use, specifically after the protective film 1 is removed. It can be applied in subsequent manufacturing method steps.

In step (3), attach the first chip 10 to the upper surface 301 of the base island 30 by using the die-mount adhesive 80 .

Referring to FIG. 13 , in combination with FIG. 3 , spray or smear a mounting glue 80 at the center of the upper surface 301 of the base island 30. Specifically, the mounting glue 80 can be silver glue, and then the first chip 10 is pressed against the mounting glue. 80 to be mounted on the upper surface 301 of the base island 30, during the pressing process, the die-mounting adhesive 80 will fill up between the lower surface of the first chip 10 and the upper surface 301 of the base island 30, so as to avoid assembly gaps .

Wherein, the lower surface of the first chip 10 is a non-electric signal functional surface, which is pasted and fixed on the upper surface of the base island 30 and covered by the mounting adhesive 80 . Correspondingly, the upper surface of the first chip 10 is an electrical signal functional surface, that is, the upper surface of the first chip 10 can be provided with aluminum pads/other terminals for power supply signal transmission, for soldering with the leads 70 .

Further, in this step (3), the mounting adhesive 80 can also be coated on a local area of the upper surface 101 of the first chip 10, in order to assist in fixing the second chip 20 and avoid the generation of assembly gaps (see epilogue).

In step (4), solder the connecting post 51 to the upper surface 301 of the base island 30 so that the second chip 20 is fixed to the base island 30 .

Referring to Fig. 14, specifically, the aforementioned second chip 20 processed by step (1) and step (2) (that is, the second chip 20 carrying the base film layer 52 and the connecting post 51) is removed from the protective film 1 The upper part is peeled off, and then snapped onto the base island 30 ; that is, it is arranged on the base island 30 in such a way that the connection post 51 is on the lower second chip 20 .

A part of the second chip 20 is overlapped and attached to the mounting glue 80 on the upper surface 101 of the first chip 10. In a specific implementation, the position where the second chip 20 and the first chip 10 overlap up and down is filled with the mounting glue 80. , to stabilize the mounting position of the second chip 20, and avoid assembly gaps; and, the lower end of the connecting post 51 is welded to the upper surface 301 of the base island 30, specifically, the bump 512 of the connecting post 51 is welded to the base island 30, thus passing The welding connection can ensure the stable position of the connecting column 51 .

It can be understood that the second chip 20 is set higher than the first chip 20 through the connecting posts 51, and the distance between the lower surface of the second chip 20 and the upper surface 301 of the base island 30 is greater than that of the first chip 10. The distance between the lower surface and the upper surface 301 of the base island 30 , and a gap S0 around the connection pillar 51 is formed between the second chip 20 and the base island 30 .

In step (5), at least two of the first chip 10 , the second chip 20 , and the pins 40 are electrically connected through wires 70 .

Referring to Fig. 15, in this embodiment, the upper surface of the pin 40 has a conductive film layer 41, and the lead wire 70 is connected by welding, so that the pin 40 and the first chip 10, the pin 40 and the second chip 20, and the first chip 10 and the second chip 20 are electrically connected. Preferably, in this embodiment, the conductive film layer 41 is set as a silver-plated film layer, but of course it is not limited thereto.

Step (6), encapsulating with the encapsulation compound 60 to obtain the chip encapsulation structure 100 .

Wherein, the base island 30 and the pins 40 constitute at least part of the lead frame; referring to FIG. 16 , the entire upper area of the lead frame is covered by the encapsulation compound 60, and the lower end surface of the encapsulation compound 60 is flush with the lower surface of the lead frame. In the example shown in the figure, the lower end surface of the encapsulation material 60 is flush with the lower surface of the base island 30, so that the encapsulation material 60 encapsulates the first chip 10, the second chip 20 and the leads 70, and simultaneously covers the upper surface of the base island 30 301 and the upper surface of the pin 30 , the lower surface of the base island 30 and the lower surface of the pin 30 are exposed outside the encapsulation compound 60 .

In this way, the chip packaging structure 100 can be obtained, and it can be obtained that by setting the base film layer 52 on the lower surface of the second chip 20 and planting a plurality of connecting posts 51, the second chip 20 can pass through while being elevated. The connection post 51 is fixed on the base island 30, and in the encapsulation process of its manufacturing process, the encapsulation material 60 is wrapped around the connection post 51 and can be filled to the gap between the second chip 20 and the base island 30 In S0, it is beneficial for the gas in the gap S0 to be discharged smoothly during the encapsulation process, avoiding the occurrence of voids, and ensuring product quality; in addition, the connection post 52 can be firmly connected with the second chip 20 and the base island 30, avoiding the occurrence of the connection post 30 Falling off or shifting, further, guarantees product quality.

Further preferably, any two connection posts 51 are separated from each other and do not contact each other, so that the entire area of the gap S0 between the second chip 20 and the base island 30 is connected and integrated, which can further ensure that the encapsulation material 60 can effectively fill the gap S0 between the second chip 20 and the base island 30 , avoiding the cavity problem caused by the inability to discharge the gas.

It needs to be reiterated that in this application, unless there is a necessary dependency relationship, the implementation order of the steps of the manufacturing method is not limited to the above word order, and the steps are described herein as " Numbers such as S1", "S2", "(1)", and "(2)" do not imply the implementation order of each step, and the manufacturing method can implement each step in a reasonable and feasible order. For example, although step (1) is located before step (3) in word order, it is not limited to the implementation of step (1) prior to step (3); for another example, although step (2) is located in step (1) in numbering ), step (3), and are not limited to be implemented in the order of step (1), step (2), and step (3).

In addition, in the embodiments shown in FIG. 6 to FIG. 12 , step (1) and step (2) are illustrated in the form of a single second chip 20 . Of course, in the variant embodiment, step (1) and step (2) are also preferably implemented in a way that multiple second chips 20 are integrated on the same wafer and carried out in batches simultaneously, that is, the same wafer includes multiple The second chip 20, simultaneously carry out the operation of step (1) and/or step (2) to this plurality of second chips 20 synchronously, can improve production efficiency like this; Correspondingly, with reference to shown in Figure 17, in step (1 ) and step (2) are implemented, before step (4), the wafer can be cut into a plurality of second chips 20 carrying a base film layer 52 and a plurality of connecting posts 51, that is, the A plurality of second chips 20 are cut and separated from the wafer, so as to facilitate the assembly of the second chips 20 and the base island 30 in step (4).

It should be understood that although this description is described according to implementation modes, not each implementation mode only contains an independent technical solution, and this description in the description is only for clarity, and those skilled in the art should take the description as a whole, and each The technical solutions in the embodiments can also be properly combined to form other embodiments that can be understood by those skilled in the art.

The series of detailed descriptions listed above are only specific descriptions for feasible implementations of the present invention, and they are not intended to limit the protection scope of the present invention. Any equivalent implementation or implementation that does not depart from the technical spirit of the present invention All changes should be included within the protection scope of the present invention.

Claims (7)

1. A chip packaging structure comprises a base island, packaging materials, a first chip and a second chip, wherein the first chip is attached to the upper surface of the base island, the second chip is arranged far away from the upper surface of the base island compared with the first chip; the connecting columns comprise metal copper columns and tin ball bumps implanted at the lower ends of the metal copper columns, and any two connecting columns are separated from each other and are not in contact with each other; the upper end of the connecting column is planted in the base film layer, the lower end of the connecting column is welded to the upper surface of the base island through the convex spot, and the packaging material encapsulates the first chip and the second chip and is filled between the base island and the second chip.

2. The chip package structure according to claim 1, wherein the upper surface of the second chip is an electrical signal functional surface; the upper surface of the first chip is an electrical signal functional surface;

the packaging structure further comprises a pin, and electrical connection is established among any two of the second chip, the pin and the first chip through a lead;

the encapsulant also encapsulates the leads and covers the upper surfaces of the pins.

3. The chip package structure according to claim 1, wherein the first chip is mounted on the upper surface of the base island by a die attach adhesive;

and a part of the second chip and a part of the first chip are arranged in an up-and-down overlapping manner, and a mounting adhesive is filled between the second chip and the first chip.

4. A method for manufacturing a chip package structure includes:

forming a base film layer on the first surface of the second chip, wherein the base film layer is set as a sputtering metal film;

sequentially planting a metal copper column and a tin ball bump on the substrate film layer to obtain a plurality of connecting columns, wherein any two connecting columns are separated from each other and are not in contact with each other;

attaching a first chip to the upper surface of the base island;

welding the connecting column to the upper surface of the base island through the bump to fixedly mount the second chip to the base island;

and encapsulating by using an encapsulating material to obtain the chip encapsulating structure.

5. The method for manufacturing the chip package structure according to claim 4, wherein the step of forming the substrate film layer on the first surface of the second chip comprises:

attaching a protective film to a second surface of a second chip, wherein the second surface is opposite to the first surface and is an electrical signal functional surface of the second chip;

grinding and ultrasonically cleaning the first surface of the second chip;

and sputtering and forming a base film layer on the first surface of the second chip.

6. The method for manufacturing a chip package structure according to claim 4, wherein the step of implanting a copper pillar and a solder bump on the substrate film in sequence to obtain a plurality of connection posts comprises:

laying a photosensitive dry film on the substrate film layer;

carrying out partition exposure development on the photosensitive dry film to pattern a plurality of column planting openings exposing the substrate film layer on the photosensitive dry film;

sequentially planting a metal copper column and a tin ball salient point at the column planting opening to obtain a connecting column;

and removing the photosensitive dry film from the substrate film layer implanted with the connecting column.

7. The method for manufacturing the chip package structure according to claim 4, wherein before the encapsulating with the encapsulant, at least two of the first chip, the second chip and the pins are electrically connected by wires;

the method comprises the steps of forming a base film layer on a first surface of a second chip, and planting a copper metal column and a tin ball bump on the base film layer in sequence to obtain a plurality of connecting columns, wherein a plurality of second chips are integrated on the same wafer and are synchronously carried out in batch; and dicing the plurality of second chips from the wafer before the step of bonding the connection posts to the upper surface of the base island to secure the second chips to the base island.

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