CN112117287A - Image Sensor - Google Patents

Abstract

An image sensor is provided. The image sensor includes a substrate, a grid structure, and a color filter. The substrate includes pixel separation structures defining pixel regions and sub-pixel regions for each pixel region. The grid structure is disposed on the substrate, and includes a first fence portion disposed between sub-pixel regions and a second fence portion disposed between adjacent pixel regions. The mesh structure defines openings respectively corresponding to the sub-pixel regions. Color filters are disposed in openings defined by the mesh structure. Each color filter has a flat top surface, and the flat top surface of each color filter is parallel to its bottom surface.

Description

Image Sensor

This application claims Korean Patent Application No. 10-2019-0074388, filed in the Korean Intellectual Property Office on Jun. 21, 2019, and U.S. Patent No. 16/775,937, filed in the U.S. Patent and Trademark Office on Jan. 29, 2020 The priority of the applications, the entire contents of these two patent applications are hereby incorporated by reference.

technical field

The present disclosure relates to an image sensor and a method of fabricating the same, and more particularly, to an image sensor having improved electrical and optical properties and a method of fabricating the same.

Background technique

Image sensors convert photon images into electrical signals. Recent advances in the computer and communications industries have led to increased demand for high-performance image sensors in a variety of consumer electronic devices such as digital cameras, mobile phones, camcorders, personal communication systems (PCS), game controllers, security cameras, and medical miniature cameras. strong demand.

SUMMARY OF THE INVENTION

One aspect provides an image sensor with improved electrical and optical properties.

The aspects are not limited to those mentioned above, and other aspects not mentioned above will be clearly understood by those skilled in the art from the following description.

According to an aspect of some example embodiments, there is provided an image sensor comprising: a substrate including a pixel separation structure defining a plurality of pixel regions and a plurality of sub-regions for each pixel region of the plurality of pixel regions A pixel area; a grid structure, disposed on the substrate, and comprising a first fence portion disposed between sub-pixel areas and a second fence portion disposed between adjacent pixel areas, the mesh structure defining a plurality of sub-pixel areas, respectively a plurality of openings corresponding to the pixel area; and a plurality of color filters disposed in the openings defined by the grid structure, each color filter having a flat top surface, the flat top surface of each color filter being parallel to the bottom surface.

According to another aspect of some example embodiments, there is provided an image sensor including a substrate having a first surface and a second surface opposite the first surface, the substrate including pixel separations defining a plurality of pixel regions structure; a device isolation layer disposed adjacent to the first surface of the substrate on each of the plurality of pixel regions, the device isolation layer defining an active region in the plurality of pixel regions; a plurality of layers an inter-dielectric layer stacked on the first surface of the substrate and including contact plugs and connection lines; a fixed charge layer disposed on the second surface of the substrate; a flat dielectric layer disposed on the fixed charge layer; a grid a structure disposed on the flat dielectric layer to overlap the pixel separation structure in plan view, the grid structure including fence portions disposed between adjacent pixel regions, the grid structure defining respectively corresponding to the plurality of pixel regions a plurality of openings; a plurality of color filters arranged in the openings defined by the grid structure; a sacrificial flat layer located between adjacent color filters in the plurality of color filters, the sacrificial flat layer having the same The uppermost surface of each color filter is a coplanar top surface; and a microlens array is disposed on the plurality of color filters.

According to another aspect of some example embodiments, there is provided a method of fabricating an image sensor, the method comprising the steps of: providing a substrate having a plurality of pixel regions and a plurality of sub-pixel regions for each pixel region; on the substrate A grid structure is formed, and the grid structure includes a first fence part arranged between sub-pixel regions and a second fence part arranged between adjacent pixel regions; an initial color filter is formed on the pixel region, and the initial color filter The filter fills the space defined by the grid structure, wherein, in each pixel area, the corresponding initial color filter covers the first fence portion of the grid structure in the pixel area; a sacrificial flat layer is formed to cover the initial color filter a top surface; and performing a planarization process on the sacrificial planarization layer to form a color filter on the pixel area, the color filter having a planar top surface parallel to its bottom surface after the planarization process.

Description of drawings

1 illustrates a simplified plan view showing an image sensor in accordance with some example embodiments;

2A and 2B illustrate circuit diagrams showing an active pixel sensor array of an image sensor according to some example embodiments;

3 illustrates a simplified plan view showing an active pixel sensor array of an image sensor according to some example embodiments;

4A illustrates a plan view showing an image sensor according to some example embodiments;

4B illustrates a cross-sectional view taken along line II' of FIG. 4A showing an image sensor according to some example embodiments;

Figures 5A-5C show enlarged views showing section A of Figure 4B;

6 illustrates a cross-sectional view taken along line II' of FIG. 4A showing an image sensor according to some example embodiments;

Figures 7A and 7B show enlarged views showing section B of Figure 6;

8 illustrates a cross-sectional view taken along line II' of FIG. 4A showing an image sensor according to some example embodiments;

Figures 9A and 9B show enlarged views showing section C of Figure 8;

10A illustrates a cross-sectional view taken along line II' of FIG. 4A showing an image sensor according to some example embodiments;

Fig. 10B shows an enlarged view showing section D of Fig. 10A;

11 illustrates a cross-sectional view showing an image sensor according to some example embodiments;

12A illustrates a plan view showing an image sensor according to some example embodiments;

12B illustrates a cross-sectional view taken along line II-II' of FIG. 12A showing an image sensor according to some example embodiments;

13 illustrates a circuit diagram showing an active pixel sensor array of an image sensor according to some example embodiments;

14 shows a block diagram showing an image sensor according to some example embodiments;

15 illustrates a cross-sectional view showing an image sensor in accordance with some example embodiments;

16A-16H illustrate cross-sectional views taken along line II' of FIG. 4A showing a method of fabricating an image sensor according to some example embodiments; and

17A-17D illustrate cross-sectional views taken along line II' of FIG. 4A showing a method of fabricating an image sensor according to some example embodiments.

Detailed ways

An image sensor and a method of fabricating the same according to some example embodiments will be discussed in conjunction with the accompanying drawings.

1 illustrates a simplified plan view showing an image sensor in accordance with some example embodiments.

Referring to FIG. 1 , an image sensor may include a pixel array region R1 and a pad (pad, may also be referred to as “pad”) region R2.

A plurality of unit pixels P may be two-dimensionally arranged in the row direction and the column direction on the pixel array region R1. Each unit pixel P of the pixel array region R1 may output an electrical signal converted from incident light. The pixel array area R1 may include a center area (see CR of FIG. 11 ) and an edge area (see ER of FIG. 11 ) surrounding the center area CR. For example, the edge regions ER may be disposed on the top, bottom, left, and right sides of the center region CR when viewed in a plane. The pad region R2 may include a plurality of conductive pads CP for inputting and outputting control signals and photoelectric conversion signals. For easy connection with external devices, the pad area R2 may surround the pixel array area R1 when viewed in a plane.

2A and 2B illustrate circuit diagrams showing an active pixel sensor array of an image sensor according to some example embodiments.

2A , the active pixel sensor array may include a plurality of unit pixels P, and each unit pixel P may include first and second photoelectric conversion elements PD1 and PD2, first and second transfer transistors TX1 and TX2, and Logic transistors RX, SX and AX. The logic transistors RX, SX, and AX may include a reset transistor RX, a selection transistor SX, and an amplifier transistor AX. The gate electrode of the first transfer transistor TX1, the gate electrode of the second transfer transistor TX2, the gate electrode of the reset transistor RX, and the gate electrode of the selection transistor SX may be correspondingly connected to the driving signal lines TG1, TG2, RG, and SG, respectively.

The first transfer transistor TX1 may include a first transfer gate electrode connected to the driving signal line TG1. The first transfer transistor TX1 may be connected to the first photoelectric conversion element PD1. The second transfer transistor TX2 may include a second transfer gate electrode connected to the driving signal line TG2. The second transfer transistor TX2 may be connected to the second photoelectric conversion element PD2. The first transfer transistor TX1 and the second transfer transistor TX2 may share a charge detection node FD (ie, a floating diffusion region).

The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 can generate and accumulate photocharges proportional to the amount of external incident light thereon. The first transfer gate electrode and the second transfer gate electrode may transfer the charges accumulated in the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 to the charge detection node FD (ie, the floating diffusion region). The first transfer gate electrode and the second transfer gate electrode may receive complementary signals. For example, charges may be transferred from one of the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 to the charge detection node FD. At a later time, charges may be transferred from the other of the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 to the charge detection node FD.

The charge detection node FD may receive and accumulate charges generated from the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2. The amplifier transistor AX can be controlled by the amount of photocharge accumulated in the charge detection node FD.

The reset transistor RX may periodically reset the charges accumulated in the charge detection node FD. For example, the reset transistor RX may have a drain electrode connected to the charge detection node FD and a source electrode connected to the power supply voltage _VDD . When the reset transistor RX is turned on, the charge detection node FD may receive the power supply voltage V _DD connected to the source electrode of the reset transistor RX. Therefore, when the reset transistor RX is turned on, the charges accumulated in the charge detection node FD are depleted, and thus the charge detection node FD can be reset.

The amplifier transistor AX can amplify the change in the potential at the charge detection node FD, and can output the amplified signal or the pixel signal to the output line V _OUT through the selection transistor SX. The amplifier transistor AX may be a source follower buffer amplifier configured to generate a source-drain current proportional to the amount of photocharge applied to the gate electrode. The amplifier transistor AX may have a gate electrode connected to the charge detection node FD, a drain electrode connected to the power supply voltage _VDD , and a source electrode connected to the drain electrode of the selection transistor SX.

The selection transistor SX can select the unit pixel P of each row to be read out. When the selection transistor SX is turned on, the power supply voltage V _DD connected to the drain electrode of the amplifier transistor AX may be transferred to the drain electrode of the selection transistor SX.

2B , the active pixel sensor array may include a plurality of unit pixels P, and each unit pixel P may include four photoelectric conversion elements PD1 , PD2 , PD3 and PD4 and four transfer transistors TX1 , TX2 , TX3 and TX4 . The four transfer transistors TX1, TX2, TX3 and TX4 may share the charge detection node FD and logic transistors RX, SX and AX. In the example embodiment shown in FIG. 2B , according to the signals applied to the four transfer transistors TX1 , TX2 , TX3 and TX4 , charges can be transferred from one of the four photoelectric conversion elements PD1 , PD2 , PD3 and PD4 to charges Detect node FD.

3 illustrates a simplified plan view showing an active pixel sensor array of an image sensor according to some example embodiments.

3, the active pixel sensor array may include a plurality of pixel regions P1, P2 and P3 arranged in a matrix shape along the first and second directions D1 and D2. The plurality of pixel areas P1, P2 and P3 may include a first pixel area P1, a second pixel area P2 and a third pixel area P3, each of the first pixel area P1, the second pixel area P2 and the third pixel area P3 Light having a wavelength band different from that of light incident on other pixel regions in the first pixel region P1 , the second pixel region P2 , and the third pixel region P3 may be received.

In some example embodiments, the number of the first pixel regions P1 may be twice as large as the number of the second pixel regions P2 or the number of the third pixel regions P3. The first pixel area P1 may be arranged in a diagonal direction, and the second pixel area P2 and the third pixel area P3 may be arranged in a diagonal direction. As shown in FIG. 3, each of the first pixel regions P1 may be disposed between the second pixel regions P2 in the first direction D1 (or in the second direction D2) and in the second direction D2 (or in the second direction D2). One direction D1) is disposed between the third pixel regions P3.

Each of the first pixel area P1, the second pixel area P2 and the third pixel area P3 may include a plurality of sub-pixel areas PG1/PG2, PB or PR. For example, each of the first pixel area P1 , the second pixel area P2 and the third pixel area P3 may include a plurality of sub-pixel areas PG1 / PG2 , PB or PR arranged in a 2×2 quaternary matrix shape. Specifically, in some example embodiments, each first pixel region P1 may include a plurality of first sub-pixel regions PG1 or PG2, and each second pixel region P2 may include a plurality of second sub-pixel regions PR. Each third pixel area P3 may include a plurality of third sub-pixel areas PB.

The first sub-pixel regions PG1/PG2 may receive light having a first wavelength band, and the second sub-pixel region PR may receive light having a second wavelength band, and the second wavelength band is longer than the first wavelength band. The third sub-pixel region PB may receive light having a third wavelength band, which is shorter than the first wavelength band. For example, green light may be incident on the first sub-pixel region PG1/PG2, red light may be incident on the second sub-pixel region PR, and blue light may be incident on the third sub-pixel region PB.

In some example embodiments, each of the first sub-pixel region PG1/PG2, the second sub-pixel region PR, and the third sub-pixel region PB may include the photoelectric conversion elements and transmission elements discussed above with reference to FIG. 2A or FIG. 2B transistor. For example, each of the first sub-pixel region PG1/PG2, the second sub-pixel region PR, and the third sub-pixel region PB may include the unit pixel discussed with reference to FIG. 2A or 2B.

4A illustrates a plan view showing an image sensor according to some example embodiments. 4B illustrates a cross-sectional view taken along line II' of FIG. 4A showing an image sensor according to some example embodiments. 5A to 5C show enlarged views showing section A of FIG. 4B.

Referring to FIGS. 4A and 4B , an image sensor according to some example embodiments may include a semiconductor substrate 100 . The semiconductor substrate 100 may have a first surface 100a and a second surface 100b facing away from each other. The photoelectric conversion region 110 may be disposed on the semiconductor substrate 100 . The readout circuit layer may be disposed on the first surface 100 a (or the front surface) of the semiconductor substrate 100 , and the light-transmitting layer may be disposed on the second surface 100 b (or the rear surface) of the semiconductor substrate 100 .

The semiconductor substrate 100 may be a first conductivity type (eg, p-type) bulk silicon substrate on which an epitaxial layer having a first conductivity type is formed. Alternatively, the semiconductor substrate 100 may be a p-type epitaxial layer that remains after the bulk silicon substrate is removed in a manufacturing process for an image sensor. Alternatively, the semiconductor substrate 100 may be a bulk semiconductor substrate including a first conductivity type well.

As discussed above with reference to FIG. 3 , the semiconductor substrate 100 may include the first pixel area P1 , the second pixel area P2 and the third pixel area P3 arranged in a quaternary matrix, and the first pixel area P1 , the second pixel area Each of P2 and the third pixel region P3 may receive light having a wavelength band different from that of light incident on other pixel regions in the first pixel region P1, the second pixel region P2 and the third pixel region P3.

As discussed above, the first pixel area P1, the second pixel area P2 and the third pixel area P3 may include a plurality of corresponding sub-pixel areas PG1/PG2, PR and PB, respectively. Each first pixel region P1 may include a plurality of first sub-pixel regions PG1 or PG2, and each second pixel region P2 may include a plurality of second sub-pixel regions PR. Each third pixel area P3 may include a plurality of third sub-pixel areas PB. The respective sub-pixel regions PG1 / PG2 , PR and PB of the first pixel region P1 , the second pixel region P2 and the third pixel region P3 may have the same size and may be defined by the pixel separation structure 103 . For example, as shown in FIGS. 4A and 4B , at least two first subpixel regions PG1 may be disposed between adjacent second subpixel regions PR.

The pixel separation structure 103 may extend vertically from the first surface 100a of the semiconductor substrate 100 to the second surface 100b. The pixel separation structure 103 may penetrate the semiconductor substrate 100 . In this case, the pixel separation structure 103 may have substantially the same vertical thickness as that of the semiconductor substrate 100 . Alternatively, in some example embodiments, the pixel separation structure 103 may extend vertically from the first surface 100a of the semiconductor substrate 100 toward but not reach the second surface 100b.

In some example embodiments, as shown in FIG. 4B , the pixel separation structure 103 may have a first width adjacent to the first surface 100 a of the semiconductor substrate 100 and a width smaller than the first width adjacent to the second surface 100 b of the semiconductor substrate 100 A width of a second width. The pixel separation structure 103 may have a width gradually decreasing from the first surface 100 a to the second surface 100 b of the semiconductor substrate 100 . Alternatively, in some example embodiments, the pixel separation structure 103 may have a uniform width and may penetrate the semiconductor substrate 100 .

When viewed in a plane, as shown in FIG. 4A , the pixel separation structure 103 may surround each of the first subpixel region PG1 / PG2 , the second subpixel region PR, and the third subpixel region PB. For example, the pixel separation structure 103 may include first parts 103a extending parallel to each other in the first direction D1 and spaced apart from each other in the second direction D2, and further including extending parallel to each other in the second direction D2 while crossing the first parts 103a And the second portions 103b are spaced apart from each other in the first direction D1.

In some example embodiments, each of the first sub-pixel region PG1/PG2, the second sub-pixel region PR, and the third sub-pixel region PB may have a space between adjacent first portions 103a and/or The width corresponding to the interval between adjacent second portions 103b. The first portion 103a of the pixel separation structure 103 may have a pitch in a range of, for example, about 50 μm to about 100 μm. For example, the first portion 103a of the pixel separation structure 103 may have a pitch of about 70 μm.

The pixel separation structure 103 may be formed of a dielectric material having a refractive index smaller than that of the semiconductor substrate 100 , and may include a single dielectric layer or a plurality of dielectric layers. For example, the semiconductor substrate 100 may be silicon. For example, the pixel separation structure 103 may be formed of a silicon oxide layer, a silicon nitride layer, an undoped polysilicon layer, air, or a combination thereof. The pixel separation structure 103 can prevent crosstalk between adjacent sub-pixel regions in the first sub-pixel region PG1/PG2, the second sub-pixel region PR, and the third sub-pixel region PB.

The photoelectric conversion regions 110 may be correspondingly disposed on the first sub-pixel regions PG1/PG2, the second sub-pixel region PR and the third sub-pixel region PB. The photoelectric conversion region 110 may be formed by implanting the semiconductor substrate 100 with an impurity having a second conductivity type opposite to that of the semiconductor substrate 100 . A photodiode may be formed at a junction between the semiconductor substrate 100 having the first conductivity type and the photoelectric conversion region 110 having the second conductivity type. The photoelectric conversion region 110 may generate photocharge proportional to the magnitude of incident light.

In some example embodiments, each of the photoelectric conversion regions 110 may have a difference in impurity concentration between a portion adjacent to the first surface 100 a and a portion adjacent to the second surface 100 b , so that the semiconductor substrate 100 may have a difference in impurity concentration. A potential slope is provided between the first surface 100a and the second surface 100b. For example, each photoelectric conversion region 110 may include a plurality of vertically stacked impurity portions.

The device isolation layer 101 may be disposed adjacent to the first surface 100a of the semiconductor substrate 100 on each of the first subpixel region PG1/PG2, the second subpixel region PR, and the third subpixel region PB. The device isolation layer 101 may define an active region of the semiconductor substrate 100 .

The readout circuit may be disposed on the first surface 100 a of the semiconductor substrate 100 . The readout circuit may include the MOS transistors discussed with reference to Figures 2A and 2B. On each of the sub-pixel regions PG1/PG2, PR, and PB, the transfer gate electrode TG may be provided on the first surface 100a of the semiconductor substrate 100, and the readout circuit discussed with reference to FIGS. 2A and 2B may also be provided on the first surface 100a of the semiconductor substrate 100. on the first surface 100 a of the semiconductor substrate 100 .

The transfer gate electrode TG may be disposed on a central portion of each of the sub-pixel regions PG1/PG2, PR, and PB when viewed in a plane. A portion of the transfer gate electrode TG may be disposed within the semiconductor substrate 100 , and a gate dielectric layer may be interposed between the transfer gate electrode TG and the semiconductor substrate 100 . The floating diffusion region FD may be provided in the semiconductor substrate 100 on one side of the transfer gate electrode TG. The floating diffusion region FD may be formed by implanting the semiconductor substrate 100 with an impurity of a conductivity type opposite to that of the semiconductor substrate 100 . For example, the floating diffusion region FD may be an n-type impurity region.

Interlayer dielectric layers 211, 213 and 215 may be stacked on the first surface 100a of the semiconductor substrate 100, and may cover transfer gate electrodes TG and MOS transistors constituting a readout circuit. The interlayer dielectric layers 211, 213, and 215 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride. A connection line CL may be disposed on each of the interlayer dielectric layers 211, 213, and 215, and the connection line CL may be electrically connected to the readout circuit through the contact plug CT.

The fixed charge layer 300 may be disposed on the second surface 100 b of the semiconductor substrate 100 . The fixed charge layer 300 may prevent the photoelectric conversion region 110 from receiving charges (eg, electrons or holes) generated from defects existing on the second surface 100 b of the semiconductor substrate 100 . The fixed charge layer 300 may include a single layer or multiple layers. For example, the fixed charge layer 300 may include a metal oxide or a metal fluoride, the metal oxide or the metal fluoride including from hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti) At least one metal selected from the group consisting of , yttrium (Y) and lanthanide (Ln). For example, the fixed charge layer 300 may include one or more of an aluminum oxide layer and a hafnium oxide layer. The fixed charge layer 300 may have a thickness in the range of about 1 nm to about 50 nm.

The flat dielectric layer 310 may be disposed on the fixed charge layer 300 . The planarization dielectric layer 310 may include a first planarization layer 311, a second planarization layer 313, and a third planarization layer 315 (see FIG. 5A) sequentially stacked. The first planarization layer 311, the second planarization layer 313, and the third planarization layer 315 may include transparent dielectric materials. The first flattening layer 311, the second flattening layer 313, and the third flattening layer 315 may have refractive indices different from each other. The first flattening layer 311, the second flattening layer 313, and the third flattening layer 315 may be combined with each other to have an appropriate thickness, which causes a high refractive index. For example, the first flat layer 311 may be thicker than the fixed charge layer 300 . The second flat layer 313 may be thicker than the first flat layer 311 . The third planarization layer 315 may be thinner than the second planarization layer 313 .

The first flattening layer 311 and the third flattening layer 315 may have the same refractive index, and the second flattening layer 313 may have a refractive index different from the refractive index of the first flattening layer 311 and the refractive index of the third flattening layer 315 . For example, the first planarization layer 311 and the third planarization layer 315 may include metal oxide, and the second planarization layer 313 may include silicon oxide.

The mesh structure 320 may be disposed on the flat dielectric layer 310 . Similar to the pixel separation structure 103, the grid structure 320 may have a grid shape when viewed in a plane. The grid structure 320 may overlap the pixel separation structure 103 when viewed in a plane. For example, the mesh structure 320 may include a first portion extending in the first direction D1 and a second portion extending in the second direction D2 while intersecting the first portion. The mesh structure 320 may be disposed between the photoelectric conversion regions 110 of the sub-pixel regions PG1/PG2, PR and PB. As shown in FIG. 4B , the grid structure 320 may have substantially the same width as the minimum width of the pixel separation structure 103 , or may have a width smaller than the minimum width of the pixel separation structure 103 .

至大约

的范围内的高度。网格结构320可以具有在大约50nm至大约150nm的范围内的宽度。The mesh structure 320 may refract light obliquely incident through the microlenses 353, and then may cause the refracted light to enter the photoelectric conversion regions 110 of the sub-pixel regions PG1/PG2, PR, and PB. The grid structure 320 may have an aspect ratio in the range of about 2:1 to about 5:1. The grid structure 320 may have a

to approx.

height within the range. The mesh structure 320 may have a width in the range of about 50 nm to about 150 nm.

The mesh structure 320 may include light blocking patterns 322 and low refractive index patterns 324 sequentially stacked on the flat dielectric layer 310 . The light shielding pattern 322 may be disposed between the low refractive index pattern 324 and the flat dielectric layer 310 . The light shielding pattern 322 may include a metal material such as titanium, tantalum or tungsten.

The low refractive index pattern 324 may include a material whose refractive index is smaller than that of the color filters 345a and 345b. The low refractive index pattern 324 may include an organic material, and may have a refractive index in a range of about 1.1 to about 1.3. For example, the grid structure 320 may be a polymer layer including silica nanoparticles. Since the low refractive index pattern 324 has a low refractive index, it may be possible to increase the amount of light incident on the photoelectric conversion region 110 and reduce crosstalk between the sub-pixel regions PG1/PG2, PR, and PB. In this configuration, each photoelectric conversion region 110 can improve light receiving efficiency and improve signal-to-noise ratio (SNR).

The protective layer 330 may be disposed on the flat dielectric layer 310 to cover the flat dielectric layer 310 and the surface of the mesh structure 320 on the flat dielectric layer 310 with a substantially uniform thickness. For example, the protective layer 330 may be directed from the space between the sidewall of any one of the color filters 345a and 345b and the sidewall of the mesh structure 320 toward the flat dielectric layer 310 and any one of the color filters 345a and 345b The space between the bottom surfaces extends.

至大约

的范围内的厚度。保护层330可以保护滤色器345a和345b，并且可以用于吸收湿气。在一些示例实施例中，保护层330可以形成为具有大约

至大约

的厚度，因此不会对入射到子像素区域PG1/PG2、PR和PB上的光的路径有影响。The protective layer 330 may be a single layer or multiple layers including, for example, one or more of aluminum oxide and silicon oxycarbide. In some example embodiments, the protective layer 330 may have a

to approx.

thickness within the range. The protective layer 330 may protect the color filters 345a and 345b, and may function to absorb moisture. In some example embodiments, the protective layer 330 may be formed to have approximately

to approx.

Therefore, it will not affect the path of the light incident on the sub-pixel regions PG1/PG2, PR and PB.

In some example embodiments, the mesh structure 320 may have openings O, each opening O being formed by a pair of first portions of the mesh structure 320 extending in the first direction D1 and by a pair of first portions of the mesh structure 320 in the second direction A pair of second portions extending on D2 defines that the opening O may overlap with the photoelectric conversion regions 110 of the sub-pixel regions PG1/PG2, PR and PB.

The color filters 345a and 345b may be disposed in the openings defined by the mesh structure 320 . For example, the first color filter 345a may be disposed on the corresponding first sub-pixel area PG1/PG2 of the first pixel area P1, and the second color filter 345b may be disposed on the corresponding second sub-pixel in the second pixel area P2 Regional PR. Likewise, a third color filter (not shown in FIG. 4B ) may be disposed on the corresponding third sub-pixel area PB of the third pixel area (see P3 of FIG. 3 ). The first color filter 345a, the second color filter 345b and the third color filter may include a green color filter, a red color filter and a blue color filter, respectively. Alternatively, the first color filter 345a, the second color filter 345b and the third color filter may include a magenta color filter, a yellow color filter and a cyan color filter, respectively. Although three types of color filters are provided as mentioned above, in some example embodiments, four types of color filters may be provided.

In some example embodiments, as shown in FIG. 4B , at least two first color filters 345a may be disposed between adjacent second color filters 345b. The grid structure 320 may include a first barrier part FS1 disposed between the sub-pixel areas PG1/PG2, PR and PB of the pixel areas P1, P2 and P3, and may further include a first barrier part FS1 disposed between the different pixel areas P1, P2 and P3 between the second fence section FS2. For example, the first fence part FS1 of the mesh structure 320 may be disposed between the color filters 345a or 345b whose colors are the same as each other, and the second fence part FS2 of the mesh structure 320 may be disposed between the color filters whose colors are different from each other between devices 345a and 345b.

至大约

的范围内。滤色器345a和345b中的每个可以具有基本平坦的顶表面，并且滤色器345a和345b的顶表面可以平行于滤色器345a和345b的底表面。Each of the color filters 345 a and 345 b may have a first sidewall S1 adjacent to the first fence portion FS1 of the mesh structure 320 and a second sidewall S1 adjacent to the second fence portion FS2 of the mesh structure 320 S2. The first side wall S1 may have substantially the same height H1 as the height H2 of the second side wall S2. For example, the difference between the first height H1 of the first side wall S1 and the second height H2 of the second side wall S2 may be approximately

to approx.

In the range. Each of the color filters 345a and 345b may have a substantially flat top surface, and the top surfaces of the color filters 345a and 345b may be parallel to the bottom surfaces of the color filters 345a and 345b.

4B and 5A , the protective layer 330 may cover the top surface of the grid structure 320, and the top surfaces of the color filters 345a and 345b may be substantially common with the top surface of the protective layer 330 on the top surface of the grid structure 320 noodle. For example, the top surface of the grid structure 320 may be positioned at substantially the same level as the level of the top surface of the protective layer 330 . Referring to FIG. 5B , the top surfaces of the color filters 345 a and 345 b may be positioned at a lower level than that of the top surface of the mesh structure 320 . Referring to FIG. 5C , the protection pattern 331 may directly cover the sidewalls of the mesh structure 320 and the bottom surfaces of the color filters 345a and 345b. That is, unlike the protection patterns 330 , in some example embodiments, the protection patterns 331 may not be disposed along the top surface of the mesh structure 320 . The top surface of the protection pattern 331 may be positioned at substantially the same level as the top surface of the mesh structure 320 , and the top surfaces of the color filters 345 a and 345 b may be positioned at a lower level than the top surface of the mesh structure 320 . level.

Referring back to FIGS. 4A and 4B , the microlens array 350 may be disposed on a color filter array including a first color filter 345a, a second color filter 345b, and a third color filter. The microlens array 350 may include a flat portion 351 adjacent to the color filters 345a and 345b, and may further include microlenses 353 on the flat portion 351 corresponding to the sub-pixel regions PG1/PG2, PR, and PB.

Since the first color filter 345a, the second color filter 345b and the third color filter have substantially flat top surfaces, the flat portion 351 may be in the first color filter 345a, the second color filter 345b and the third color filter The shader has a substantially uniform thickness on the top surface. For example, the flat portion 351 may have substantially the same thickness on the first side wall S1 and the second side wall S2 of each of the color filters 345a and 345b. The microlenses 353 may be correspondingly disposed on the sub-pixel regions PG1/PG2, PR, and PB, and may each have an upwardly convex shape. In some example embodiments, since the flat portion 351 has a reduced thickness distribution with respect to the microlens array 350 , it may be possible to improve the light collection efficiency by the microlens 353 .

The passivation layer 360 may conformally cover the top surface of the microlens array 350 . The passivation layer 360 may be formed of, for example, an inorganic oxide.

In the following description, for the sake of brevity of description, the same features as those of the image sensor discussed above may be omitted in some cases.

6 illustrates a cross-sectional view taken along line II' of FIG. 4A showing an image sensor according to some example embodiments. 7A and 7B show enlarged views showing section B of FIG. 6 .

6, 7A and 7B, as discussed above, each of the color filters 345a and 345b may have a substantially flat top surface. Furthermore, as shown in FIG. 6 , the top surfaces of the color filters 345 a and 345 b may be positioned at a level higher than that of the top surface of the mesh structure 320 . The mesh structure 320 may have a height smaller than thicknesses of the color filters 345a and 345b. The thickness of each of the color filters 345 a and 345 b on the flat dielectric layer 310 may be different from the thickness of each of the color filters 345 a and 345 b on the grid structure 320 .

至大约

的范围。The first color filter 345a may be disposed on the first pixel region P1 and on the plurality of first sub-pixel regions PG1. The first color filters 345a may be connected or continuous on the first fence portion FS1 of the mesh structure 320, which is disposed between the first sub-pixel regions PG1. For example, on each of the first sub-pixel regions PG1, the first color filter 345a may cover the top surface of the first barrier portion FS1 of the grid structure 320 (eg, see the middle grid structure 320 in FIG. 6). Even though each of the color filters 345a and 345b covers the first fence portion FS1 of the mesh structure 320, the first sidewall S1 adjacent to the first fence portion FS1 of the mesh structure 320 and the first sidewall S1 adjacent to the mesh structure 320 The height difference between the adjacent second side walls S2 of the two fence portions FS2 may also be approximately

to approx.

range.

至大约

的范围内(例如，在大约

至大约

的范围内)的高度。滤色器345a和345b可以具有范围在大约

至大约

的范围内的厚度。参照图7B，在一些示例性实施例中，网格结构320可以包括金属材料，并且具有在大约

至大约

的范围内的高度。Referring to FIG. 7A , the mesh structure 320 may include light-shielding patterns 322 and low-refractive index patterns 324 that are sequentially stacked. The low refractive index pattern 324 may have a

to approx.

range (for example, around

to approx.

range) height. The color filters 345a and 345b may have a range between about

to approx.

thickness within the range. Referring to FIG. 7B , in some exemplary embodiments, the mesh structure 320 may include a metallic material and have a thickness of about

to approx.

height within the range.

8 illustrates a cross-sectional view taken along line II' of FIG. 4A showing an image sensor according to some example embodiments. 9A and 9B illustrate enlarged views showing section C of FIG. 8 .

8 , each of the color filters 345a and 345b may have different thicknesses at portions adjacent to the first and second fence portions FS1 and FS2 of the mesh structure 320, respectively. In other words, as shown in FIG. 8 , the thickness t1 of each of the color filters 345a and 345b adjacent to the first fence portion FS1 may be greater than the thickness t1 of the color filters 345a and 345b adjacent to the second fence portion FS2 The thickness t2 of each. The sacrificial flat layer 355 may partially remain between the adjacent first and second color filters 345a and 345b. The sacrificial planarization layer 355 may have a top surface that is substantially coplanar with uppermost surfaces of the first and second color filters 345a and 345b.

至大约

的范围内。Referring to FIG. 9A , in some example embodiments, each of the color filters 345 a and 345 b may have a minimum thickness and a maximum thickness that are both greater than the height of the grid structure 320 . Each of the color filters 345a and 345b may have a maximum thickness at a portion adjacent to the first fence portion FS1 of the mesh structure 320a, and at a portion adjacent to the second fence portion FS2 of the mesh structure 320b with minimum thickness. The difference between the maximum thickness and the minimum thickness of each of the color filters 345a and 345b may be around

to approx.

In the range.

9B , in some example embodiments, each of the color filters 345a and 345b may have a level at substantially the same level as the level of the top surface of the protective layer 330 covering the top surfaces of the mesh structures 320a and 320b top surface. In this configuration, the minimum thickness of each of the color filters 345a and 345b may be less than the height of the mesh structures 320a and 320b.

10A illustrates a cross-sectional view taken along line II' of FIG. 4A showing an image sensor according to some example embodiments. Fig. 10B shows an enlarged view showing section D of Fig. 10A.

Referring to FIGS. 10A and 10B , a flat dielectric layer 310 may be disposed on the second surface 100 b of the semiconductor substrate 100 , and the mesh structure 320 may have a lower portion within the flat dielectric layer 310 . For example, the lower portion of the mesh structure 320 may penetrate the flat dielectric layer 310 .

The fixed charge layer 300 may be disposed between the flat dielectric layer 310 and the second surface 100 b of the semiconductor substrate 100 , and the mesh structure 320 may have a bottom surface in contact with the fixed charge layer 300 . Optionally, in some example embodiments, the bottom surface of the grid structure 320 may be in contact with the pixel separation structure 103 . The flat dielectric layer 310 may include a first flat layer 311 and a second flat layer 313 sequentially stacked. The first flattening layer 311 and the second flattening layer 313 may have different refractive indices and different thicknesses.

The mesh structure 320 may include a material whose refractive index is smaller than that of the semiconductor substrate 100 . For example, the semiconductor substrate 100 may be, for example, silicon. For example, the mesh structure 320 may be formed of a low refractive index material having a refractive index of about 1.3 or less. For example, the grid structure 320 may be a polymer layer including silica nanoparticles.

11 illustrates a cross-sectional view showing an image sensor according to some example embodiments.

11 , as discussed above with reference to FIG. 1 , the semiconductor substrate 100 may include a pixel array region R1 and a pad region R2 around the pixel array region R1 , and the pixel array region R1 may include a center region CR and surrounding the center region CR and The edge region ER adjacent to the pad region R2.

The color filters 345a and 345b may have substantially flat top surfaces on the central region CR and the edge region ER. As shown in FIG. 11 , the color filters 345a and 345b may have a relatively small thickness on the edge region ER and a relatively large thickness on the central region CR. For example, on the central region CR, the top surfaces of the color filters 345a and 345b may be positioned at substantially the same level as the top surface of the protective layer 330, and on the edge region ER, the top surfaces of the color filters 345a and 345b The surface may be positioned at a lower level than the level of the top surface of the grid structure 320 .

On the pad region R2, the through plugs TPLG may be disposed to penetrate the semiconductor substrate 100, and the sidewall dielectric layer SS may surround sidewalls of the through plugs TPLG. On the pad region R2 , the connection line CL may be disposed on the first surface 100 a of the semiconductor substrate 100 , and the conductive pad CP may be disposed on the second surface 100 b of the semiconductor substrate 100 . The connection line CL of the pad region R2 may be connected to the connection line CL of the pixel array region R1. The through plug TPLG may electrically connect the connection line CL to the conductive pad CP.

12A illustrates a plan view showing an image sensor according to some example embodiments. 12B illustrates a cross-sectional view taken along line II-II' of FIG. 12A showing an image sensor according to some example embodiments.

Referring to FIGS. 12A and 12B , each of the first pixel area P1 , the second pixel area P2 and the third pixel area P3 discussed above with reference to FIG. 3 may include corresponding sub-pixel areas PG1 / PG2 , PR and PB pixel regions, these corresponding sub-pixel regions are arranged in a 3×3 matrix shape. For example, at least three first sub-pixel regions PG1/PG2 may be disposed between adjacent second sub-pixel regions PR.

The grid structure 320 may include a first fence part FS1 disposed between the sub-pixel regions PG1/PG2, PR and PB, and may further include a second fence part FS2 disposed between the pixel regions P1, P2 and P3. In this configuration, at least two first fence portions FS1 may be provided between the second fence portions FS2 spaced apart from each other.

As discussed above, the color filters 345a and 345b can fill the openings defined by the grid structure 320, and each of the color filters 345a and 345b can have a substantially flat surface.

13 illustrates a circuit diagram showing an active pixel sensor array of an image sensor according to some example embodiments.

13 , each unit pixel P may include a photoelectric conversion element PD1, an organic photoelectric conversion element OPD, first and second transfer transistors TX1 and TX2, and readout transistors RX, SX, and AX. As discussed with reference to FIG. 2A, the readout transistors may include a reset transistor RX, an amplifier transistor AX, and a select transistor SX.

The first transfer transistor TX1 may be connected to the photoelectric conversion element PD1, and the second transfer transistor TX2 may be connected to the organic photoelectric conversion element OPD. The first transfer transistor TX1 and the second transfer transistor TX2 may share a charge detection node FD (ie, a floating diffusion region).

The photoelectric conversion element PD1 and the organic photoelectric conversion element OPD can generate and accumulate photocharges proportional to the amount of external incident light. In some example embodiments, the photoelectric conversion element PD1 may be one of a photodiode, a phototransistor, a grating, a pinned photodiode (PPD), and a combination thereof. The organic photoelectric conversion element OPD may include an organic photoelectric conversion layer. The organic photoelectric conversion layer can generate photocharges (electron-hole pairs) proportional to incident light having a specific wavelength band. The difference in voltages applied to the opposite ends of the organic photoelectric conversion element OPD may cause the charge detection node FD to store photocharges generated from the organic photoelectric conversion layer.

The first transfer transistor TX1 and the second transfer transistor TX2 may transfer the charges accumulated in the photoelectric conversion element PD1 and the organic photoelectric conversion element OPD to the charge detection node FD. The first transfer transistor TX1 and the second transfer transistor TX2 may be controlled by charge transfer signals supplied through the first charge transfer line TG1 and the second charge transfer line TG2, and according to charges applied to the first transfer transistor TX1 and the second transfer transistor TX2 For the transfer signal, charges can be transferred from any one of the photoelectric conversion element PD1 and the organic photoelectric conversion element OPD to the charge detection node FD. Specifically, when the voltage V _PIX is applied to one of the terminals of the organic photoelectric conversion element OPD and the charge transfer signal is applied to the second transfer transistor TX2 , the generated electrons or holes may be transferred to the charge detection node FD and Accumulated in the charge detection node FD.

14 shows a block diagram showing an image sensor according to some example embodiments.

14 , the image sensor may include a plurality of unit pixels P two-dimensionally arranged along a first direction D1 and a second direction D2 crossing the first direction D1. Each unit pixel P of the image sensor may have a structure in which at least two photoelectric conversion elements are stacked in a third direction D3 perpendicular to the first direction D1 and the second direction D2. Each unit pixel P may include one of the first and second photoelectric conversion elements PD1 and PD2, one of the first and second color filters CF1 and CF2, and an organic photoelectric conversion element OPD. For example, the unit pixel P may include a first photoelectric conversion element PD1, a first color filter CF1, and an organic photoelectric conversion element OPD, and another unit pixel P may include a second photoelectric conversion element PD2, a second color filter CF2, and an organic photoelectric conversion element Photoelectric conversion element OPD, etc.

The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may be provided in the semiconductor substrate and may be arranged in a matrix shape. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may be arranged in a zigzag manner.

As shown in FIG. 14 , the organic photoelectric conversion elements OPD may be correspondingly stacked on the first photoelectric conversion elements PD1 and the second photoelectric conversion elements PD2 . For example, the organic photoelectric conversion element OPD may overlap with a corresponding one of the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 when viewed in a plane. The first color filter CF1 may be correspondingly disposed between the first photoelectric conversion element PD1 and the organic photoelectric conversion element OPD, and the second color filter CF2 may be correspondingly disposed between the second photoelectric conversion element PD2 and the organic photoelectric conversion element OPD. between.

In some example embodiments, the organic photoelectric conversion element OPD of the unit pixel P may receive the first incident light L1 , the second incident light L2 and the third incident light L3 having the first wavelength band, the second wavelength band and the third wavelength band, respectively The corresponding incident light in . The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 and the organic photoelectric conversion element OPD may each receive incident light having a wavelength band different from that of any other incident light, and may each generate light proportional to the amount of the incident light charge.

For example, the first photoelectric conversion element PD1 may generate first photocharges corresponding to the first incident light L1 having the first wavelength band. The second photoelectric conversion element PD2 may generate second photocharges corresponding to the second incident light L2 having the second wavelength band. The organic photoelectric conversion element OPD may generate third photocharges corresponding to the third incident light L3 having the third wavelength band. The first band may be longer than the third band, and the second band may be shorter than the third band. For example, the first incident light L1 having the first wavelength band may appear red, the second incident light L2 having the second wavelength band may appear blue, and the third incident light L3 having the third wavelength band may appear green.

The first incident light L1 with the first wavelength band may pass through the organic photoelectric conversion element OPD and the first color filter CF1, and then may enter the first photoelectric conversion element PD1, and the second incident light L2 with the second wavelength band may pass through the organic photoelectric conversion element OPD and the first color filter CF1. The photoelectric conversion element OPD and the second color filter CF2 can then enter the second photoelectric conversion element PD2. The third incident light L3 having the third wavelength band may enter the organic photoelectric conversion element OPD.

At the unit pixel P including the first photoelectric conversion element PD1, a first pixel signal S1 corresponding to the first incident light L1 having the first wavelength band may be output, and at the unit pixel P including the second photoelectric conversion element PD2, The second pixel signal S2 corresponding to the second incident light L2 having the second wavelength band may be output. In addition, the organic photoelectric conversion element OPD of the unit pixel P may output the third pixel signal S3 corresponding to the third incident light L3 having the third wavelength band. For example, the first photoelectric conversion element PD1 may generate photocharges corresponding to red light. The second photoelectric conversion element PD2 may generate photocharges corresponding to blue light. The organic photoelectric conversion element OPD can generate photocharges corresponding to green light.

15 illustrates a cross-sectional view showing an image sensor according to some example embodiments.

15 , as discussed above, the semiconductor substrate 100 may include therein a photoelectric conversion region 110 and a pixel separation structure defining pixel regions P1 and P2 (see 103 of FIGS. 4A and 4B ).

On each of the pixel regions P1 and P2, the transfer gate electrode TG may be provided on the first surface 100a of the semiconductor substrate 100, and the first floating diffusion region FD1 may be provided on the semiconductor substrate on one side of the transfer gate electrode TG 100 out of 100. The second floating diffusion region FD2 may be disposed in the semiconductor substrate 100 and spaced apart from the first floating diffusion region FD1.

The first floating diffusion region FD1 and the second floating diffusion region FD2 may be formed by implanting the semiconductor substrate 100 with impurities whose conductivity type is opposite to that of the semiconductor substrate 100 . For example, the first floating diffusion region FD1 and the second floating diffusion region FD2 may be n-type impurity regions.

The pixel regions P1 and P2 may have the through electrode structure 130 penetrating a part of the pixel separation structure 103 therebetween.

The through-electrode structure 130 may include: through-electrodes 134 vertically penetrating the semiconductor substrate 100 ; and through-dielectric patterns 132 surrounding sidewalls of the through-electrodes 134 . The through electrodes 134 may include conductive materials. The through electrodes 134 may include polysilicon or metal doped with n-type or p-type impurities. The through electrode 134 may have a width gradually decreasing from the first surface 100 a to the second surface 100 b of the semiconductor substrate 100 . The through-dielectric pattern 132 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

Interlayer dielectric layers 211, 213 and 215 may be disposed on the first surface 100a of the semiconductor substrate 100, and may cover the transfer gate electrodes TG and MOS transistors constituting the first readout circuit and the second readout circuit. A plurality of bottom contact plugs BCP1 to BCP3 may be disposed in the interlayer dielectric layers 211 , 213 and 215 . For example, the first bottom contact plug BCP1 may be coupled to the first floating diffusion region FD1, and the second bottom contact plug BCP2 may be coupled to the second floating diffusion region FD2. The third bottom contact plug BCP3 may be coupled to the through electrode 134 .

The first bottom contact plug BCP1 may be electrically connected to the reset transistor (see RX of FIG. 13 ) and the amplifier transistor (see AX of FIG. 13 ) through the first connection line CL1 . The second bottom contact plug BCP2 may be connected to the third bottom contact plug BCP3 through the second connection line CL2. For example, the through electrode 134 may be electrically connected to the second floating diffusion region FD2 through the second bottom contact plug BCP2, the third bottom contact plug BCP3 and the second connection line CL2.

The flat dielectric layer 310 may be disposed on the second surface 100b of the semiconductor substrate 100 . As discussed above, the planar dielectric layer 310 may comprise a single layer or multiple layers. The planar dielectric layer 310 may include metal oxides such as aluminum oxide and/or hafnium oxide.

The color filters 345a and 345b may be disposed on the flat dielectric layer 310 at the corresponding pixel regions P1 and P2. The color filters 345a and 345b may include a first color filter 345a on the first pixel area P1 and a second color filter 345b on the second pixel area P2.

The color filters 345a and 345b may be disposed in openings defined by the mesh structures 320 disposed on the flat dielectric layer 310 . The first color filter 345a may be disposed on the first pixel area P1, and the second color filter 345b may be disposed on the second pixel area P2. As discussed above, in some example embodiments, each of the color filters 345a and 345b may have a substantially flat top surface parallel to its bottom surface. The top surfaces of the color filters 345a and 345b may be positioned at a lower level than the level of the top surface of the mesh structure 320, or may be positioned at substantially the same level as the level of the top surface of the mesh structure 320.

The first upper flat layer BPL may cover the top surfaces of the color filters 345a and 345b. The first upper flat layer BPL is formed on the flat top surfaces of the color filters 345a and 345b, and may have substantially flat top surfaces.

The top contact plug TCP may penetrate through the first upper planarization layer BPL, a portion of the mesh structure 320 and the planar dielectric layer 310 to be bonded to the corresponding through electrodes 134 . Each top contact plug TCP may include a barrier metal layer formed of metal nitride such as titanium nitride, tantalum nitride or tungsten nitride, and may further include a metal layer formed of metal such as tungsten or copper.

The organic photoelectric conversion element OPD may be disposed on the first upper planarization layer BPL disposed on the second surface 100 b of the semiconductor substrate 100 . The organic photoelectric conversion element OPD may include a bottom electrode BE, a top electrode TE, and an organic photoelectric conversion layer OPL between the bottom electrode BE and the top electrode TE.

The bottom electrode BE may be disposed on the first upper flat layer BPL having a flat top surface. When viewed in a plane, the bottom electrodes BE may be disposed to correspond to the pixel regions P1 and P2 and may be spaced apart from each other. Each bottom electrode BE may be electrically connected to the second floating diffusion region FD2 through the corresponding top contact plug TCP, the through electrode 134, the second and third bottom contact plugs BCP2 and BCP3, and the second connection line CL2 .

The bottom electrode BE may include a transparent conductive material. For example, the bottom electrode BE may include ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), SnO ₂ , ATO (antimony doped tin oxide), AZO (aluminum doped zinc oxide), GZO (gallium doped tin oxide) One or more of zinc oxide), _TiO2 , and FTO (fluorine-doped tin oxide).

The organic photoelectric conversion layer OPL may be disposed on the bottom electrode BE. The organic photoelectric conversion layer OPL can selectively absorb light having a specific wavelength band, and thus can cause photoelectric conversion. The organic photoelectric conversion layer OPL may include a p-type organic semiconductor material and an n-type organic semiconductor material, and the p-type semiconductor material and the n-type semiconductor material form a p-n junction. In other embodiments, the organic photoelectric conversion layer OPL may include quantum dots or chalcogenides.

The top electrode TE may be disposed on the organic photoelectric conversion layer OPL. The top electrode TE may include a transparent conductive material, and may completely cover the pixel regions P1 and P2.

The encapsulation layer TFE may be disposed on the top electrode TE. The encapsulation layer TFE may be formed of a single layer or multiple layers. The encapsulation layer TFE may include, for example, an aluminum layer and a silicon oxynitride layer. The second upper planarization layer TPL may be disposed on the encapsulation layer TFE, and the microlens array 350 may be disposed on the second upper planarization layer TPL. The second upper planarization layer TPL may include a transparent dielectric material, eg, metal oxide or silicon oxide. The microlens array 350 may include microlenses corresponding to the pixel regions P1 and P2.

16A-16H illustrate cross-sectional views taken along line II' of FIG. 4A showing a method of fabricating an image sensor according to some example embodiments.

Referring to FIGS. 4A and 16A , a semiconductor substrate 100 having a first conductivity type (eg, p-type) may be provided. The semiconductor substrate 100 may have a first surface 100a and a second surface 100b facing away from each other.

In some example embodiments, the semiconductor substrate 100 may include a first pixel area, a second pixel area, and a third pixel area (see P1 , P2 and P3 of FIG. 3 ), each of the pixel areas P1 , P2 and P3 A plurality of sub-pixel regions may be included (see PG1/PG2, PR and PB in FIG. 3).

The photoelectric conversion region 110 may be formed in the semiconductor substrate 100 . On each of the sub-pixel regions PG1/PG2, PR, and PB, the photoelectric conversion region 110 may be formed by implanting the semiconductor substrate 100 with an impurity having a second conductivity type (eg, n-type) different from the first conductivity type .

The device isolation layer 101 may be formed to be adjacent to the first surface 100 a on each of the sub-pixel regions PG1 / PG2 , PR and PB and to define an active region on the semiconductor substrate 100 . The device isolation layer 101 may be formed by forming a shallow trench by patterning the first surface 100a of the semiconductor substrate 100, and then depositing a dielectric material in the shallow trench. The formation of the device isolation layer 101 may be performed before or after the formation of the photoelectric conversion region 110 .

The pixel separation structure 103 may be formed on the semiconductor substrate 100, thereby defining the sub-pixel regions PG1/PG2, PR and PB. The pixel separation structure 103 may be formed by forming deep trenches by patterning the first surface 100a and/or the second surface 100b of the semiconductor substrate 100, and then filling the deep trenches with a dielectric material.

4A and 16B, a metal oxide semiconductor (MOS) transistor may be formed on the first surface 100a of the semiconductor substrate 100 to constitute a readout circuit. For example, transfer gate electrodes TG may be formed on the first surface 100a of the semiconductor substrate 100, and a gate dielectric layer may be provided between the semiconductor substrate 100 and each transfer gate electrode TG. The gate electrode (not shown) of the MOS transistor may also be formed together with the transfer gate electrode TG.

After the transfer gate electrode TG is formed, a floating diffusion region FD may be formed in the semiconductor substrate 100 on one side of the transfer gate electrode TG. The floating diffusion region FD may be formed by implanting impurities having the second conductivity type. In addition, source/drain impurity regions (not shown) of the MOS transistor may also be formed together with the floating diffusion region FD.

Referring to FIGS. 4A and 16C , interlayer dielectric layers 211 , 213 and 215 , contact plugs CT, and connection lines CL may be formed on the first surface 100 a of the semiconductor substrate 100 . The interlayer dielectric layers 211, 213 and 215 may cover the first and second transfer transistors and the logic transistors. The interlayer dielectric layers 211, 213, and 215 may be formed of materials having excellent gap-filling properties, and may have their planarized upper portions.

Contact plugs CT may be formed in the interlayer dielectric layers 211 , 213 and 215 so as to be connected to the floating diffusion regions FD or MOS transistors. Connection lines CL may be formed between the interlayer dielectric layers 211 , 213 and 215 . The contact plug CT and the connection line CL may be made of, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), nitride Tantalum (TaN), zirconium nitride (ZrN), tungsten nitride (WN) or their alloys are formed.

Referring to FIGS. 4A and 16D, a thinning process may be performed to remove a portion of the semiconductor substrate 100, and thus the semiconductor substrate 100 may have a reduced vertical thickness. The semiconductor substrate 100 may be turned upside down to perform a thinning process thereon. A grinding process or a polishing process may be performed to remove a portion of the semiconductor substrate 100 , and then an anisotropic etching process or an isotropic etching process may be performed to remove remaining surface defects from the semiconductor substrate 100 . The thinning process for the semiconductor substrate 100 may expose the pixel separation structure 103 from the second surface 100 b of the semiconductor substrate 100 . For example, the pixel separation structure 103 may have a surface at substantially the same level as that of the surface of the second surface 100 b of the semiconductor substrate 100 .

After that, the fixed charge layer 300 may be formed on the second surface 100 b of the semiconductor substrate 100 . The fixed charge layer 300 may directly cover the second surface 100 b of the semiconductor substrate 100 . The fixed charge layer 300 may be formed of a metal oxide such as aluminum oxide and/or hafnium oxide.

A flat dielectric layer 310 may be formed on the fixed charge layer 300 . The formation of the planarizing dielectric layer 310 may include sequentially depositing a first planarizing layer 311 , a second planarizing layer 313 and a third planarizing layer 315 . The first flattening layer 311, the second flattening layer 313, and the third flattening layer 315 may be formed of a transparent dielectric material, and may have different thicknesses from each other. The first planarization layer 311, the second planarization layer 313 and the third planarization layer 315 may include, for example, metal oxide or silicon oxide.

The light shielding layer 321 and the low refractive index layer 323 may be sequentially formed on the flat dielectric layer 310 . The light shielding layer 321 may be formed of a metal material such as titanium, tungsten, or aluminum. As discussed above, the low refractive index layer 323 may be formed of a material having a refractive index in the range of about 1.1 to about 1.3. The low refractive index layer 323 may include organic materials and oxides. The refractive index of the low refractive index layer 323 may depend on the concentration of the oxide contained in the low refractive index layer 323 . The formation of the low refractive index layer 323 may include: spin-coating a composition including an organic material and a solvent on the light shielding layer 321; and performing a soft bake process or a dry process to remove the solvent.

Referring to FIGS. 4A and 16E , the low refractive index layer 323 and the light shielding layer 321 may be patterned to form a mesh structure 320 including the low refractive index pattern 324 and the light shielding pattern 322 . When viewed in plane, as discussed above, the grid structure 320 may overlap the pixel separation structures 103 in the semiconductor substrate 100 .

The formation of the mesh structure 320 may include forming a mask pattern (not shown) on the low refractive index layer 323, using the mask pattern as an etching mask through which the low refractive index layer 323 and the light shielding layer 321 are sequentially etched to The planar dielectric layer 310 is exposed. After the grid structure 320 is formed, the mask pattern may be removed.

The grid structure 320 may include a first fence part FS1 disposed between the adjacent sub-pixel regions PG1/PG2, PR and PB and a second fence part FS2 disposed between the adjacent pixel regions P1, P2 and P3 . The first fence part FS1 and the second fence part FS2 may have substantially the same height. Also, the first fence portion FS1 and the second fence portion FS2 may have substantially the same width.

After that, a protective layer 330 may be formed to conformally cover the surface of the mesh structure 320 and the top surface of the flat dielectric layer 310 exposed by the mesh structure 320 . The protective layer 330 may be formed by performing a chemical vapor deposition process or an atomic layer deposition process. The protective layer 330 may be formed of a single layer or multiple layers including one or more of an aluminum oxide layer and a silicon oxycarbide layer.

Referring to FIGS. 4A and 16F, initial color filters 340a and 340b may be sequentially formed on corresponding pixel regions (see P1, P2, and P3 of FIG. 3). For example, the first preliminary color filter 340a may be formed on the first pixel area P1, and the second preliminary color filter 340b may be formed on the second pixel area P2. Also, a third preliminary color filter (not shown) may be formed on the third pixel region P3.

Each of the preliminary color filters 340a and 340b may be formed by performing a spin coating process and a patterning process several times. The initial color filters 340a and 340b may fill the empty spaces defined by the grid structure 320 . For example, the preliminary color filters 340a and 340b may be formed through a coating process, a soft bake process, an exposure process, and a development process sequentially performed on a photoresist composition including a dye or pigment.

In some example embodiments, each of the initial color filters 340a and 340b may be commonly provided for the sub-pixel regions PG1/PG2, PR, and PB of the pixel regions P1, P2, and P3. For example, when each of the preliminary color filters 340 a and 340 b is formed, a coating process may be performed so that each of the preliminary color filters 340 a and 340 b may cover the first fence portion FS1 of the mesh structure 320 . Each of the initial color filters 340a and 340b may have a relatively large thickness at a portion adjacent to the first fence portion FS1 and a relatively small thickness at a portion adjacent to the second fence portion FS2 . As such, each of the primary color filters 340a and 340b may have an upwardly convex top surface. Also, the preliminary color filters 340a and 340b may be formed independently of each other, so that the preliminary color filters 340a and 340b may have different thicknesses from each other.

Referring to FIGS. 4A and 16G , a sacrificial planarization layer 355 may be formed to cover the top surfaces of the initial color filters 340a and 340b. The sacrificial planarization layer 355 may be formed of a material having an etch selectivity of approximately 1:1 relative to the initial color filters 340a and 340b in an etch process using the same etch recipe for the initial color filters 340a and 340b. The sacrificial planarization layer 355 may be formed of a transparent dielectric material. The sacrificial planarization layer 355 may be formed of, for example, SOG (spin on glass), FSG (fluoride silicate glass), FOX (flowable oxide), or TOSZ (tonen silazene). The sacrificial planarization layer 355 may be formed by spin coating a flowable material. The sacrificial flat layer 355 may cover the uneven top surfaces of the initial color filters 340a and 340b, but may have substantially flat top surfaces. For example, the sacrificial planarization layer 355 may have different thicknesses on the first barrier portion FS1 and the second barrier portion FS2. That is, for example, as shown in FIG. 16G , the thickness of the sacrificial planarization layer 355 on the second barrier portion FS2 may be greater than that on the first barrier portion FS1 .

4A and 16H, after the sacrificial planarization layer 355 is formed, a planarization process may be performed on the sacrificial planarization layer 355 and the initial color filters 340a and 340b. Accordingly, a first color filter 345a, a second color filter 345b, and a third color filter (not shown) may be formed to correspond to the first pixel area P1, the second pixel area P2, and the third pixel area P3. For example, the planarization process may include an etch back process or a chemical mechanical polishing process.

When the planarization process is performed, the protective layer 330 covering the top surface of the mesh structure 320 may serve as an etch stop layer or a planarization stop layer. For example, the planarization process may continue until the protective layer 330 covering the top surface of the grid structure 320 is exposed. After the planarization process, the first barrier portion FS1 of the grid structure 320 may separate the first initial color filter 340a into four first color filters 345a. This separation can be applied equally to the second initial color filter 340b.

When the planarization process is performed, the sacrificial planarization layer 355 may be etched with an etch selectivity of about 1:1 with respect to the initial color filters 340a and 340b. Accordingly, each of the first color filter 345a, the second color filter 345b, and the third color filter may have substantially the same thickness on the first and second barrier portions FS2 and FS2. For example, each of the first color filter 345a, the second color filter 345b, and the third color filter may have a substantially flat top surface. Also, after the planarization process, the top surfaces of the first color filter 345a, the second color filter 345b, and the third color filter may be positioned at a lower level than that of the top surface of the mesh structure 320, or positioned At substantially the same level as the level of the top surface of the grid structure 320 .

Thereafter, as shown in FIGS. 4A and 4B , a microlens array 350 may be formed to include microlenses 353 corresponding to the sub-pixel regions PG1/PG2, PR, and PB.

The microlens array 350 may be formed by: forming a light-transmitting photoresist layer; partially patterning the photoresist layer to form photoresists corresponding to the sub-pixel regions PG1/PG2, PR, and PB pattern; and reflowing the photoresist pattern. Therefore, the microlenses 353 can be formed in an upwardly convex shape with a constant curvature. In addition, the flat portion 351 may be formed to have a uniform thickness between the microlenses 353 and the first, second and third color filters 345a, 345b, and 345b.

Because the microlens array 350 is formed by coating a light-transmitting photoresist layer on the first color filter 345a, the second color filter 345b, and the third color filter having flat top surfaces, the microlens array 350 The microlens array 350 may have a substantially uniform thickness at the maximum thickness. The microlenses 353 may have substantially constant curvature on the top surfaces of the color filters 345a and 345b. In this case, the thickness distribution of the microlens array 350 can be improved.

Afterwards, a passivation layer 360 may be formed to conformally cover the surface of the microlenses 353 . The passivation layer 360 may be formed of, for example, an inorganic oxide.

17A-17D illustrate cross-sectional views taken along line II' of FIG. 4A showing a method of fabricating an image sensor according to some example embodiments.

Referring to FIG. 17A, after the planarization process of the second surface 100b of the semiconductor substrate 100 as discussed above in FIG. 16D, a fixed charge layer 300 may be formed on the second surface 100b. A flat dielectric layer 310 may be formed on the fixed charge layer 300 . In this case, the formation of the flat dielectric layer 310 may include sequentially depositing the first flat layer 311 and the second flat layer 313 . The first flattening layer 311 and the second flattening layer 313 may be formed of transparent dielectric materials, and may have different thicknesses and different refractive indices. The first planarization layer 311 may include a hafnium oxide layer, a tantalum oxide layer or a titanium oxide layer. The second planarization layer 313 may include a silicon oxide layer such as TEOS.

After that, sacrificial patterns MP may be formed on the flat dielectric layer 310 . The sacrificial pattern MP may have a thickness greater than that of the flat dielectric layer 310 . The formation of the sacrificial pattern MP may include: coating a sacrificial layer on the flat dielectric layer 310; forming a photoresist pattern on the sacrificial layer; and etching the sacrificial layer using the photoresist pattern as an etch mask. The sacrificial patterns MP may define grid-shaped initial recesses RR1 on the flat dielectric layer 310 . The initial recess RR1 may expose the planar dielectric layer 310 . The sacrificial pattern MP may contain carbon in an amount equal to or greater than about 70 wt %. For example, the sacrificial pattern MP may include a spin-on hard mask (SOH) layer.

Referring to FIG. 17B , the flat dielectric layer 310 may be patterned using the sacrificial pattern MP as an etch mask. Accordingly, the flat dielectric layer 310 may have recesses RR2 therein formed to expose the fixed charge layer 300 . Optionally, in some example embodiments, the fixed charge layer 300 may be etched when the recess RR2 is formed, so the recess RR2 may expose the pixel separation structure 103 .

After forming the recess RR2, a low refractive index layer 323 may be formed to fill the recess RR2. The low refractive index layer 323 may be formed by performing a spin coating process. Therefore, the low refractive index layer 323 may completely fill the recess RR2 and may cover the top surface of the sacrificial pattern MP.

Thereafter, a planarization process may be performed with respect to the low refractive index layer 323 until the top surfaces of the sacrificial patterns MP are exposed.

The sacrificial pattern MP may be selectively removed to expose the top surface of the planar dielectric layer 310 for each of the sub-pixel regions PG1/PG2, PR, and PB. For example, the sacrificial patterns MP may be removed through an ashing process using oxygen.

Referring to FIG. 17C , after the sacrificial patterns MP are selectively removed, a protective layer 330 may be conformally formed. For example, the protective layer 330 may have a uniform thickness, and the protective layer 330 covers the top surface of the flat dielectric layer 310 and the sidewalls and the top surface of the mesh structure 320 . The removal of the sacrificial pattern MP and the formation of the protective layer 330 may form openings defined by the sidewalls of the mesh structure 320 and the top surface of the flat dielectric layer 310 . As a result, as shown in FIG. 17C, a mesh structure 320 including a low refractive index pattern may be formed.

17D , a first preliminary color filter 340a, a second preliminary color filter 340b, and a third preliminary color filter may be formed to correspond to the first pixel area P1, the second pixel area P2, and the third pixel area P3.

Because the coating process is performed to form each of the first preliminary color filter 340a, the second preliminary color filter 340b, and the third preliminary color filter as discussed with reference to FIG. 16F, the first preliminary color filter 340a, the first preliminary color filter 340a, the third preliminary color filter Each of the second initial color filter 340b and the third initial color filter may cover the first fence portion FS1 of the grid structure 320 . As such, each of the first preliminary color filter 340a, the second preliminary color filter 340b, and the third preliminary color filter may have an upwardly convex top surface.

Afterwards, as discussed with reference to FIG. 16G, a sacrificial planarization layer 355 may be formed to cover the top surfaces of the first preliminary color filter 340a, the second preliminary color filter 340b, and the third preliminary color filter. The sacrificial flat layer 355 may cover the uneven top surfaces of the initial color filters 340a and 340b, but may have substantially flat top surfaces.

Afterwards, as discussed above, a planarization process may be performed on the sacrificial planarization layer 355 and on the first preliminary color filter 340a, the second preliminary color filter 340b, and the third preliminary color filter. Accordingly, the first color filter 345a, the second color filter 345b, and the third color filter may be formed to correspond to the first pixel area P1, the second pixel area P2, and the third pixel area P3. The color filters 345a and 345b may have substantially flat top surfaces.

According to some example embodiments, each pixel region of the image sensor may include a color filter whose top surface is flat and whose thickness at its opposing sidewalls is substantially the same. Therefore, the image sensor can improve its sensitivity degradation caused by the uneven thickness of the color filter filling the empty space defined by the mesh structure.

In addition, the color filter may be provided with microlenses having a uniform radius of curvature. Therefore, crosstalk between pixel regions of the image sensor can be minimized. As a result, the sensitivity characteristics and signal-to-noise ratio characteristics of the image sensor can be improved.

Although the inventive concept has been described in conjunction with some example embodiments shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications and changes can be made hereto without departing from the scope and spirit of the claims.

Claims (20)

1. An image sensor comprising: a substrate comprising a pixel separation structure defining a plurality of pixel regions and a plurality of sub-pixel regions for each of the plurality of pixel regions; a grid structure, disposed on the substrate, and comprising a first fence portion disposed between sub-pixel regions and a second fence portion disposed between adjacent pixel regions, the mesh structure defining the plurality of sub-pixels respectively a plurality of openings corresponding to the regions; and A plurality of color filters are disposed in the openings defined by the grid structure, each color filter having a flat top surface, the flat top surface of each color filter being parallel to the bottom surface of each color filter. 2. The image sensor of claim 1, wherein the color filter has a first height adjacent to the first barrier portion and a second height adjacent to the second barrier portion, and a distance between the first height and the second height is The difference is

to

3. The image sensor of claim 1, wherein the grid structure includes a protective layer covering a top surface of the grid structure, and the flat top surface of the color filter is coplanar with the top surface of the protective layer. 4. The image sensor of claim 1, wherein a top surface of the color filter is lower than a top surface of the grid structure. 5. The image sensor of claim 1, wherein the mesh structure includes a protection pattern covering only sidewalls of the mesh structure and a bottom surface of the color filter, and The top surface of the color filter is lower than the top surface of the mesh structure. 6. The image sensor of claim 1, further comprising a fixed charge layer and a flat dielectric layer sequentially stacked between the substrate and the grid structure, Wherein, the grid structure includes a light shielding pattern arranged on the flat dielectric layer and a low refractive index pattern arranged on the light shielding pattern. 7. The image sensor of claim 6, wherein the height of the low refractive index pattern is

to

The thickness of each color filter is

to

8 . The image sensor according to claim 1 , further comprising a microlens array provided on the color filter, the microlens array comprising a flat portion provided on the color filter and an AND sub-array on the flat portion. 9 . A plurality of microlenses corresponding to the pixel area. 9. The image sensor of claim 1, wherein a height of the grid structure is smaller than a thickness of each color filter. 10. The image sensor of claim 1, wherein the substrate includes a pixel array region and a pad region surrounding the pixel array region, the pixel array region including the plurality of pixel regions, The pixel array area includes a center area and an edge area surrounding the center area, In plan view, the grid structure overlaps the pixel separation structure in the central area, and The plurality of color filters have a thickness smaller in the edge region than in the central region. 11. An image sensor comprising: a substrate having a first surface and a second surface opposite to the first surface, the substrate including a pixel separation structure defining a plurality of pixel regions; a device isolation layer disposed adjacent to the first surface of the substrate on each of the plurality of pixel regions, the device isolation layer defining an active region in the plurality of pixel regions; a plurality of interlayer dielectric layers stacked on the first surface of the substrate and including contact plugs and connection lines; a fixed charge layer disposed on the second surface of the substrate; a flat dielectric layer arranged on the fixed charge layer; a grid structure disposed on the flat dielectric layer to overlap the pixel separation structure in plan view, the grid structure including fence portions disposed between adjacent pixel regions, the grid structure defining the plurality of pixels respectively Multiple openings corresponding to the area; a plurality of color filters disposed in the openings defined by the grid structure; a sacrificial planarization layer between adjacent ones of the plurality of color filters, the sacrificial planarization layer having a top surface coplanar with an uppermost surface of each color filter; and A microlens array is provided on the plurality of color filters. 12. The image sensor of claim 11, wherein the sacrificial planar layer fills the space above each barrier portion such that a top surface of the sacrificial planar layer is coplanar with an uppermost surface of each color filter. 13. The image sensor of claim 11, wherein the pixel separation structure defines a plurality of sub-pixel regions for each of the plurality of pixel regions, The fence portion is a second fence portion, and the grid structure further includes a first fence portion disposed between the sub-pixel regions, and Each color filter has a first height at a portion adjacent to the first fence portion that is greater than a second height at a portion adjacent to the second fence portion. 14. The image sensor of claim 13, wherein the microlens array includes a flat portion disposed on the color filter and a plurality of microlenses corresponding to the sub-pixel regions on the flat portion. 15 . The image sensor of claim 11 , wherein the plurality of pixel regions form a 2×2 matrix, and the sacrificial flat layer fills spaces between the pixel regions. 16 . 16. The image sensor of claim 11, wherein the grid structure includes a protective layer covering a top surface of the grid structure, and an uppermost surface of each color filter is coplanar with the top surface of the protective layer. 17. The image sensor of claim 11, wherein the mesh structure includes a light shielding pattern disposed on the flat dielectric layer and a low refractive index pattern disposed on the light shielding pattern. 18. The image sensor of claim 17, wherein the height of the low refractive index pattern is

to

The thickness of each color filter is

to

19. The image sensor of claim 11, wherein a height of the grid structure is smaller than a maximum thickness of each color filter. 20. The image sensor of claim 11, wherein the substrate includes a pixel array region and a pad region surrounding the pixel array region, the pixel array region including the plurality of pixel regions, The pixel array area includes a center area and an edge area surrounding the center area, In plan view, the grid structure overlaps the pixel separation structure in the central area, and The maximum thickness of each color filter in the edge region is smaller than the maximum thickness of the thicknesses of each color filter in the central region.

Images