CN112134809A

CN112134809A - Flow control method, device, equipment and readable storage medium

Info

Publication number: CN112134809A
Application number: CN202010975195.7A
Authority: CN
Inventors: 葛海亮; 李仁刚; 阚宏伟; 刘钧锴
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2020-09-16
Filing date: 2020-09-16
Publication date: 2020-12-25
Anticipated expiration: 2040-09-16
Also published as: CN112134809B

Abstract

The invention discloses a flow control method, a flow control device, flow control equipment and a readable storage medium, wherein the method comprises the following steps: the FPGA card sends data to an opposite-end FPGA card; receiving a flow regulation data packet sent by an opposite-end FPGA card; analyzing the flow regulation data packet to obtain speed regulation and control information; and regulating the data sending speed by using the speed regulation and control information. In the method, under the condition of not needing equipment such as a gateway and the like, the data sending speed can be adjusted according to the flow regulation and control packet sent by the FPGA card at the opposite end. In addition, compared with the existing flow control mechanism which only can realize stop-equation flow control, the method can adjust the data transmission speed and can meet the requirements of more actual flow control conditions.

Description

Flow control method, device, equipment and readable storage medium

Technical Field

The present invention relates to the field of computer application technologies, and in particular, to a flow control method, apparatus, device, and readable storage medium.

Background

FPGA (Field Programmable Gate Array) accelerator cards are widely applied to data centers. The FPGA accelerator card generally has a standard MAC (Media Access Control, ethernet) network port, and in practical engineering, a large number of situations exist in which two FPGA accelerator cards are interconnected through the MAC network port. How to control the network flow between the FPGA accelerator cards becomes an increasingly critical engineering practical problem.

Under the full-duplex MAC control framework, the flow control mechanism is a simple stop-and-go flow control mechanism implemented by PAUSE (ethernet frame format compliant with IEEE802.3 protocol) functionality. This flow control mechanism only enables simple stop-and-wait flow operations. In other schemes, a device such as a gateway is involved to realize flow control.

In summary, how to effectively solve the problems of flow control between FPGA cards and the like is a technical problem that needs to be solved urgently by those skilled in the art at present.

Disclosure of Invention

The invention aims to provide a flow control method, a flow control device, flow control equipment and a readable storage medium, so as to realize more accurate flow control among FPGA cards.

In order to solve the technical problems, the invention provides the following technical scheme:

a method of flow control, comprising:

the FPGA card sends data to an opposite-end FPGA card;

receiving the flow regulation and control data packet sent by the opposite-end FPGA card;

analyzing the flow regulation data packet to obtain speed regulation and control information;

and regulating the data sending speed by utilizing the speed regulation and control information.

Preferably, analyzing the flow regulation data packet to obtain speed regulation information includes:

analyzing the frame corresponding to the flow regulation data packet to obtain data content corresponding to the data and the filling field;

and extracting the speed regulation and control information from the data content.

Preferably, the extracting the speed regulation information from the data content includes:

and extracting at least one speed regulation and control information from the data content, wherein the speed regulation and control information is selected from control stage information, regulation and control duration information and reference speed information.

Preferably, analyzing the frame corresponding to the traffic regulation packet to obtain data content corresponding to the data and the padding field, including:

reading values from the data and the filling fields in sequence according to the corresponding specified byte length;

and analyzing the numerical value according to byte definition to obtain the data content.

Preferably, if the speed regulation information includes the regulation duration information and the reference speed information, correspondingly, the adjusting the data transmission speed by using the speed regulation information includes:

in a time period corresponding to the regulation and control duration information, data is sent according to a data sending speed corresponding to the reference speed information;

or, in the time period corresponding to the regulation and control duration information, smoothly transitioning the data sending speed from the current data sending speed to the time period corresponding to the reference speed information.

Preferably, the method further comprises the following steps:

receiving data sent by the opposite-end FPAG card, and acquiring the data receiving speed;

determining whether the data sending speed needs to be adjusted or not by using the data receiving speed;

and if so, sending the flow regulation and control data packet to the opposite-end FPGA card.

Preferably, the determining whether the data transmission speed needs to be adjusted by using the data receiving speed includes:

determining a target regulation and control stage corresponding to the data receiving speed from corresponding regulation and control stages according to each regulation and control range;

if the target regulation and control stage corresponds to the regulation and control required, determining that the data sending speed is required to be regulated;

and if the target regulation and control stage is not required to be regulated and controlled correspondingly, determining that the data sending speed is not required to be regulated.

A flow control device comprising:

the data sending module is used for sending data to the opposite terminal FPGA card by the FPGA card;

the flow regulation and control data packet receiving module is used for receiving the flow regulation and control data packet sent by the opposite-end FPGA card;

the speed regulation and control information acquisition module is used for analyzing the flow regulation data packet to obtain speed regulation and control information;

and the speed regulation and control module is used for regulating the data sending speed by utilizing the speed regulation and control information.

A flow control device comprising:

a memory for storing a computer program;

and the processor is used for realizing the steps of the flow control method when executing the computer program.

A readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the above-described flow control method.

By applying the method provided by the embodiment of the invention, the FPGA card sends data to the opposite-end FPGA card; receiving a flow regulation data packet sent by an opposite-end FPGA card; analyzing the flow regulation data packet to obtain speed regulation and control information; and regulating the data sending speed by using the speed regulation and control information.

In the method, under the condition that the FPGA card sends data to the opposite-end FPGA card, if a flow regulation and control data packet sent by the opposite-end FPGA card is received, the speed regulation and control information can be obtained by analyzing the flow regulation and control data packet. And then adjusting the data transmission speed based on the speed regulation information. That is, in the method, the data sending speed can be adjusted according to the flow regulation packet sent by the opposite-end FPGA card without the need of a gateway or other devices. In addition, compared with the existing flow control mechanism which only can realize stop-equality, the method can adjust the data transmission speed and can meet the requirements of more actual flow control conditions.

Accordingly, embodiments of the present invention further provide a flow control device, a device, and a readable storage medium corresponding to the flow control method, which have the above technical effects and are not described herein again.

Drawings

In order to more clearly illustrate the embodiments of the present invention or technical solutions in related arts, the drawings used in the description of the embodiments or related arts will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a flowchart illustrating an implementation of a flow control method according to an embodiment of the present invention;

fig. 2 is an application system corresponding to a flow control method in an embodiment of the present invention;

FIG. 3 is a flow chart illustrating another method for flow control according to an embodiment of the present invention;

fig. 4 is a flowchart illustrating an embodiment of a flow control method according to the present invention;

FIG. 5 is a schematic structural diagram of a flow control device according to an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a flow control device according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a flow control device according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a flowchart illustrating a flow control method according to an embodiment of the present invention, the method including the following steps:

s101, the FPGA card sends data to the opposite-end FPGA card.

The FPGA card and the opposite-end FPGA card correspond to a source end and a terminal of data transmission. The model numbers of the FPGA card and the opposite end FPGA card can be the same or different.

When the FPGA card sends data to the opposite-end FPGA card, the opposite-end FPGA card can determine whether the data sending speed needs to be adjusted according to the actual processing condition, and can send a flow regulation and control data packet to the FPGA card if the data sending speed needs to be adjusted.

It should be further noted that, in the embodiment of the present invention, the FPGA card and the opposite-end FPGA card are only relative, and the FPGA card may also receive data sent by the opposite-end FPGA card. Namely, the data transmission between the FPGA card and the opposite-end FPGA card can be carried out in a simplex mode, a half-duplex mode or a full-duplex mode.

S102, receiving a flow regulation and control data packet sent by the opposite-end FPGA card.

The flow regulation and control data packet, namely the opposite-end FPGA card, determines that flow regulation and control are needed and then sends the regulation and control data packet. The regulatory data packet may carry specific information about speed regulation.

And S103, analyzing the flow regulation data packet to obtain speed regulation and control information.

The traffic data packet can be analyzed according to the transmission protocol corresponding to the traffic regulation data packet to obtain speed regulation information. Specifically, the data frame corresponding to the traffic data packet is interpreted according to the specific frame format definition, so as to obtain the speed regulation information carried by the traffic regulation data packet.

The speed regulation information is regulation information for regulating the data transmission speed with reference. The speed regulation information may specifically be a speed parameter, such as specifically including one or more of a specific reference speed for regulating the data transmission speed, a duration of speed regulation, and a speed regulation direction (such as acceleration or deceleration); the speed regulation information may specifically be a tag that may also be a regulation stage (for example, a specific mode that corresponds to the regulation data sending speed in the regulation stage is predefined).

In an embodiment of the present invention, the step S103 may specifically include:

step one, analyzing a frame corresponding to the flow regulation data packet to obtain data content corresponding to the data and the filling field.

The frame format of the flow control data packet can adopt an IEEE802.3 Ethernet frame format. Referring to table 1, Data frames for regulating network traffic are predefined on the basis and located in Data and Pad (Data and Pad) fields.

TABLE 1 flow control packet frame format

Preamble

SFD

dst MAC

src MAC

Length

Type

IP head

UDP head

Data and Pad

FCS

Wherein, Preamble: a lead code, 7 bytes, used for synchronizing the sending and receiving rates of both parties in the data transmission process;

SFD: frame start, 1 byte, indicating that the next byte starts with real data (destination MAC address);

dst MAC: destination MAC address, 6 bytes, indicating the recipient of the frame;

src MAC: source MAC address, 6 bytes, indicating the sender of the frame;

length: length, 2 bytes, indicating the length of the frame data field;

type: type, 2 bytes, indicating the protocol type of the data in the frame;

IP head: IP, datagram header;

UDP head: a UDP datagram frame header;

data and Pad: self-defined flow control data format;

FCS: and checking a sequence by using the frame.

Specifically, the traffic adjustment data packet is analyzed according to a frame format corresponding to the traffic adjustment data packet, so as to obtain data content corresponding to the data and the filling field.

Specifically, the implementation process of reading and obtaining the data content includes:

step 1, reading values from data and filling fields in sequence according to corresponding specified byte lengths;

and 2, analyzing the numerical value according to the byte definition to obtain the data content.

For convenience of description, please refer to fig. 2, which illustrates the above 2 steps in combination.

In fig. 2, a TX side flow monitoring module is used for monitoring the data flow rate of the MAC TX. And the RX side flow monitoring and TX control module is used for monitoring the receiving data flow speed of the MAC RX and controlling the data flow sending speed of the MAC TX. And the opposite-end module flow adjustment indicating module is used for adjusting and controlling the MAC TX flow sending of the opposite side by sending a flow adjustment data packet to the opposite side through the MAC TX. The MAC TX and the MAC RX are an MAC sending end and an MAC receiving end in the FPGA. The FPGA a card may be an opposite-end FPGA card, and certainly, the FPGA B card may also be an opposite-end FPGA card.

Data and Pad is the custom Data frame for flow control in this embodiment. Please refer to table 2 for the specific format.

TABLE 2 Data and Pad definitions

ctrl_flag

ctrl_action

ctrl_rate

ctrl_time

ctrl_stop

ctrl_warning

other_data

Wherein ctrl _ flag: 4 bytes, including but not limited to a feature code word, such as 0x8808_593d, to indicate that the packet is for the FPGA to regulate network traffic.

ctrl _ action: 2bit, wherein the value 1 represents that the current MAC RX flow (data receiving speed) of the card (namely FPGA card) is close to the threshold value in the early warning stage of the network flow of the opposite side; the value 2 represents that the network flow of the opposite side needs to be regulated and controlled, and represents that the current MAC RX side flow (data transmission speed) of the FPGA card just exceeds a threshold value; the value 3 represents the stage of needing the opposite network flow to stop, and represents that the current MAC RX side flow of the card seriously exceeds the threshold value. A value of 0 indicates that the partner is not required to react.

ctrl _ rate: and 2 bytes, which indicates that when ctrl _ action is 1 or 2, the opposite party is instructed to adjust the network traffic on its MAC TX side to the corresponding reference speed.

ctrl _ time: 2 bytes, the duration of the current flow regulation, and a value of 0 indicates that the current flow regulation is finished.

ctrl _ stop: 1bit, which is invalid for 0, and 1 represents that the MAC TX end of the opposite side needs to stop transmitting packets.

ctrl _ warning: when ctrl _ action is 1 or 2, 2bit indicates that the transmission rate of the MAC TX end of the counterpart needs to be decreased, and 2 indicates that the transmission rate of the MAC TX end of the counterpart needs to be increased. The value 0 indicates a default value, invalid.

other _ data: other message data.

I.e., Data content, meaning the content corresponding to the value read in the Data and Pad field.

And step two, extracting speed regulation and control information from the data content.

The speed regulation information can be obtained according to the data content. For example, if ctrl _ stop is 1, it is determined that the speed control information includes stop data transmission.

Wherein, the second step can specifically comprise: and extracting at least one speed regulation and control information from the control stage information, the regulation and control duration information and the reference speed information from the data content.

That is, at least one of the control phase information, the control duration information, and the parameter speed information may be extracted as information that can be used to adjust the data transmission speed.

And S104, adjusting the data sending speed by using the speed regulation and control information.

After the speed regulation information is obtained, the data transmission speed can be regulated based on the depth regulation information. Specifically, if the speed regulation information includes a specific speed parameter, the data sending speed can be directly regulated to be matched with the speed parameter; and if the speed regulation information is the label of the regulation and control stage, regulating the data sending speed according to the specific mode of the corresponding regulation and control stage.

In a specific embodiment of the present invention, if the speed regulation information includes the regulation duration information and the reference speed information, step S104 may include the following two cases:

and in the condition 1, data is sent according to the data sending speed corresponding to the reference speed information in the time period corresponding to the regulation and control duration information.

That is, a time period in which the adjusted speed matches the reference speed information and the duration corresponds to the control duration information is defined.

For example, if the current data transmission speed is V1 and the reference speed corresponding to the reference data information is V2, the data transmission speed is directly adjusted from V1 to V2 and is continuously maintained at V2 for the time period T corresponding to the control duration information.

And 2, smoothly transitioning the data sending speed from the current data sending speed to correspond to the reference speed information in the time period corresponding to the regulation and control duration information.

That is, it is limited that the adjusted speed matches the reference speed information, and the adjustment of the data transmission speed takes a time period corresponding to the control duration information.

For example, if the current data transmission speed is V1 and the reference speed corresponding to the reference data information is V2, the data transmission speed is adjusted from V1 to V2 within the time period T corresponding to the control duration information.

It should be noted that, according to actual requirements, the adjustment mode corresponding to the case 1 or the case 2 may be selected for execution.

It should be noted that, based on the above embodiments, the embodiments of the present invention also provide corresponding improvements. In the preferred/improved embodiment, the same steps as those in the above embodiment or corresponding steps may be referred to each other, and corresponding advantageous effects may also be referred to each other, which are not described in detail in the preferred/improved embodiment herein.

In a specific embodiment of the present invention, on the basis of the above embodiment, the FPGA card may further send a flow rate regulation and control packet corresponding to the data sending speed regulation to the FPGA card at the opposite end. Of course, the specific implementation of sending the traffic control packet by the opposite-end FPGA card may also be referred to herein.

Referring to fig. 3, fig. 3 is a flowchart illustrating another flow control method according to an embodiment of the present invention, where the implementation process includes:

s201, receiving data sent by an opposite terminal FPAG card, and acquiring a data receiving speed.

That is, when receiving data sent by the FPGA card at the opposite end, the FPGA card can monitor the data receiving speed, thereby obtaining the data receiving speed.

S202, determining whether the data sending speed needs to be adjusted or not by using the data receiving speed.

After the data receiving speed is obtained, it may be determined whether the data transmitting speed needs to be adjusted based on the data receiving speed. The data sending speed here refers to the speed of sending data to the local card by the opposite-end FPGA card, but not the speed of sending data to the outside by the local card.

Specifically, the FPGA card may be configured to match the processing efficiency with the data receiving speed according to the current processing efficiency, and may not need to be adjusted if the processing efficiency is not matched with the data receiving speed (for example, the processing efficiency is too low, the received data cannot be effectively processed, or the processing efficiency is high, and more data may be processed).

Of course, the adjustment threshold may also be directly set, and the corresponding relationship between the data transmission speed and the adjustment threshold is determined, so as to determine whether adjustment is required. For example, an upper threshold and a lower threshold are set, and if the data receiving speed is greater than the upper threshold, it is determined that the data sending speed needs to be adjusted (such as speed reduction or sending stop); if the data receiving speed is less than the lower threshold, it is determined that the data transmitting speed needs to be adjusted (e.g., accelerated).

In a specific embodiment of the present invention, the determining process specifically includes:

step one, determining a target regulation and control stage corresponding to the data receiving speed from corresponding regulation and control stages according to each regulation and control range;

step two, if the target regulation and control stage corresponds to the regulation and control required, determining the sending speed of the data required to be regulated;

and step three, if the target regulation and control stage is not required to be correspondingly regulated and controlled, determining that the data sending speed is not required to be regulated.

For convenience of description, the above three steps will be described in combination.

Referring to table 3 of the drawings, please refer to,

table 3, MAC RX side speed X and regulation strategy description list

The MAC RX side flow rate has an upper limit threshold and a lower limit threshold, wherein the upper limit threshold represents the maximum speed, and the lower limit threshold represents the minimum speed.

That is, the regulation phase can be determined by the current data reception speed, and then it is clear whether data transmission speed regulation is currently to be performed.

If the judgment result is yes, executing the step of S203; if the judgment result is no, executing the operation without operation.

And S203, sending a flow regulation and control data packet to the opposite-end FPGA card.

Reference may be made to the above embodiments regarding the specific frame format of the traffic conditioning packet, and how the conditioning information is carried.

After receiving the flow rate adjustment data packet, the opposite-end FPGA may refer to the specific adjustment process of the data transmission speed described in the above embodiment to perform processing.

For easy understanding, please refer to fig. 4, and the flow control method will be described in detail below with reference to a specific application flow as an example.

Step 1, the FPGA board card (namely the PPGA card) is electrified and initialized, the numerical values in the upper limit threshold value register and the lower limit threshold value register are updated, and the step 2 is entered.

And 2, transmitting data by the MAC TX of the opposite-end FPGA card, receiving the data by the MAC RX of the FPGA card, and entering the step 3.

And 3, matching the MAC RX side data receiving speed of the FPGA card with that in the table 3, and entering the step 4.

And 4, judging whether the flow needs to be regulated or not, if not, skipping to the step 2, and if so, performing the step 5.

And 5, the FPGA card sends a flow regulation and control data packet to an opposite-end FPGA card through the MAC TX end.

Step 6, the MAC RX end of the opposite-end FPGA card receives and analyzes the data regulation and control data packet, timing is started, and the step 7 is entered;

and 7, the opposite side regulates and controls the data of the data packet according to the received data, adjusts the sending speed of the MAC TX end of the opposite side, the adjusting speed is gradually adjusted to the reference speed of ctrl _ rate from the current speed, the MAC TX of the opposite side sends data, the MAC RX of the FPGA card receives the data, and the step 8 is carried out.

And 8, comparing the time of the timer with ctrl _ time, and judging whether the timing is reached, if so, performing step 2, and if not, performing step 9.

And 9, adjusting whether the network flow speed is in accordance with the expectation, if so, entering the step 2, and if not, entering the step 7.

Therefore, the flow control method provided by the embodiment of the invention can realize the prevention of network congestion and the quantitative regulation and control of network flow among the FPGA board cards. The method has certain practical significance in meeting the actual engineering requirements.

Corresponding to the above method embodiment, the embodiment of the present invention further provides a flow control device, and the flow control device described below and the flow control method described above may be referred to in correspondence with each other.

Referring to fig. 5, the apparatus includes the following modules:

the data sending module 101 is used for sending data to the opposite terminal FPGA card by the FPGA card;

a flow control data packet receiving module 102, configured to receive a flow control data packet sent by an opposite-end FPGA card;

a speed regulation and control information acquisition module 103, configured to analyze the flow regulation packet to obtain speed regulation and control information;

and the speed regulation and control module 104 is used for regulating the data sending speed by using the speed regulation and control information.

By applying the device provided by the embodiment of the invention, the FPGA card sends data to the opposite-end FPGA card; receiving a flow regulation data packet sent by an opposite-end FPGA card; analyzing the flow regulation data packet to obtain speed regulation and control information; and regulating the data sending speed by using the speed regulation and control information.

In the device, under the condition that the FPGA card sends data to the opposite-end FPGA card, if a flow regulation and control data packet sent by the opposite-end FPGA card is received, the flow regulation and control data packet can be analyzed to obtain speed regulation and control information. And then adjusting the data transmission speed based on the speed regulation information. That is, in the present apparatus, the data transmission speed can be adjusted according to the traffic control packet sent by the opposite-end FPGA card without the need of a gateway or other devices. Compared with the existing flow control mechanism which only can realize stop-equality, the device can adjust the data transmission speed and can meet the requirements of more actual flow control conditions.

In a specific embodiment of the present invention, the speed regulation information obtaining module 103 is specifically configured to analyze a frame corresponding to the traffic regulation data packet to obtain data content corresponding to the data and the padding field; speed regulation information is extracted from the data content.

In an embodiment of the present invention, the speed regulation information obtaining module 103 is specifically configured to extract at least one of the control stage information, the regulation duration information, and the reference speed information from the data content.

In a specific embodiment of the present invention, the speed regulation information obtaining module 103 is specifically configured to read values from the data and the padding fields in sequence according to corresponding specified byte lengths; and analyzing the numerical value according to the definition of the byte to obtain the data content.

In a specific embodiment of the present invention, if the speed regulation information includes the regulation duration information and the reference speed information, correspondingly, the speed regulation module 104 is specifically configured to perform data transmission according to the data transmission speed corresponding to the reference speed information within the time period corresponding to the regulation duration information; or, in the time period corresponding to the regulation and control duration information, smoothly transitioning the data transmission speed from the current data transmission speed to the speed corresponding to the reference speed information.

In one embodiment of the present invention, the method further comprises:

the regulation and control initiation module is used for receiving data sent by the opposite terminal FPAG card and acquiring the data receiving speed; determining whether the data sending speed needs to be adjusted or not by using the data receiving speed; and if so, sending a flow regulation and control data packet to the FPGA card at the opposite end.

In a specific embodiment of the present invention, the regulation initiating module is specifically configured to determine, according to each regulation range, a target regulation stage corresponding to the data receiving speed from the corresponding regulation stages; if the target regulation and control stage corresponds to the regulation and control required, determining the data sending speed required to be regulated; and if the target regulation and control stage is not required to be correspondingly regulated and controlled, determining that the data sending speed is not required to be regulated.

Corresponding to the above method embodiment, an embodiment of the present invention further provides a flow control device, and a flow control device described below and a flow control method described above may be referred to in correspondence.

Referring to fig. 6, the flow control apparatus includes:

a memory 332 for storing a computer program;

the processor 322 is configured to implement the steps of the flow control method of the above-described method embodiment when executing the computer program.

Specifically, referring to fig. 7, fig. 7 is a schematic diagram of a specific structure of a flow control device provided in this embodiment, which may generate relatively large differences due to different configurations or performances, and may include one or more processors (CPUs) 322 (e.g., one or more processors) and a memory 332, where the memory 332 stores one or more computer applications 342 or data 344. Memory 332 may be, among other things, transient or persistent storage. The program stored in memory 332 may include one or more modules (not shown), each of which may include a sequence of instructions operating on a data processing device. Still further, the central processor 322 may be configured to communicate with the memory 332 to execute a series of instruction operations in the memory 332 on the flow control device 301.

The flow control device 301 may also include one or more power sources 326, one or more wired or wireless network interfaces 350, one or more input-output interfaces 358, and/or one or more operating systems 341.

The steps in the flow control method described above may be implemented by the structure of the flow control apparatus.

Corresponding to the above method embodiment, the embodiment of the present invention further provides a readable storage medium, and a readable storage medium described below and a flow control method described above may be referred to in correspondence.

A readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the flow control method of the above-mentioned method embodiment.

The readable storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and various other readable storage media capable of storing program codes.

Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

Claims

1. A method of flow control, comprising:

the FPGA card sends data to an opposite-end FPGA card;

2. The flow control method according to claim 1, wherein analyzing the flow adjustment packet to obtain speed adjustment information comprises:

3. The flow control method according to claim 2, wherein extracting the speed regulation information from the data content includes:

4. The flow control method according to claim 3, wherein parsing the frame corresponding to the flow adjustment packet to obtain data content corresponding to the data and the padding field comprises:

5. The flow control method according to claim 3, wherein if the speed regulation information includes the regulation duration information and the reference speed information, correspondingly, the adjusting the data transmission speed using the speed regulation information includes:

6. The flow control method according to any one of claims 1 to 5, characterized by further comprising:

7. The flow control method according to claim 6, wherein determining whether the data transmission speed needs to be adjusted using the data reception speed comprises:

8. A flow control device, comprising:

9. A flow control apparatus, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the flow control method according to any one of claims 1 to 7 when executing said computer program.

10. A readable storage medium, having stored thereon a computer program which, when executed by a processor, carries out the steps of the flow control method according to any one of claims 1 to 7.