CN112187257B - High-speed low-jitter data synchronous phase discriminator - Google Patents
High-speed low-jitter data synchronous phase discriminator Download PDFInfo
- Publication number
- CN112187257B CN112187257B CN202011112317.6A CN202011112317A CN112187257B CN 112187257 B CN112187257 B CN 112187257B CN 202011112317 A CN202011112317 A CN 202011112317A CN 112187257 B CN112187257 B CN 112187257B
- Authority
- CN
- China
- Prior art keywords
- data
- trigger
- circuit
- clock
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001360 synchronised effect Effects 0.000 title abstract description 12
- 238000012937 correction Methods 0.000 abstract description 19
- 230000000630 rising effect Effects 0.000 abstract description 6
- 102100038026 DNA fragmentation factor subunit alpha Human genes 0.000 description 11
- 102100038023 DNA fragmentation factor subunit beta Human genes 0.000 description 11
- 101100277639 Homo sapiens DFFB gene Proteins 0.000 description 11
- 101000950906 Homo sapiens DNA fragmentation factor subunit alpha Proteins 0.000 description 11
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 10
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 10
- 101001122448 Rattus norvegicus Nociceptin receptor Proteins 0.000 description 8
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 6
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 6
- 101100033865 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA1 gene Proteins 0.000 description 6
- 101100524516 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA2 gene Proteins 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 238000005070 sampling Methods 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 101100020619 Arabidopsis thaliana LATE gene Proteins 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a high-speed low-jitter data synchronous phase discriminator, which comprises a data latch circuit, a data clock comparison circuit, a data correction circuit and a decision circuit, wherein the data latch circuit is connected with the data clock comparison circuit; the data latch circuit is used for receiving a high-speed data stream input from the outside and latching the high-speed data stream when the rising edge of the next clock period arrives; the data clock comparison circuit compares the time sequence of the data stream with the input reference clock; the data correction circuit corrects the front-end latched data signal and the received clock signal to ensure that the front-end latched data signal and the received clock signal are aligned with each data and the input clock temporarily in the next clock; the decision circuit is used for determining the lead-lag relation between data and a clock; the invention has the advantages of small recovered clock jitter, large tuning range, low power consumption, simple structure and the like.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a high-speed low-jitter data synchronous phase discriminator.
Background
In the clock data recovery circuit, the phase detector is one of the most important units, and the structure of the phase detector can limit the error rate and jitter tolerance of the clock data recovery circuit, so that in order to reduce the error rate and improve the jitter tolerance of the clock data recovery circuit, the data receiving speed and accuracy of the phase detector need to be improved as much as possible, and clock and data jitter generated by the structure of the phase detector is reduced. Current phase detectors generally simply have two processes, namely data acquisition and clock comparison, and only take into account the inherent jitter factors present within the transmitted data during data acquisition. Meanwhile, the method has the defect of low synchronization precision of data and clocks. In order to reduce the error rate of the clock data recovery circuit and to increase its jitter tolerance, it is necessary to reduce the data synchronization time of the phase detector. At the same time, jitter is a very important indicator of the circuit, and a low jitter phase detector should be designed to reduce jitter between the input clock and data.
Disclosure of Invention
The invention aims at: in order to overcome the defects, the invention provides a high-speed low-jitter data synchronous phase discriminator.
In order to achieve the above purpose, the present invention provides the following technical solutions:
The high-speed low-jitter data synchronous phase discriminator comprises a data latch circuit, a data clock comparison circuit, a data correction circuit and a decision circuit; the data latch circuit is respectively connected with the data clock comparison circuit, the data correction circuit and the decision circuit, the data clock comparison circuit is connected with the data correction circuit, and the data correction circuit is connected with the decision circuit;
The data latch circuit includes: a buffer BUF1, a buffer BUF2, a buffer BUF3, a flip-flop DFF1, a flip-flop DFF2, a flip-flop DFF3, a DATA terminal, a CLK1 terminal, and a CLK2 terminal; the CLK2 end is respectively connected with the input end of the DATA correction circuit and the input end of the decision circuit, the Q ends of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3 are respectively connected with the input end of the DATA clock comparison circuit and the input end of the DATA correction circuit, the D ends of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3 are respectively correspondingly connected with the output ends of the buffer BUF1, the buffer BUF2 and the buffer BUF3, the CLK1 end is respectively connected with the clock input ends of the flip-flop DFF1 and the flip-flop DFF2, the CLK2 end is connected with the clock input end of the flip-flop DFF3, and the DATA end is respectively connected with the input ends of the buffer BUF1, the buffer BUF2 and the buffer BUF 3.
Removing burrs and minute jitter which may exist in input data through a buffer; and the input data is latched by utilizing a trigger according to the added quadrature input reference clock, so that a transient data latching task is completed.
Further, the data clock comparison circuit comprises a three-input AND gate AND; the output end of the three-input AND gate AND is connected with the input end of the data correction circuit; AND three input ends of the three-input AND gate AND are respectively AND correspondingly connected with Q ends of the trigger DFF1, the trigger DFF2 AND the trigger DFF 3.
The time sequence comparison AND unification of clocks of different data are realized by adopting a three-input AND gate AND.
Further, the data correction circuit comprises a decision register; the ENABLE input end REG_ENABLE of the decision register is connected with the output end of the DATA clock comparison circuit, the DATA output end DATA_In1, the DATA output end DATA_In2 and the DATA output end DATA_In3 of the decision register are respectively connected with the input end of the decision circuit, the clock input end of the decision register is connected with the DATA latch circuit, the DATA input end DATA1, the DATA input end DATA2 and the DATA input end DATA3 of the decision register are respectively correspondingly connected with the Q ends of the trigger DFF1, the trigger DFF2 and the trigger DFF3, and the clock output end of the decision register outputs RE_TIMING signals.
The data correction circuit corrects the front-end latched data signal and the received clock signal, and the data can be collected at the rising edge of the input clock, so that an optimal sampling interval is formed, clock jitter is reduced, and the accuracy of the recovered data is improved.
Further, the decision register is a first-in first-out memory with a data selection terminal; the continuous storage task of the data with larger bit width is realized by utilizing the judgment register, so that the clock jitter is reduced and the precision of the recovered data is improved.
Further, the decision circuit comprises a flip-flop DFF4, a flip-flop DFF5, a flip-flop DFF6, and exclusive or gates XOR1 and XOR2; the clock input ends of the trigger DFF4, the trigger DFF5 and the trigger DFF6 are connected with a data latch circuit, the D ends of the trigger DFF4, the trigger DFF5 and the trigger DFF6 are respectively and correspondingly connected with the output end of the data correction circuit, the Q end of the trigger DFF4 is connected with an exclusive OR gate XOR1, the Q end of the trigger DFF5 is respectively connected with the exclusive OR gate XOR1 and the exclusive OR gate XOR2, and the Q end of the trigger DFF6 is connected with the exclusive OR gate XOR2; the exclusive or gate XOR1 and the exclusive or gate XOR2 are used for outputting a lead signal EARLY or a lag signal LATE.
By latching the data into the flip-flop for discrimination, the phase error of the data and clock accumulated in the circuit is reduced to the minimum level, so that the timing sequence of the data is greatly improved.
The invention has the beneficial effects that: the high-speed low-jitter data synchronous phase discriminator has six data triggers, can simultaneously receive a group of quadrature clocks, controls the data flow rate by clock signals, has the advantages of small recovered clock jitter, large tuning range, low power consumption, simple structure and the like compared with the traditional phase discriminator, and can be widely applied to integrated circuit design.
Drawings
Fig. 1 is a general circuit diagram of a high-speed low-jitter data synchronous phase detector according to the present invention;
fig. 2 is a waveform diagram of data transmission of a high-speed low-jitter data synchronous phase discriminator according to the invention;
FIG. 3 is a schematic diagram of an optimal sampling point of a high-speed low-jitter data synchronous phase discriminator according to the invention;
Fig. 4 is a schematic diagram illustrating data timing adjustment of a high-speed low-jitter data synchronous phase detector according to the present invention.
Detailed Description
As shown in fig. 1, a high-speed low-jitter data synchronous phase discriminator comprises a data latch circuit, a data clock comparison circuit, a data correction circuit and a decision circuit; the data latch circuit is connected with the data clock comparison circuit, the data correction circuit and the decision circuit, the data clock comparison circuit is connected with the data correction circuit, and the data correction circuit is connected with the decision circuit.
The data latch circuit includes: a buffer BUF1, a buffer BUF2, a buffer BUF3, a flip-flop DFF1, a flip-flop DFF2, a flip-flop DFF3, a DATA terminal, a CLK1 terminal, and a CLK2 terminal; when one clock signal is high level in the CLK1 and the CLK2, the DATA end sends the DATA DATA into the buffer BUF1, the buffer BUF2 and the buffer BUF3, the buffer BUF1, the buffer BUF2 and the buffer BUF3 transfer the DATA DATA into the D end of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3 which are correspondingly connected, at the moment, two groups of orthogonal input reference clocks CLK1 and CLK2 are added into the CLK1 end and the CLK2 end, the DATA DATA is respectively locked in different flip-flops, and when the rising edge of the next clock arrives, the Q end of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3 correspondingly output the DATA DATA1, the DATA DATA2 and the DATA DATA3 to the input end of the DATA clock comparison circuit, so that the transient DATA latch task is completed.
Removing burrs and minute jitter which may exist in input data through a buffer; and the input data is latched by utilizing a trigger according to the added quadrature input reference clock, so that a transient data latching task is completed.
The data clock comparison circuit comprises a three-input AND gate AND; the DATA DATA1, DATA2 AND DATA3 correspondingly output by the Q terminals of the flip-flop DFF1, the flip-flop DFF2 AND the flip-flop DFF3 enter the three-input AND gate AND through the three input terminals of the three-input AND gate AND, when the output DATA1, DATA2, AND DATA3 all reach the output terminals of the three-input AND gate AND, the output terminals of the three-input AND gate AND output the reg_enable signal to the input terminal of the DATA correction circuit.
The time sequence comparison AND unification of clocks of different data are realized by adopting a three-input AND gate AND.
The data correction circuit comprises a judgment register; when the REG_ENABLE of the input enabling end REG_ENABLE of the judging register receives the REG_ENABLE signal output by the output end of the three-input AND gate AND, the Q end of the trigger DFF1, the Q end of the trigger DFF2 AND the Q end of the trigger DFF3 correspondingly output DATA DATA1, DATA DATA2 AND DATA DATA3 are all stored in the judging register; when the rising edge of the next clock of the input reference clock CLK2 arrives, the latched three paths of DATA are uniformly output to a decision circuit through a DATA output end DATA_In1, a DATA output end DATA_In2 and a DATA output end DATA_In3 of the decision register; the clock output of the decision register outputs a RE_TIMING signal. The decision register is a first-in first-out memory with a data selection end; the continuous storage task of the data with larger bit width is realized by utilizing the judgment register, so that the clock jitter is reduced and the precision of the recovered data is improved.
The data correction circuit corrects the front-end latched data signal and the received clock signal, and the data can be collected at the rising edge of the input clock, so that an optimal sampling interval is formed, clock jitter is reduced, and the accuracy of the recovered data is improved.
The decision circuit comprises a trigger DFF4, a trigger DFF5, a trigger DFF6, an exclusive OR gate XOR1 and an exclusive OR gate XOR2; the DATA DATA_In1, DATA_In2 and DATA_In3 outputted by the judging register flow into the D end of the corresponding trigger DFF4, the D end of the trigger DFF5 and the D end of the trigger DFF6 IN the judging circuit; when the rising edge of the next clock of the input reference clock CLK2 comes, three paths of DATA are uniformly latched into the flip-flop DFF4, the flip-flop DFF5 and the flip-flop DFF6, then after one clock period, the DATA DATA_In1 is latched by the flip-flop DFF4, the DATA DATA_OUT1 is output to the exclusive OR gate XOR1 through the Q end of the flip-flop DFF4, the DATA DATA_In2 is latched by the flip-flop DFF5, the DATA DATA_OUT2 is output to the exclusive OR gates XOR1 and XOR2 through the Q end of the flip-flop DFF5, and the DATA DATA_In3 is latched by the flip-flop DFF6, and the DATA DATA_OUT3 is output to the exclusive OR gate XOR2 through the Q end of the flip-flop DFF 6; the outputs of the exclusive or gates XOR1 and XOR2 are both the outputs of the decision circuit and also the outputs of the whole data sync phase detector. By judging the lead-lag relationship of the three groups of data after passing through the same input reference clock CLK2, a corresponding lead signal EARLY or lag signal LATE is generated.
The phase error of the data and the clock accumulated in the circuit is reduced to the minimum level through the decision circuit, so that the time sequence of the data is greatly improved.
The present invention has been described in terms of the preferred embodiments thereof, and it should be understood by those skilled in the art that various modifications can be made without departing from the principles of the invention, and such modifications should also be considered as being within the scope of the invention.
Claims (2)
1. The high-speed low-jitter data synchronous phase discriminator is characterized by comprising a data latch circuit, a data clock comparison circuit, a data correction circuit and a decision circuit; the data latch circuit is respectively connected with the data clock comparison circuit, the data correction circuit and the decision circuit, the data clock comparison circuit is connected with the data correction circuit, and the data correction circuit is connected with the decision circuit;
The data latch circuit includes: a buffer BUF1, a buffer BUF2, a buffer BUF3, a flip-flop DFF1, a flip-flop DFF2, a flip-flop DFF3, a DATA terminal, a CLK1 terminal, and a CLK2 terminal; the CLK2 end is respectively connected with the input end of the DATA correction circuit and the input end of the decision circuit, the Q ends of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3 are respectively connected with the input end of the DATA clock comparison circuit and the input end of the DATA correction circuit, the D ends of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3 are respectively correspondingly connected with the output ends of the buffer BUF1, the buffer BUF2 and the buffer BUF3, the CLK1 end is respectively connected with the clock input ends of the flip-flop DFF1 and the flip-flop DFF2, the CLK2 end is connected with the clock input end of the flip-flop DFF3, and the DATA end is respectively connected with the input ends of the buffer BUF1, the buffer BUF2 and the buffer BUF 3;
the data clock comparison circuit comprises a three-input AND gate AND; the output end of the three-input AND gate AND is connected with the input end of the data correction circuit, AND the three input ends of the three-input AND gate AND are correspondingly connected with the Q ends of the trigger DFF1, the trigger DFF2 AND the trigger DFF3 respectively;
The data correction circuit comprises a judgment register; the ENABLE input end REG_ENABLE of the decision register is connected with the output end of the DATA clock comparison circuit, the DATA output end DATA_In1, the DATA output end DATA_In2 and the DATA output end DATA_In3 of the decision register are respectively connected with the input end of the decision circuit, the clock input end of the decision register is connected with the DATA latch circuit, the DATA input end DATA1, the DATA input end DATA2 and the DATA input end DATA3 of the decision register are respectively correspondingly connected with the Q ends of the trigger DFF1, the trigger DFF2 and the trigger DFF3, and the clock output end of the decision register outputs RE_TIMING signals;
The decision circuit comprises a trigger DFF4, a trigger DFF5, a trigger DFF6, an exclusive OR gate XOR1 and an exclusive OR gate XOR2; the clock input ends of the trigger DFF4, the trigger DFF5 and the trigger DFF6 are connected with a data latch circuit, the D ends of the trigger DFF4, the trigger DFF5 and the trigger DFF6 are respectively and correspondingly connected with the output end of the data correction circuit, the Q end of the trigger DFF4 is connected with an exclusive OR gate XOR1, the Q end of the trigger DFF5 is respectively connected with the exclusive OR gate XOR1 and the exclusive OR gate XOR2, and the Q end of the trigger DFF6 is connected with the exclusive OR gate XOR2; the exclusive or gate XOR1 and the exclusive or gate XOR2 are used for outputting a lead signal EARLY or a lag signal LATE.
2. A high speed low jitter data sync phase detector according to claim 1 wherein said decision register is a first in first out memory with data select terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011112317.6A CN112187257B (en) | 2020-10-16 | 2020-10-16 | High-speed low-jitter data synchronous phase discriminator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011112317.6A CN112187257B (en) | 2020-10-16 | 2020-10-16 | High-speed low-jitter data synchronous phase discriminator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112187257A CN112187257A (en) | 2021-01-05 |
| CN112187257B true CN112187257B (en) | 2024-06-14 |
Family
ID=73950661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011112317.6A Active CN112187257B (en) | 2020-10-16 | 2020-10-16 | High-speed low-jitter data synchronous phase discriminator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112187257B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN213152037U (en) * | 2020-10-16 | 2021-05-07 | 广西师范大学 | A High-speed and Low-Jitter Data Synchronous Phase Detector |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5812776B2 (en) * | 1975-05-24 | 1983-03-10 | 日本電気株式会社 | Digital Shingounosokudhenkan Cairo |
| US5920600A (en) * | 1995-09-18 | 1999-07-06 | Oki Electric Industry Co., Ltd. | Bit phase synchronizing circuitry for controlling phase and frequency, and PLL circuit therefor |
| US5808691A (en) * | 1995-12-12 | 1998-09-15 | Cirrus Logic, Inc. | Digital carrier synthesis synchronized to a reference signal that is asynchronous with respect to a digital sampling clock |
| US6538475B1 (en) * | 2000-03-15 | 2003-03-25 | Intel Corporation | Phase detector |
| US7746134B1 (en) * | 2007-04-18 | 2010-06-29 | Altera Corporation | Digitally controlled delay-locked loops |
| CN101572527A (en) * | 2009-06-09 | 2009-11-04 | 中国人民解放军国防科学技术大学 | High-speed high-jitter-tolerance random-data linear phase detector circuit |
| CN108270436B (en) * | 2016-12-30 | 2021-06-08 | 中国科学院电子学研究所 | Control code latch circuit and clock data recovery circuit |
| CN107565956B (en) * | 2017-09-22 | 2020-06-30 | 哈尔滨工业大学 | VCO frequency band switching circuit and loop switching method applied in dual loop clock data recovery circuit |
| CN110649922B (en) * | 2019-10-26 | 2022-12-20 | 复旦大学 | A digital clock frequency multiplier |
-
2020
- 2020-10-16 CN CN202011112317.6A patent/CN112187257B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN213152037U (en) * | 2020-10-16 | 2021-05-07 | 广西师范大学 | A High-speed and Low-Jitter Data Synchronous Phase Detector |
Non-Patent Citations (1)
| Title |
|---|
| 一种10 Gb / s 超低抖动时钟数据恢复电路的设计;刘泽法;电子元件与材料;20201205;第12卷(第39期);89-100 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112187257A (en) | 2021-01-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8760325B2 (en) | Scheme for balancing skew between lanes of high-speed serial digital interface | |
| EP0679307B1 (en) | Delay line separator for data bus | |
| EP1620968B1 (en) | Multiphase clock recovery | |
| US7482841B1 (en) | Differential bang-bang phase detector (BBPD) with latency reduction | |
| CN112073058B (en) | Clock data recovery circuit and method based on FPGA | |
| CN102611447B (en) | A Noise-Added Signal Synchronous Clock Extraction Device Based on FPGA | |
| CN112152626B (en) | Analog-to-digital conversion acquisition circuit and chip | |
| CN103475362A (en) | Oversampling-based data recovery circuit without clock recovery | |
| CN106385251A (en) | Clock data recovery circuit | |
| JP2008066879A (en) | Oversampling circuit and oversampling method | |
| CN102946306B (en) | Clock data recovery circuit structure and digitlization clock and data recovery method | |
| CN107425848B (en) | Clock data recovery circuit and method | |
| CN213152037U (en) | A High-speed and Low-Jitter Data Synchronous Phase Detector | |
| CN115796094A (en) | A second-order serial majority voter circuit | |
| CN112764363A (en) | Multi-channel delay control circuit | |
| CN112187257B (en) | High-speed low-jitter data synchronous phase discriminator | |
| CN113037667B (en) | Data signal recovery method based on FPGA | |
| CN103812505B (en) | bit synchronization lock detector | |
| US7120838B2 (en) | Method and unit for deskewing signals | |
| US8054927B2 (en) | Synchronous circuit and method for receiving data | |
| CN202586998U (en) | Synchronous clock extraction device for noise-added signal based on FPGA (field programmable gate array) | |
| CN114710152B (en) | A baud rate phase detector circuit using alternating edges | |
| CN105591649B (en) | A kind of clock data signal restoring circuit based on over-sampling structure | |
| CN202488431U (en) | Device achieving data synchronization | |
| US11582018B2 (en) | Clock data calibration circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |