CN112216333B - Chip testing method and device - Google Patents
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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Abstract
The application is applicable to the technical field of semiconductor chips, and provides a chip testing method which comprises the following steps: writing first data to each memory cell in the semiconductor chip to be tested; respectively executing N times of reading operation on each storage unit to obtain a first result, wherein N is a positive integer greater than or equal to 3; and determining whether the semiconductor chip to be tested is a chip with faults according to the first result. By the method, the semiconductor chip with faults can be effectively and accurately detected.
Description
Technical Field
The application belongs to the technical field of semiconductor chips, and particularly relates to a chip testing method and device.
Background
The invention of semiconductor chips is an innovation in the twentieth century, which opens the way to the information age. To advance the semiconductor industry, it is common from the perspective of shrinking the size of semiconductor processes.
Along with the continuous reduction of the semiconductor process size, the probability of faults of the semiconductor chip is increased, the fault types are increased continuously, and the test time and the test cost are increased rapidly, but the existing test method still has difficulty in effectively and accurately detecting the semiconductor chip with faults.
Disclosure of Invention
The embodiment of the application provides a chip testing method and device, which can solve the following problems: the existing test method is difficult to effectively and accurately detect the semiconductor chip with faults.
In a first aspect, an embodiment of the present application provides a chip testing method, including:
writing first data to each memory cell in the semiconductor chip to be tested;
respectively executing N times of reading operation on each storage unit to obtain a first result, wherein N is a positive integer greater than or equal to 3;
and determining whether the semiconductor chip to be tested is a chip with faults or not according to the first result.
In a second aspect, an embodiment of the present application provides a chip testing apparatus, where the chip testing apparatus is applied to a first terminal, and the chip testing apparatus includes:
a first writing unit for writing first data to each memory cell in the semiconductor chip to be tested;
the first reading unit is used for respectively executing N times of reading operation on each storage unit to obtain a first result, wherein N is a positive integer greater than or equal to 3;
and the first determining unit is used for determining whether the semiconductor chip to be tested is a chip with faults or not according to the first result.
In a third aspect, an embodiment of the present application provides a terminal device, including: a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing steps of the chip test method when the computer program is executed.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium, comprising: the computer readable storage medium stores a computer program which, when executed by a processor, implements steps of a method for testing a chip, for example.
In a fifth aspect, embodiments of the present application provide a computer program product for, when run on a terminal device, causing the terminal device to perform the steps of the chip testing method of any one of the first aspects described above.
It will be appreciated that the advantages of the second to fifth aspects may be found in the relevant description of the first aspect, and are not described here again.
Compared with the prior art, the embodiment of the application has the beneficial effects that: after writing the first data to each memory cell in the semiconductor chip to be tested, N read operations are performed on each memory cell, respectively. N is a positive integer greater than or equal to 3, namely, each memory cell is subjected to multiple reading operations, the number of charges in the memory cells in the semiconductor chip to be tested may be reduced due to the multiple reading operations, the reduction of the number of charges may cause first data loss of the written memory cells, if the first data loss, the weak constitution of the semiconductor chip to be tested is indicated, and if the weak constitution of the semiconductor chip to be tested is indicated, the semiconductor chip to be tested is a failed chip, therefore, in the embodiment of the present application, the multiple reading operations are respectively performed on each memory cell to obtain a first result, and according to the first result, whether the semiconductor chip to be tested is the failed chip can be determined more effectively and accurately, namely, the embodiment of the present application can detect the failed semiconductor chip effectively and accurately.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments or the prior art will be briefly described below.
FIG. 1 is a flow chart of a first method for testing a chip according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a first memory cell according to an embodiment of the present disclosure;
FIG. 3 is a flow chart of a second method for testing chips according to an embodiment of the present application;
FIG. 4 is a flow chart of a third method for testing a chip according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a second memory cell according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a chip testing device according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a terminal device provided in an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Furthermore, the terms first, second and the like in the description and in the claims, are used for distinguishing between the descriptions and not necessarily for indicating or implying relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
Embodiment one:
fig. 1 shows a flow chart of a first chip testing method according to an embodiment of the present application, which is described in detail below:
the chip testing method can be applied to terminal equipment.
In this embodiment of the present application, the first data may be 0 or 1, and if the first data is 0, the second data is 1 correspondingly; if the first data is 1, the second data is 0 correspondingly.
The semiconductor chip to be tested comprises a plurality of memory blocks (banks), and each Bank comprises E rows and G columns of memory cells, wherein E is the row number of the memory cells contained in each Bank, and G is the column number of the memory cells contained in each Bank.
By way of example and not limitation, assume that a semiconductor chip under test includes 8 banks, each Bank containing E rows and G columns of memory cells, where E is 1024 and G is 32768, i.e., each Bank contains 1024 x 32768 memory cells. Assume that a first Bank in the semiconductor chip to be tested is Bank a, which can be shown in fig. 2.
Step S101, writing first data to each memory cell in the semiconductor chip to be tested.
As an example and not by way of limitation, assuming the first data is 1, correspondingly, step S101 may be specifically: each memory cell in the semiconductor chip under test is written with 1 once.
Step S102, N times of reading operation are respectively executed on each storage unit to obtain a first result, wherein N is a positive integer greater than or equal to 3.
Specifically, if the first data is successfully written into each memory cell in the semiconductor chip to be tested, N times of reading operation are respectively executed on each memory cell, and a first result is obtained. If the data read by each reading operation is the first data, the first result is used for indicating that the data read by each reading operation is the first data, and if the data read by each reading operation is not the first data, the first result is used for indicating that the data read by each reading operation is not the first data. When the first data is not read by the read operation, it may be indicated that the read operation occurs as follows: the read operation does not read any data.
In some embodiments, the terminal device has a display screen for facilitating the user to set N, and therefore, before step S102, includes: displaying a first setting interface on a display screen, receiving a first setting instruction set by a user on the first setting interface, and setting N according to the first setting instruction, wherein the first setting interface can comprise: n corresponds to an input box or N corresponds to a selection item, and a user can set N through the first setting interface.
The first setting instruction carries N and is used for indicating the terminal equipment to set N.
By way of example and not limitation, N may be 12.
Step S103, determining whether the semiconductor chip to be tested is a chip with faults according to the first result.
Specifically, if the first result indicates that the first data can not be read in every reading operation, the semiconductor chip to be tested is determined to be a chip with a fault.
Each memory cell is subjected to N number of read operations (N is a positive integer greater than or equal to 3), which corresponds to a number of stimulations performed on each memory cell, which may result in a reduced amount of charge in the memory cell and thus in a loss of the first data in the memory cell. If the first data is easy to lose, the data retention performance of the semiconductor chip to be tested is poor, and the data retention performance is as follows: the memory cells maintain the performance of the written data. For convenience of description, a semiconductor chip to be tested having poor data retention performance may be used as the semiconductor chip to be tested having a data retention barrier, which may be: the time that the memory cell holds the written data is short. Correspondingly, the step S103 may specifically be: if the first result indicates that the data read by each reading operation are the first data, determining that the semiconductor chip to be tested is not a chip with data retention faults; if the first result indicates that the first data can not be read in every reading operation, the semiconductor chip to be tested is determined to be the chip with the data retention fault.
In the embodiment of the application, after writing the first data to each memory cell in the semiconductor chip to be tested, N times of reading operations are respectively performed on each memory cell. N is a positive integer greater than or equal to 3, namely, each memory cell is subjected to multiple reading operations, the number of charges in the memory cells in the semiconductor chip to be tested may be reduced due to the multiple reading operations, the reduction of the number of charges may cause the first data loss of the written memory cells, if the first data loss indicates that the constitution of the semiconductor chip to be tested is weaker, if the constitution of the semiconductor chip to be tested is weaker, the semiconductor chip to be tested is a failed chip, therefore, in the embodiment of the present application, the multiple reading operations are respectively performed on each memory cell to obtain a first result, and according to the first result, whether the semiconductor chip to be tested is the failed chip can be effectively and accurately determined, namely, the embodiment of the present application can effectively and accurately detect the failed semiconductor chip.
Embodiment two:
fig. 3 is a schematic diagram showing a second chip testing method according to the embodiment of the present application, and step S303 of the present embodiment is the same as step S102 of the first embodiment, and is not repeated here:
In step S301, second data is written into each memory cell in the semiconductor chip to be tested, so as to obtain a second result.
Specifically, if the first data is successfully written into each memory cell in the semiconductor chip to be tested, N times of reading operation are respectively executed on each memory cell, and a first result is obtained. If the data read by each reading operation is the first data, the first result is used for indicating that the data read by each reading operation is the first data, and if the data read by each reading operation is not the first data, the first result is used for indicating that the data read by each reading operation is not the first data.
Specifically, second data are written once to each memory cell in the semiconductor chip to be tested, respectively, to obtain a second result. If the second data can be successfully written into each storage unit, the second result is used for indicating that the second data is written into each storage unit; if the second data cannot be successfully written into each storage unit, the second result is used for indicating that the second data is not written into each storage unit.
Optionally, a plurality of memory cell addresses are pre-stored in the semiconductor chip to be tested, and step S301 includes: step c) is performed for each memory cell address separately:
And c, searching a storage unit corresponding to the storage unit address, and if the storage unit address corresponds to the searched storage unit one by one, writing second data to the searched storage unit.
Step c is performed for each memory cell address, which corresponds to traversing each memory cell address. In the process of traversing each memory cell address, if each memory cell address has a memory cell corresponding to each memory cell address, determining the semiconductor chip to be tested as a chip without addressing faults (Adress Decoder Faults, AF); if the memory cells corresponding to each memory cell address one by one cannot be found (for example, a plurality of memory cells corresponding to a single memory cell address, a single memory cell corresponding to a plurality of memory cell addresses, a memory cell not corresponding to a single memory cell address, etc.), the semiconductor chip to be tested is determined to be a chip with addressing failure, that is, the semiconductor chip to be tested is determined to be a chip with failure.
In some embodiments, if a memory cell corresponding to each memory cell address cannot be found, determining the semiconductor chip to be tested as a chip having an addressing failure. Where addressing failures may result in write data failures. The write data failure is: data cannot be written to the failure of all memory cells in the semiconductor chip under test.
In some embodiments, after step S301, comprising: and if the second result indicates that the second data is not written in each storage unit, determining that the semiconductor chip to be tested is a chip with faults.
Specifically, if the second result indicates that the second data is not written in each memory cell, the semiconductor chip to be tested is determined to be the chip with the fault of writing the data.
In step S302, if the second result indicates that the second data has been written into each memory cell, the first data is written into each memory cell in the semiconductor chip under test.
By way of example and not limitation, assuming that the second data is 0 and the first data is 1, if the second result indicates that 0 has been written to each memory cell, it is indicated that the semiconductor chip under test is not a chip having a write data failure, and 1 is written to each memory cell in the semiconductor chip under test.
In step S303, N times of reading operations are performed on each memory cell, so as to obtain a first result, where N is a positive integer greater than or equal to 3.
Optionally, before step S303, it includes: respectively executing a reading operation on each storage unit to obtain a third result; correspondingly, step S303 includes: if the third result indicates that the data read by each reading operation is the first data, N times of reading operation are respectively executed on each storage unit.
Specifically, if the first data can be successfully written into each memory cell in the semiconductor chip to be tested in step S302, a read operation is performed on each memory cell to obtain a third result, where the third result may be used to indicate that the data read by each read operation is the first data, or indicate that the first data cannot be read by each read operation. When the first data is not read by the read operation, the following condition occurs in the read operation: the read operation does not read any data.
If the third result indicates that the first data can not be read in each reading operation, that is, the first data in each storage unit in the semiconductor chip to be tested can not be correctly read, the semiconductor chip to be tested can be determined to be the chip with the data reading fault, that is, the semiconductor chip to be tested is determined to be the chip with the fault; if the third result indicates that the data read by each reading operation is the first data, that is, the first data in each storage unit in the semiconductor chip to be tested can be correctly read, the semiconductor chip to be tested is determined to be the chip without the data reading fault.
Before step S303, a read operation is performed on each memory cell, so as to obtain a third result, and according to the third result, it can be determined whether the semiconductor chip to be tested has a data reading obstacle. If the third result indicates that the data read by each reading operation is the first data, it can be determined that the semiconductor chip to be tested has no data reading obstacle. After determining that the semiconductor chip to be tested has no data reading fault, N times of reading operation are respectively carried out on each storage unit, and a first result is obtained. Thus, the first result is effectively prevented from being influenced by the data reading fault.
Step S304, determining whether the semiconductor chip to be tested is a chip with faults according to the first result.
Specifically, if the first result indicates that the data read by each reading operation is the first data, determining that the semiconductor chip to be tested is not a chip with data retention fault; if the first result indicates that the first data can not be read in every reading operation, the semiconductor chip to be tested is determined to be the chip with the data retention fault.
In the embodiment of the application, the second data is written to each storage unit in the semiconductor chip to be tested to obtain the second result, if the second result indicates that the second data is written to each storage unit, the second result indicates that the semiconductor chip to be tested has no data writing fault, after the fact that the semiconductor chip to be tested has no data writing fault is determined, the first data is written to each storage unit in the semiconductor chip to be tested, and the multiple times of reading operation is respectively performed on each storage unit to obtain the first result, if the first result indicates that the first data can not be read in each reading operation, and the first result is not caused by the data writing fault, the first result can be accurately determined to be caused by the data holding fault, and the semiconductor chip to be tested can be accurately determined to be the chip with the data holding fault, namely, the semiconductor chip with the fault can be effectively and accurately detected.
Embodiment III:
fig. 4 is a schematic diagram showing a third method for testing a chip according to the embodiment of the present application, where step S401 and step S402 in the present embodiment are the same as step S101 and step S102 in the first embodiment, and are not repeated here:
step S401, writing first data to each memory cell in the semiconductor chip to be tested;
step S402, respectively executing N times of reading operation on each storage unit to obtain a first result, wherein N is a positive integer greater than or equal to 3;
in step S403, if the first result indicates that the data read by each reading operation is the first data, the second data is written to each memory cell, and a fourth result is obtained.
Specifically, if the first result indicates that the data read by each reading operation is the first data, writing the second data into each storage unit, and if the second data can be successfully written into each storage unit, the fourth result is used for indicating that the second data is written into each storage unit; if the second data cannot be successfully written into each memory cell, the fourth result is used for indicating that the second data is not written into each memory cell.
In some embodiments, if the fourth result indicates that the second data is not written to each memory cell, the semiconductor chip under test is determined to be a chip with a fault, specifically, the semiconductor chip under test is determined to be a chip with a fault of writing data.
In some embodiments, if the fourth result indicates that the second data has been written to each memory cell, it indicates that the semiconductor chip under test has no write data obstacle after a plurality of read operations.
In step S404, if the fourth result indicates that the second data has been written into each memory cell, the first data is written into each memory cell Q times, and Q is a positive integer greater than or equal to 3.
By way of example and not limitation, assuming Q is 12, correspondingly, step S404 is specifically: if the fourth result indicates that the second data has been written to each memory cell, the first data is written to each memory cell 12 times, respectively.
In some embodiments, the terminal device has a display screen for convenience of user setting Q, and thus, before step S404, includes: displaying a second setting interface on the display screen, receiving a second setting instruction set by a user on the second setting interface, and setting Q according to the second setting instruction, wherein the second setting interface can comprise: q corresponds to an input box or a selection item corresponding to Q, and a user can set Q through the first setting interface.
The second setting instruction carries Q and is used for indicating the terminal device to set Q.
In step S405, a read operation is performed on each memory cell, resulting in a fifth result.
Specifically, a read operation is performed once for each memory cell, resulting in a fifth result.
Specifically, a fifth result is obtained by executing a read operation on each memory cell, where if the data read by each read operation is the first data, the fifth result is used to indicate that the data read by each read operation is the first data, and if the data can not be read by each read operation, the fifth result is used to indicate that the data can not be read by each read operation.
Step S406, determining whether the semiconductor chip to be tested is a chip with fault according to the fifth result.
Specifically, if the fifth result indicates that the data read by each reading operation is the first data, determining that the semiconductor chip to be tested is not a chip with a data retention fault; if the fifth result indicates: and if the first data can not be read in every reading operation, determining the semiconductor chip to be tested as a chip with data retention faults.
Optionally, each storage unit corresponds to a storage unit address, where the smallest storage unit address is the first address, and correspondingly, writing the first data Q times to each storage unit includes: writing Q times of first data to the storage unit corresponding to the first address; the following step a is executed for each storage unit corresponding to the non-head address, wherein the step a is as follows: performing a reading operation on the storage unit corresponding to the non-first address to obtain a sixth result, and writing Q times of first data on the storage unit corresponding to the non-first address; correspondingly, step S406 includes: and determining whether the semiconductor chip to be tested is a chip with faults according to the fifth result and the sixth result.
The memory cell address is the number of the memory cell in the semiconductor chip to be tested. As an example and not by way of limitation, each memory cell address is a hexadecimal number, for example, as shown in fig. 5, it is assumed that a first Bank in the semiconductor chip to be tested is Bank a, and a memory cell address corresponding to a first memory cell in an upper left corner of Bank a is the smallest, that is, a memory cell corresponding to a first memory cell in an upper left corner of Bank a is a first memory cell.
The sixth result is used for indicating that the data read by the reading operation is the first data or indicating that the data read by the reading operation is the second data. In addition, the failure in step S406 includes: data retention Faults or/and Coupling Faults (CF), correspondingly, step S406 includes: and determining whether the semiconductor chip to be tested is a chip with coupling faults according to the sixth result, and determining whether the semiconductor chip to be tested is a chip with data retention faults according to the fifth result.
The reason for the coupling failure may be: a circuit with a short circuit or/and coupling exists between the memory cells, and the coupling fault can be expressed as follows: a change in state of one memory cell causes a change in state of another memory cell.
Wherein, determining whether the semiconductor chip to be tested is a chip with coupling fault according to the sixth result specifically comprises: if the sixth result obtained after each execution of the step a indicates that the data read by the reading operation is the second data, determining that the semiconductor chip to be tested is not a chip with coupling fault; if the sixth result indicates that the data read by the reading operation is the first data, the semiconductor chip to be tested is determined to be the chip with the coupling fault.
For convenience of description, a memory cell preceding and adjacent to the current memory cell corresponding to the sixth result is referred to as a last memory cell corresponding to the sixth result, for example, assume that the current memory cell corresponding to the sixth result is: a memory cell having a memory cell address of 0002 is a memory cell having a memory cell address of 0001, and a memory cell adjacent to a memory cell having a memory cell address of 0002 before the memory cell having a memory cell address of 0002 is a memory cell having a memory cell address of 0001, and the memory cell having a memory cell address of 0001 is the last memory cell corresponding to the sixth result. If the sixth result indicates that the data read by the reading operation is the second data, it indicates that after the last storage unit corresponding to the sixth result is written with the first data for Q times, the state of the last storage unit corresponding to the sixth result does not affect the current storage unit corresponding to the sixth result. If all the sixth results indicate that the data read by the reading operation is the second data, the semiconductor chip to be tested is not a chip with coupling fault can be accurately determined according to the sixth results; if the sixth result indicates that the data read by the reading operation is the first data, the semiconductor chip to be tested can be more accurately determined to be the chip with the coupling fault.
Optionally, the steps of all the steps of writing data to each memory cell and the steps of reading operation are performed in a first order before determining whether the semiconductor chip to be tested is a chip having a failure according to the fifth result, the first order being for indicating: the step of writing data to each memory cell and the step of reading operation are performed in the order of the memory cell addresses from small to large, the reverse order of the first order being a second order for indicating: the step of writing data to each memory cell and the step of reading operation are performed in the order of the memory cell addresses from large to small, and correspondingly, step S406 includes:
and b1, if the fifth result indicates that the data read by each reading operation are the first data, writing the second data to each storage unit in the semiconductor chip to be tested according to the second sequence to obtain a sixth result.
And b2, if the sixth result indicates that the second data is written into each storage unit, writing the first data into each storage unit in the semiconductor chip to be tested according to a second sequence.
And b3, respectively executing N times of reading operation on each storage unit according to the second sequence to obtain a seventh result.
And b4, determining whether the semiconductor chip to be tested is a chip with faults according to the seventh result.
Wherein the step of performing all write data to each memory cell before determining whether the semiconductor chip to be tested is a failed chip according to the fifth result may include the steps of: the writing of the first data to each memory cell in the semiconductor chip to be tested, the writing of the first data to each memory cell Q times, the writing of the second data to each memory cell in the semiconductor chip to be tested, and the writing of the first data to each memory cell Q times; the step of performing all read operations for each memory cell before determining whether the semiconductor chip to be tested is a failed chip according to the fifth result may include the steps of: the above-mentioned N times of read operations are performed on each of the memory cells, respectively, and the above-mentioned read operations are performed on each of the memory cells.
Wherein the sixth result may be used to indicate that the second data has been written to each memory cell or to indicate that the second data has not been written to each memory cell. The seventh result may be used to indicate that the data read by each read operation is the first data, or that the first data is not readable by each read operation.
The step b4 specifically includes: if the seventh result indicates that the data read by each reading operation are the first data, determining that the semiconductor chip to be tested is not a chip with data retention faults; if the seventh result indicates that the first data can not be read every reading operation, the semiconductor chip to be tested is determined to be the chip with the data retention fault.
Both the step of reading and the step of writing data may result in a reduced amount of charge in the memory cells in the semiconductor chip under test (the reduced amount of charge is colloquially referred to as "leakage"). The steps of determining whether the semiconductor chip to be tested is a failed chip according to the fifth result, all the steps of writing data to each memory cell and the steps of reading operation are performed in the first order, and can be used for determining the forward leakage condition of the semiconductor chip to be tested, and the subsequent steps b1 to b4 can be used for determining the reverse leakage condition of the semiconductor chip to be tested, so that the data retention performance of the semiconductor chip to be tested can be more comprehensively determined, that is, whether the semiconductor chip to be tested is a chip with data retention failure can be more comprehensively and accurately determined.
Illustrating forward leakage and reverse leakage conditions. The storage unit of the semiconductor chip to be tested is assumed to be composed of a capacitor, and correspondingly, the positive leakage condition is the positive leakage condition of the capacitor, and the reverse leakage condition is the negative leakage condition of the capacitor.
In this embodiment of the present application, writing the first data to each memory cell for a plurality of times is equivalent to performing a plurality of times of stimulation to each memory cell, and after the plurality of times of stimulation, performing a read operation on each memory cell to obtain a fifth result, where if the fifth result indicates that the first data cannot be read in each read operation, it is described that: some memory cells cannot hold the written first data or/and some memory cells hold the written first data for a short time, so that it can be explained that the constitution of the semiconductor chip to be tested is weak (weakbit), and if the constitution of the semiconductor chip to be tested is weak, the semiconductor chip to be tested is a chip with a fault. That is, in the embodiment of the present application, the first data is written to each memory cell for multiple times, and then the read operation is performed to each memory cell, so as to obtain a fifth result, and according to the fifth result, whether the semiconductor chip to be tested is a chip with a fault can be effectively and accurately determined, that is, the embodiment of the present application can effectively and accurately detect the semiconductor chip with the fault.
Embodiment four:
corresponding to the above embodiment, fig. 6 shows a schematic structural diagram of a chip testing device according to an embodiment of the present application, where the chip testing device includes: a first writing unit 601, a first reading unit 601, and a first determining unit 603.
The chip testing device can be applied to terminal equipment.
A first writing unit 601 for writing first data to each memory cell in the semiconductor chip to be tested.
The chip testing device further includes: a second writing unit.
The second writing unit is used for: before the first writing unit 601 writes the first data to each memory cell in the semiconductor chip to be tested, writing the second data to each memory cell in the semiconductor chip to be tested to obtain a second result, where correspondingly, the first writing unit 601 is specifically configured to: and if the second result indicates that the second data is written into each storage unit, writing the first data into each storage unit in the semiconductor chip to be tested.
The chip testing device further includes: and a second determination unit.
The second determining unit is used for: and after the second writing unit writes second data to each storage unit in the semiconductor chip to be tested to obtain a second result, if the second result indicates that the second data is not written in each storage unit, determining that the semiconductor chip to be tested is a chip with faults.
The first reading unit 602 is configured to: and respectively executing N times of reading operation on each storage unit to obtain a first result, wherein N is a positive integer greater than or equal to 3.
Optionally, the terminal device is provided with a display screen, so that, for convenience of setting N by a user, the chip test apparatus further includes: a first setting unit.
The first setting unit is used for: before the first reading unit 602 performs N reading operations on each storage unit, a first setting interface is displayed on the display screen, a first setting instruction set on the first setting interface by a user is received, and N is set according to the first setting instruction, where the first setting interface may include: n corresponds to an input box or N corresponds to a selection item, and a user can set N through the first setting interface.
The chip testing device further includes: and a second reading unit.
The second reading unit is used for: before the first reading unit 602 performs N times of reading operations on each memory cell to obtain a first result, performing a reading operation on each memory cell to obtain a third result, and correspondingly, when the first reading unit 602 performs N times of reading operations on each memory cell to obtain the first result, the method is specifically used for: if the third result indicates that the data read by each reading operation is the first data, executing the reading operation on each storage unit for N times respectively to obtain a first result.
The first determining unit 603 determines whether the semiconductor chip to be tested is a chip having a failure according to the first result.
The first determining unit 603 may specifically be configured to: if the first result indicates that the data read by each reading operation are the first data, writing the second data into each storage unit to obtain a fourth result; if the fourth result indicates that the second data are written into each storage unit, respectively writing Q times of first data into each storage unit, wherein Q is a positive integer greater than or equal to 3; performing a read operation on each memory cell to obtain a fifth result; and determining whether the semiconductor chip to be tested is a chip with faults according to the fifth result.
Optionally, each memory cell corresponds to a memory cell address, where the smallest memory cell address is the first address, and correspondingly, when writing the first data Q times to each memory cell, the first determining unit 603 is specifically configured to: writing Q times of first data to the storage unit corresponding to the first address; the following step a) is executed for each storage unit corresponding to the non-head address respectively: performing a reading operation on the storage unit corresponding to the non-first address to obtain a sixth result, and writing Q times of first data on the storage unit corresponding to the non-first address; correspondingly, the determining whether the semiconductor chip to be tested is a chip with a fault according to the fifth result includes: and determining whether the semiconductor chip to be tested is a chip with faults according to the fifth result and the sixth result.
In some embodiments, the terminal device has a display screen, so that the chip test apparatus further includes: and a second setting unit.
The second setting unit is used for: before the first determining unit 603 executes the foregoing description that if the fourth result indicates that the second data has been written into each storage unit, respectively writing Q times of the first data into each storage unit, displaying a second setting interface on the display screen, receiving a second setting instruction set by the user on the second setting interface, and setting Q according to the second setting instruction, where the second setting interface may include: q corresponds to an input box or a selection item corresponding to Q, and a user can set Q through the first setting interface.
In the embodiment of the application, after writing the first data to each memory cell in the semiconductor chip to be tested, N times of reading operations are respectively performed on each memory cell. N is a positive integer greater than or equal to 3, namely, each memory cell is subjected to multiple reading operations, the number of charges in the memory cells in the semiconductor chip to be tested may be reduced due to the multiple reading operations, the reduction of the number of charges may cause the first data loss of the written memory cells, if the first data loss indicates that the constitution of the semiconductor chip to be tested is weaker, if the constitution of the semiconductor chip to be tested is weaker, the semiconductor chip to be tested is a failed chip, therefore, in the embodiment of the present application, the multiple reading operations are respectively performed on each memory cell to obtain a first result, and according to the first result, whether the semiconductor chip to be tested is the failed chip can be effectively and accurately determined, namely, the embodiment of the present application can effectively and accurately detect the failed semiconductor chip.
Fifth embodiment:
fig. 7 is a schematic structural diagram of a chip test terminal device according to an embodiment of the present application. As shown in fig. 7, the chip test terminal device 7 of this embodiment includes: at least one processor 70 (only one shown in fig. 7), a memory 71, and a computer program 72 stored in the memory 71 and executable on the at least one processor 70, the processor 70 implementing the steps in any of the various chip test method embodiments described above when executing the computer program 72.
The chip test terminal device 7 may be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server, etc. The chip test termination device may include, but is not limited to, a processor 70, a memory 71. It will be appreciated by those skilled in the art that fig. 7 is merely an example of the chip test terminal device 7 and is not meant to be limiting as to the chip test terminal device 7, and may include more or less components than illustrated, or may combine certain components, or different components, such as may also include input-output devices, network access devices, etc.
The processor 70 may be a central processing unit (Central Processing Unit, CPU) and the processor 70 may be other general purpose processors, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), an off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 71 may in some embodiments be an internal storage unit of the chip test terminal device 7, such as a hard disk or a memory of the chip test terminal device 7. The memory 71 may in other embodiments also be an external memory device of the chip test terminal device 7, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash Card (Flash Card) or the like, which are provided on the chip test terminal device 7. Further, the memory 71 may also include both an internal memory unit and an external memory device of the chip test terminal device 7. The memory 71 is used for storing an operating system, application programs, boot loader (BootLoader), data, other programs, etc., such as program codes of the computer program. The memory 71 may also be used to temporarily store data that has been output or is to be output.
It should be noted that, because the content of information interaction and execution process between the above units is based on the same concept as the method embodiment of the present application, specific functions and technical effects thereof may be referred to in the method embodiment section, and will not be described herein again.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
The present application also provides a computer readable storage medium storing a computer program which, when executed by a processor, implements steps for implementing the various method embodiments described above.
Embodiments of the present application provide a computer program product which, when run on a mobile terminal, causes the mobile terminal to perform steps that may be performed in the various method embodiments described above.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the present application implements all or part of the flow of the method of the above embodiments, and may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, where the computer program, when executed by a processor, may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in the form of source code, object code, executable files or in some intermediate form, etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photo terminal equipment, a recording medium, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Such as a U-disk, removable hard disk, magnetic or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed network device and method may be implemented in other manners. For example, the network device embodiments described above are merely illustrative, e.g., the division of the modules or elements is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The above embodiments are merely for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (8)
1. A method for testing a semiconductor chip, comprising:
writing first data to each memory cell in the semiconductor chip to be tested;
respectively executing N times of reading operation on each storage unit to obtain a first result, wherein N is a positive integer greater than or equal to 3;
Determining whether the semiconductor chip to be tested is a chip with faults according to the first result;
before the writing of the first data to each memory cell in the semiconductor chip under test, comprising:
writing second data into each storage unit in the semiconductor chip to be tested to obtain a second result; if the second data can be successfully written into each storage unit, the second result is used for indicating that the second data is written into each storage unit; if the second data cannot be successfully written into each storage unit, the second result is used for indicating that the second data is not written into each storage unit;
correspondingly, the writing of the first data by each memory cell in the semiconductor chip to be tested comprises the following steps:
if the second result indicates that the second data is written into each storage unit, writing first data into each storage unit in the semiconductor chip to be tested;
writing second data to each memory cell in the semiconductor chip to be tested to obtain a second result, wherein the second result comprises the following steps:
and if the second result indicates that the second data is not written in each storage unit, determining that the semiconductor chip to be tested is a chip with faults.
2. The chip testing method of claim 1, comprising, before said performing N read operations on each of said memory cells, respectively:
respectively executing a reading operation on each storage unit to obtain a third result;
correspondingly, the performing N times of read operations on each memory cell respectively includes:
and if the third result indicates that the data read by each reading operation is the first data, executing N times of reading operation on each storage unit respectively.
3. The method for testing a chip according to claim 1, wherein determining whether the semiconductor chip to be tested is a chip having a fault according to the first result comprises:
if the first result indicates that the data read by each reading operation are the first data, writing the second data into each storage unit to obtain a fourth result;
if the fourth result indicates that the second data is written into each storage unit, respectively writing Q times of first data into each storage unit, wherein Q is a positive integer greater than or equal to 3;
executing a reading operation on each storage unit to obtain a fifth result;
And determining whether the semiconductor chip to be tested is a chip with faults according to the fifth result.
4. The method of claim 3, wherein each memory cell corresponds to a memory cell address, and wherein the smallest memory cell address is a first address, and correspondingly, the writing Q times of the first data to each memory cell includes:
writing Q times of first data to the storage unit corresponding to the first address;
the following step a) is executed for each storage unit not corresponding to the head address respectively:
step a: performing a read operation on the storage units not corresponding to the first address to obtain a sixth result, and writing Q times of first data on the storage units not corresponding to the first address;
correspondingly, the determining whether the semiconductor chip to be tested is a chip with a fault according to the fifth result includes:
and determining whether the semiconductor chip to be tested is a chip with faults according to the fifth result and the sixth result.
5. The chip testing method according to claim 3, wherein the steps of all the write data and the read operation to each of the memory cells before the step of determining whether the semiconductor chip to be tested is a failed chip based on the fifth result are performed in a first order for indicating: the step of writing data to each memory cell and the step of reading data from each memory cell are performed in the order of the memory cell addresses from small to large, and the reverse order of the first order is a second order, where the second order is used to indicate: the step of writing data to each memory cell and the step of reading data from each memory cell are performed in the order of the memory cell addresses from large to small, and correspondingly, the step of determining whether the semiconductor chip to be tested is a chip with a fault according to the fifth result includes:
If the fifth result indicates that the data read by each reading operation are the first data, writing second data to each storage unit in the semiconductor chip to be tested according to a second sequence to obtain a sixth result;
if the sixth result indicates that the second data is written into each storage unit, writing first data into each storage unit in the semiconductor chip to be tested according to the second sequence;
respectively executing N times of reading operation on each storage unit according to the second sequence to obtain a seventh result;
and determining whether the semiconductor chip to be tested is a chip with faults according to the seventh result.
6. A chip testing apparatus, comprising:
a first writing unit for writing first data to each memory cell in the semiconductor chip to be tested;
the first reading unit is used for respectively executing N times of reading operation on each storage unit to obtain a first result, wherein N is a positive integer greater than or equal to 3;
a first determining unit, configured to determine, according to the first result, whether the semiconductor chip to be tested is a chip with a fault;
the chip testing device further includes:
the second writing unit is used for:
Writing second data to each storage unit in the semiconductor chip to be tested before the first writing unit writes the first data to each storage unit in the semiconductor chip to be tested, so as to obtain a second result, and if the second data can be successfully written to each storage unit, the second result is used for indicating that the second data is written to each storage unit; if the second data cannot be successfully written into each storage unit, the second result is used for indicating that the second data is not written into each storage unit;
correspondingly, the first writing unit is specifically used for writing first data to each memory cell in the semiconductor chip to be tested:
if the second result indicates that the second data is written into each storage unit, writing the first data into each storage unit in the semiconductor chip to be tested;
the second determining unit is used for:
and after the second writing unit writes second data to each storage unit in the semiconductor chip to be tested to obtain a second result, if the second result indicates that the second data is not written in each storage unit, determining that the semiconductor chip to be tested is a chip with faults.
7. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1 to 5 when the computer program is executed.
8. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method according to any one of claims 1 to 5.
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