CN112257365A - Method for establishing timing diagram in parallel based on geometric information - Google Patents
Method for establishing timing diagram in parallel based on geometric information Download PDFInfo
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- CN112257365A CN112257365A CN202011420689.5A CN202011420689A CN112257365A CN 112257365 A CN112257365 A CN 112257365A CN 202011420689 A CN202011420689 A CN 202011420689A CN 112257365 A CN112257365 A CN 112257365A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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Abstract
A method for establishing a time sequence diagram in parallel based on geometric information comprises the following steps: according to the geometric characteristics of the circuit diagram, performing geometric block division on the circuit diagram; starting a plurality of processes, and establishing a temporary timing chart in each geometric block in parallel; and splicing the temporary time sequence charts built in each geometric block into a complete time sequence chart. The method for establishing the timing diagram in parallel based on the geometric information can start a plurality of processes to establish the timing diagram in parallel for the geometric blocks, can be easily realized by a distributed system, and greatly shortens the time for establishing the timing diagram in the static timing analysis.
Description
Technical Field
The invention relates to the technical field of Electronic Design Automation (EDA), in particular to a method for establishing a timing diagram in parallel based on geometric information.
Background
In different stages of integrated circuit design, timing sequence inspection is required to be performed on the design to ensure that the designed circuit can meet the predetermined timing sequence requirement. Static Timing Analysis (STA) does not depend on excitation, and can quickly and accurately measure the circuit timing to measure the performance of the circuit.
Static timing analysis uses an exhaustive analysis method. It extracts all timing paths in the whole circuit, constructs a timing diagram, calculates the delay propagation of signals on the paths, and finds out the error violating the timing constraint.
The timing diagram mainly comprises logic nodes, connection relations and main input and output ports of the timing path. The logic nodes are logic units in design; the connection relation is the input and output relation of a logic unit in design; the primary input-output port is the designed input-output port.
With the increasing scale of integrated circuit design, the conventional static timing analysis tool needs a long time to establish all timing charts of the whole circuit.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a method for establishing a time sequence diagram in parallel based on geometric information, which can start a plurality of processes to establish the time sequence diagram in parallel for a geometric block, can be easily realized by a distributed system, and greatly shortens the time for establishing the time sequence diagram in static time sequence analysis.
In order to achieve the above object, the present invention provides a method for establishing a timing graph in parallel based on geometric information, comprising the following steps:
according to the geometric characteristics of the circuit diagram, performing geometric block division on the circuit diagram;
starting a plurality of processes, and establishing a temporary timing chart in each geometric block in parallel;
and splicing the temporary time sequence charts built in each geometric block into a complete time sequence chart.
Further, the step of dividing the circuit diagram into geometric blocks according to the geometric characteristics of the circuit diagram further includes inputting coordinates of the geometric blocks according to the circuit characteristics to complete the division of the geometric blocks.
Further, the step of dividing the circuit diagram into geometric blocks according to the geometric characteristics of the circuit diagram further includes calculating and dividing the geometric blocks according to the geometric information defined in the read-in Def file and the set number of processes.
Further, the number of the geometric blocks is an integral multiple of the process number set by the user.
Further, the step of starting a plurality of processes and establishing a temporary timing diagram in each geometric block in parallel further comprises reading the logic netlist information in the Def file and establishing the timing diagram according to the logic netlist information.
Further, the step of reading the logic netlist information in the Def file and establishing a timing diagram according to the logic netlist information further comprises the steps of reading the Def file with a geometric overlapping region according to the shape of the geometric block, extracting the logic netlist information located in the current geometric block from the Def file, and establishing the internal logic connection relation of the geometric block;
and establishing a temporary timing chart according to the connection relation of the internal logic nodes in each geometric block.
Further, the step of splicing the temporary time sequence diagrams established in each geometric block into a complete time sequence diagram further comprises the step of judging whether the temporary time sequence diagrams are complete time sequence diagrams.
Further, the step of judging whether the temporary timing diagram is a complete timing diagram further includes, when the temporary timing diagram is judged not to be a complete timing diagram, searching for the remaining nodes in the remaining geometric blocks according to the logical connection relation defined in the logical netlist, and splicing into the complete timing diagram.
To achieve the above object, the present invention further provides an electronic device, which includes a memory and a processor, where the memory stores a computer program running on the processor, and the processor executes the computer program to execute the steps of the method for establishing a timing diagram based on geometric information in parallel.
To achieve the above object, the present invention further provides a computer-readable storage medium, on which a computer program is stored, which when executed performs the steps of the method for parallel creation of a time diagram based on geometric information as described above.
The method for establishing the timing diagram in parallel based on the geometric information, the electronic equipment and the computer readable storage medium have the following advantages that:
1) dividing a large-scale logic circuit into a plurality of independent geometric blocks (Partition) according to the geometric characteristics of the circuit; when a temporary timing diagram is established, each Partition only needs to read a Def file required by the current Partition, and logic Netlist (Netlist) information defined in the Partition in the Def is reserved; when the timing diagram is spliced, the data volume required by interaction between the partitions can be controlled within a small range, and a plurality of processes (or threads) can be started to parallelly construct the timing diagram for the partitions.
2) The method can be easily realized by a distributed system, and the time for establishing the timing diagram in the static timing analysis is greatly shortened.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a method for parallel creation of timing diagrams based on geometric information according to the present invention;
FIG. 2 is a schematic diagram of a top level circuit structure according to an embodiment of the present invention;
FIG. 3 is a top level structure of a geometrically sliced circuit according to an embodiment of the present invention;
FIG. 4 is a Block5 diagram after geometric slicing according to an embodiment of the invention;
FIG. 5 is a schematic diagram of circuit information of Block5 in Partition1 and Partition2 after geometric slicing according to an embodiment of the invention;
FIG. 6 is a temporary timing diagram established in accordance with Block5 after a geometric cut Partition1 and Partition2, in accordance with an embodiment of the present invention;
FIG. 7 is a complete timing diagram after splicing in Partition1 according to an embodiment of the invention;
FIG. 8 is a diagram illustrating a static timing analysis data flow based on geometric information according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flowchart of a method for parallel creating a timing diagram based on geometric information according to the present invention, and the method for parallel creating a timing diagram based on geometric information according to the present invention will be described in detail with reference to fig. 1.
First, in step 101, a circuit diagram is divided into M × N geometric blocks according to geometric characteristics of the circuit diagram.
In this embodiment, a user may specify a division manner of the geometric block; estimating the division mode of the geometric blocks through the geometric information of the circuit; the finally divided geometric block is not limited to be a rectangle, and may be a figure of any shape.
Preferably, the number of geometric blocks is an integer multiple of the number of user-set processes. In this step, in order to ensure the computation load balance among the partitions, the number of partitions is an integral multiple of the number of processes set by the user as much as possible.
Preferably, when the number of processes is not set by the user, the number of geometric blocks to be divided is set according to the number of cores of the processor.
Preferably, the geometric information read into the module definition file (Def file) determines the Partition of the Partition, or the value of M, N and the area (coordinate) to be partitioned are manually set, so as to complete the Partition of the Partition.
In this embodiment, the Partition needs to read in geometric information of the Def file to determine the Partition of the Partition. The user may also manually set M, N values and the areas (coordinates) to be divided for the actual circuit diagram based on experience, thereby completing the division of the Partition.
At step 102, multiple processes (or threads) are started and a temporary timing diagram is built in parallel in each Partition.
Preferably, a timing diagram is created from the logic netlist information.
In this embodiment, the Def file includes not only Netlist but also physical information. When reading Def, the physical information can be omitted, and the reading time is reduced.
Preferably, for each Partition, according to the geometric shape of the Partition, only reading a Def file which geometrically has an overlapping (Overlap) region with the Partition, extracting Netlist information located in the current Partition from the Def, and establishing a logical connection relationship between Instance and Net in the Partition.
In this embodiment, when the logical connection is established, only Def that has geometric overlap with Partition may be read and processed according to the divided geometric blocks; only the logic netlist information in the current Partition in the Def is reserved; a temporary timing diagram may be established for each Partition in parallel. The advantage of reading Def in Partition is that Def in a large circuit may be very large, and each Partition reads the Def file needed by itself in parallel, thereby greatly improving the reading efficiency. When the Netlist information is reserved, only the information in the current Partition is reserved.
Preferably, the temporary timing chart is established according to the connection relation of each Partition internal logic node.
In this embodiment, since some instances or nets are located in multiple partitions, the timing diagram established in a single Partition is not necessarily complete, and is referred to as a temporary timing diagram.
In step 103, a plurality of processes (or threads) are started, and the temporary time sequence charts established in each Partition are spliced into a complete time sequence chart.
Preferably, the integrity in the temporary timing diagram established in the Partition is judged.
Preferably, if the temporary timing chart in the Partition is a complete timing chart, no processing is required.
Preferably, if the temporary timing diagram in the Partition is not a complete timing diagram, the remaining nodes are searched in other partitions according to the logical connection relationship defined in the Netlist, and the complete timing diagram is spliced.
In the embodiment, the complete temporary timing diagram in the Partition does not need to be processed; for the incomplete temporary timing diagram in the Partition, a complete timing diagram needs to be spliced through communication with other partitions according to the logic netlist information; the processing procedures of the respective partitions may be performed in parallel.
The method for parallel creating timing diagrams based on geometric information according to the present invention is further described below with reference to a specific embodiment.
Fig. 2 is a schematic diagram of a top layer structure of a circuit according to an embodiment of the invention. As shown in FIG. 2, the circuit has 8 blocks, which are Block1-Block 8.
And (1) dividing the circuit diagram into M-N geometric blocks (Partition) according to the geometric characteristics of the circuit diagram.
The way in which Partition is divided may be various. The first is that the user manually inputs the coordinate of the Partition according to the circuit characteristic to directly complete the Partition division; secondly, the program reads in the geometric information defined in the Def and the set number of processes (or threads) to calculate a reasonable segmentation mode; the third is that the user provides M, N values for the desired cut and the program incorporates an algorithm to estimate the reasonable cut location.
Fig. 3 is a schematic diagram of a top layer structure of a geometrically sliced circuit according to an embodiment of the present invention.
If the Partition coordinates are set in the first way, as shown in fig. 3, the coordinates of the transverse cut can be entered: (x 1, y 2) - > (x2, y 2), coordinates of longitudinal cut: (x2, y1) - > (x2, y3), thereby forming 2 × 2 partitions. It can be seen that after the division, each Partition is a standard rectangle, and the sizes of the 4 rectangles are not necessarily the same.
And (2) starting a plurality of processes (or threads), and establishing a temporary timing chart in each Partition in parallel.
Since the processing method of each Partition is the same, only Partition1 in the lower left corner of fig. 3 is separately described in this step.
As can be seen from FIG. 3, Partition1 only geometrically overlaps Block5, so only Def and Top Def of Block5 need to be read when establishing the Partition1 internal logical connection. And extracting Netlist only existing in Partition1 from the Def file, and storing the Netlist.
FIG. 4 is a Block5 diagram after geometric slicing according to an embodiment of the invention.
As shown in fig. 4, the circuit connection diagram extracted from Def and Top Def of Block5 (i.e. Def of Top Cell) is shown. Wherein the solid dots (e.g., in 1) represent the pins defined in Top Def. It can be seen that the circuits in Block5 are partly in Partition1 and partly in Partition2, with net5 and net7 being on the demarcation line.
FIG. 5 is a schematic diagram of circuit information of Block5 in Partition1 and Partition2 after geometric partitioning according to an embodiment of the invention.
As shown in FIG. 5, Partition1 contains 3 instances (r 1, r2, u 1) and 7 nets (Net 1-Net 7); the Partition2 comprises 2 instances (u 2, r 3) and 5 nets (Net 5, Net7, Net8, Net9 and Net 10); it should be noted that the Netlist stored in Partition1 also includes logical connections with other partitions.
FIG. 6 is a temporary timing diagram established in accordance with Block5 after a geometric cut Partition1 and Partition2, in accordance with an embodiment of the present invention.
As shown in fig. 6, the temporary timing chart is established in Partition1 on the left by the connection relationship between Instance and Net in Def; to the right is a temporary timing diagram created by the remainder of Block5 in Partition 2.
And (3) starting a plurality of processes (or threads), and splicing the temporary time sequence charts established in each Partition into a complete time sequence chart.
Since the processing method of each Partition is the same, in this step, the Partition1 alone is also explained.
The temporary timing diagram in Partition1 shown in fig. 6 is not a complete timing diagram, and data needs to be acquired from other partitions to be spliced into a complete timing diagram. The provisional time chart in Partition1 is analyzed below.
Two timing paths in the temporary timing diagram are complete:
and
. The two timing paths do not need to acquire data from other partitions.
Since net5 and net7 are divided, Partition1 has the following two incomplete timing paths.
At this time, Partition1 finds out the logical relationship in Netlist
And
present in Partition 2. Next, Partition2 is divided by data interaction between partitions
And
the timing diagram as the starting point is sent to Partition 1. Partition1, having obtained the complete information needed to construct the timing graph, can construct a complete timing graph.
FIG. 7 is a complete timing diagram after splicing in Partition1 according to an embodiment of the invention.
As shown in fig. 7, Partition1 splices the temporary timing charts in the two partitions to obtain a complete timing chart.
Each Partition can be constructed in the same way as a complete timing diagram based on the current Partition.
FIG. 8 is a diagram illustrating a static timing analysis data flow based on geometric information according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of a static time-series analysis data flow based on Partition after geometric partitioning. Since each Partition has a complete timing diagram, a process (or thread) can be started to perform analysis in parallel. Then, the time sequence analysis reports obtained by each Partition are combined to form a complete report. Thus, the establishment of the timing chart and the timing analysis of the whole circuit are completed.
The invention provides a method for quickly constructing a timing diagram, which divides a large-scale logic circuit into a plurality of independent partitions according to the geometric characteristics of the circuit; when a temporary timing chart is established, each Partition only needs to read a Def file required by the current Partition, and Netlist information defined in the Partition in the Def is reserved; when the time sequence diagram is spliced, the data volume required by interaction between partitions can be controlled within a very small range; multiple processes (or threads) may be launched to build a timing diagram for the Partition in parallel. The method can be easily realized by a distributed system by dividing a complex circuit into different geometric blocks and establishing the timing diagram for each geometric block in parallel, thereby greatly shortening the time for establishing the timing diagram in the static timing analysis.
In an embodiment of the present invention, there is also provided an electronic device, including a memory and a processor, where the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the method for establishing a timing diagram in parallel based on geometric information as described above.
In an embodiment of the present invention, there is also provided a computer-readable storage medium having stored thereon a computer program which, when running, performs the steps of the method for parallel creation of a timing graph based on geometric information as described above.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for establishing a time sequence diagram in parallel based on geometric information is characterized by comprising the following steps:
according to the geometric characteristics of the circuit diagram, performing geometric block division on the circuit diagram;
starting a plurality of processes, and establishing a temporary timing chart in each geometric block in parallel;
and splicing the temporary time sequence charts built in each geometric block into a complete time sequence chart.
2. The method for parallel creating timing diagrams based on geometric information as claimed in claim 1, wherein the step of dividing the circuit diagram into geometric blocks according to the geometric characteristics of the circuit diagram further comprises inputting the coordinates of the geometric blocks according to the circuit characteristics to complete the division of the geometric blocks.
3. The method for parallel establishing a timing diagram based on geometric information according to claim 1, wherein the step of dividing the circuit diagram into geometric blocks according to the geometric characteristics of the circuit diagram further comprises calculating and dividing the geometric blocks according to the geometric information defined in the read-in Def file and the set number of processes.
4. The method for parallel creation of timing graphs based on geometric information according to claim 1, wherein the number of geometric blocks is an integer multiple of the number of processes set by the user.
5. The method for parallel building of timing diagrams based on geometric information according to claim 1, wherein the step of starting a plurality of processes to build the temporary timing diagrams in parallel in each geometric block further comprises reading the logic netlist information in the Def file and building the timing diagrams according to the logic netlist information.
6. The method for parallel establishing a timing diagram based on geometric information according to claim 5, wherein the step of reading the logic netlist information in the Def file and establishing the timing diagram according to the logic netlist information further comprises the steps of reading the Def file with geometrically overlapped regions according to the shape of the geometric block, extracting the logic netlist information located in the current geometric block from the Def file, and establishing the internal logic connection relationship of the geometric block;
and establishing a temporary timing chart according to the connection relation of the internal logic nodes in each geometric block.
7. The method for parallel creation of timing graphs based on geometric information according to claim 1, wherein the step of splicing the temporary timing graphs created in each geometric block into a complete timing graph further comprises a step of determining whether the temporary timing graphs are complete timing graphs.
8. The method for parallel building of timing diagrams based on geometric information according to claim 7, wherein the step of determining whether the temporary timing diagram is a complete timing diagram further comprises, when it is determined that the temporary timing diagram is not a complete timing diagram, searching for remaining nodes in the remaining geometric blocks according to a logical connection relationship defined in the logical netlist, and splicing into a complete timing diagram.
9. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the method for parallel creation of timing diagrams based on geometric information according to any one of claims 1 to 8.
10. A computer-readable storage medium, on which a computer program is stored, which, when running, executes the steps of the method for parallel creation of a time diagram on the basis of geometric information according to any one of claims 1 to 8.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112800706A (en) * | 2021-04-08 | 2021-05-14 | 南京集成电路设计服务产业创新中心有限公司 | Method for miniaturizing fast lookup table line length model |
| CN116090383A (en) * | 2022-12-27 | 2023-05-09 | 广东高云半导体科技股份有限公司 | Method, device, computer storage medium and terminal for realizing static time sequence analysis |
| CN116822427A (en) * | 2023-05-17 | 2023-09-29 | 深圳鸿芯微纳技术有限公司 | Time sequence analysis method and device, electronic equipment and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8195439B1 (en) * | 2008-09-02 | 2012-06-05 | Infinisim, Inc. | Real-time adaptive circuit simulation |
| CN103207941A (en) * | 2013-04-27 | 2013-07-17 | 清华大学 | Transient analysis method and transient analysis system under integrated circuit power supply network full-parameter model |
| US8640066B1 (en) * | 2007-01-10 | 2014-01-28 | Cadence Design Systems, Inc. | Multi-phase models for timing closure of integrated circuit designs |
| CN106682285A (en) * | 2016-12-09 | 2017-05-17 | 深圳市紫光同创电子有限公司 | Static timing analysis method and device |
| CN108875106A (en) * | 2017-05-15 | 2018-11-23 | 中国科学院微电子研究所 | Circuit design transplanting method and system |
| CN110490970A (en) * | 2019-08-08 | 2019-11-22 | 广联达科技股份有限公司 | Store the method, apparatus and electronic equipment of three-dimensional geometric information |
| CN110765710A (en) * | 2019-10-22 | 2020-02-07 | 清华大学 | Universal logic synthesis method and device based on nonvolatile device |
| CN111079362A (en) * | 2019-12-18 | 2020-04-28 | 京微齐力(北京)科技有限公司 | Parallel comprehensive algorithm utilizing hierarchical information |
-
2020
- 2020-12-08 CN CN202011420689.5A patent/CN112257365B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8640066B1 (en) * | 2007-01-10 | 2014-01-28 | Cadence Design Systems, Inc. | Multi-phase models for timing closure of integrated circuit designs |
| US8195439B1 (en) * | 2008-09-02 | 2012-06-05 | Infinisim, Inc. | Real-time adaptive circuit simulation |
| CN103207941A (en) * | 2013-04-27 | 2013-07-17 | 清华大学 | Transient analysis method and transient analysis system under integrated circuit power supply network full-parameter model |
| CN106682285A (en) * | 2016-12-09 | 2017-05-17 | 深圳市紫光同创电子有限公司 | Static timing analysis method and device |
| CN108875106A (en) * | 2017-05-15 | 2018-11-23 | 中国科学院微电子研究所 | Circuit design transplanting method and system |
| CN110490970A (en) * | 2019-08-08 | 2019-11-22 | 广联达科技股份有限公司 | Store the method, apparatus and electronic equipment of three-dimensional geometric information |
| CN110765710A (en) * | 2019-10-22 | 2020-02-07 | 清华大学 | Universal logic synthesis method and device based on nonvolatile device |
| CN111079362A (en) * | 2019-12-18 | 2020-04-28 | 京微齐力(北京)科技有限公司 | Parallel comprehensive algorithm utilizing hierarchical information |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112800706A (en) * | 2021-04-08 | 2021-05-14 | 南京集成电路设计服务产业创新中心有限公司 | Method for miniaturizing fast lookup table line length model |
| CN116090383A (en) * | 2022-12-27 | 2023-05-09 | 广东高云半导体科技股份有限公司 | Method, device, computer storage medium and terminal for realizing static time sequence analysis |
| CN116822427A (en) * | 2023-05-17 | 2023-09-29 | 深圳鸿芯微纳技术有限公司 | Time sequence analysis method and device, electronic equipment and storage medium |
| CN116822427B (en) * | 2023-05-17 | 2024-08-09 | 深圳鸿芯微纳技术有限公司 | Time sequence analysis method and device, electronic equipment and storage medium |
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