CN112260367B

CN112260367B - A battery management system and a battery pack

Info

Publication number: CN112260367B
Application number: CN202011244128.4A
Authority: CN
Inventors: 李保安; 庄宪
Original assignee: Globe Jiangsu Co Ltd
Current assignee: Globe Jiangsu Co Ltd
Priority date: 2020-11-10
Filing date: 2020-11-10
Publication date: 2024-12-20
Anticipated expiration: 2040-11-10
Also published as: CN112260367A

Abstract

The invention provides a battery management system and a battery pack, wherein the battery management system comprises at least two analog front end chips, a control unit and a control unit, wherein the analog front end chips are used for collecting output voltage, output current or working temperature of a battery, the control unit is used for controlling the analog front end chips to be electrified and electrified, and when any analog front end chip is awakened by an external interference signal, the analog front end chips directly or indirectly supply power to the control unit so as to enable the control unit to work, and at the moment, the control unit sends an electrified signal to the analog front end chips so as to enable the analog front end chips to be electrified. Compared with the prior art, the battery management system can timely send the power-down signal to the analog front-end chip awakened by the external interference signal, so that the analog front-end chip awakened by the external interference signal can be powered down normally, and the problem that the battery core is over-discharged due to the fact that the analog front-end chip awakened by the external interference signal cannot be powered down is avoided.

Description

Battery management system and battery pack

Technical Field

The present invention relates to a battery management system and a battery pack having the same.

Background

With the progress of society, portable electric tools are increasingly used in our lives, and battery technology as a power source thereof is also continuously developed. From the viewpoints of environmental protection and repeated use, the demand of secondary batteries is increasing, and lithium batteries are becoming ideal batteries for portable electric tools by virtue of their unique advantages, such as high energy density, long service life, high discharge voltage, no memory effect, and the like. To meet the voltage and capacity requirements of portable power tools, lithium batteries may be used to power the tools.

In order to extend the life of the lithium battery pack and improve the reliability of the use of the lithium battery pack, it is necessary to manage the battery using a Battery Management System (BMS). The battery management system typically uses an analog front end chip (AFE) to sample the battery to obtain information about the output voltage, output current, operating temperature, etc. of the battery. When the battery core strings are more, a plurality of analog front end chips are generally cascaded, so that the sampling of the battery cores with multiple strings is completed. The power-on of the analog front-end chip is waken up through a TS pin hardware signal, and the power-off of the analog front-end chip is completed by a control unit (MCU) sending a power-off instruction through an I2C chip. When the battery is in the environment with serious interference, the high-string analog front end chip can be awakened abnormally, and the control unit is in an inactive state at the moment, so that the analog front end chip cannot be powered down, the high-string battery core is in an overdischarge problem, and even the whole battery pack is scrapped.

In view of the above, it is necessary to provide a new battery management system to solve the above problems.

Disclosure of Invention

The invention aims to provide a battery management system which can timely send a power-down signal to an analog front-end chip awakened by an external interference signal, so that the analog front-end chip awakened by the external interference signal can be powered down normally, and the problem that a battery core is over-discharged due to the fact that the analog front-end chip awakened by the external interference signal cannot be powered down is avoided.

The invention provides a battery management system, which comprises at least two analog front end chips, a control unit and a control unit, wherein the analog front end chips are used for collecting output voltage, output current or working temperature of a battery, the control unit is used for controlling the analog front end chips to be electrified and electrified, and when any analog front end chip is awakened by an external interference signal, the analog front end chips directly or indirectly supply power to the control unit so as to enable the control unit to work, and at the moment, the control unit sends an electrified signal to the analog front end chips so as to enable the analog front end chips to be electrified.

As a further improvement of the invention, the at least two analog front end chips comprise a primary analog front end chip and at least one advanced analog front end chip, when the advanced analog front end chip is awakened by an external interference signal, the advanced analog front end chip directly or indirectly sends an awakening signal to the primary analog front end chip to awaken the primary analog front end chip, then the primary analog front end chip supplies power for the control unit to enable the control unit to work, and at the moment, the control unit sends a down signal to the primary analog front end chip and the advanced analog front end chip to enable the primary analog front end chip and the advanced analog front end chip to be powered down.

As a further improvement of the invention, the control unit is provided with a communication pin, the analog front-end chip is provided with a TS pin connected with the communication pin, and the control unit sends a wake-up signal to the TS pin through the communication pin so as to wake up the analog front-end chip.

As a further improvement of the invention, the battery management system comprises a coupling wake-up circuit, the analog front end chip is provided with a 3V3 pin and a TS pin, the control unit is provided with a VCC pin, the 3V3 pin of the primary analog front end chip is connected to the VCC pin of the control unit, and the 3V3 pin of the advanced analog front end chip is connected to the TS pin of the primary analog front end chip through the coupling wake-up circuit.

As a further improvement of the invention, the analog front end chip further comprises a GND pin, the coupling wake-up circuit comprises a first resistor, a second resistor, a first capacitor and a second capacitor, two ends of the first resistor are respectively connected to a 3V3 pin and a GND pin of the advanced analog front end chip, two ends of the second resistor are respectively connected to a TS pin and a GND pin of the primary analog front end chip, two ends of the first capacitor are respectively connected to a TS pin and a 3V3 pin of the advanced analog front end chip of the primary analog front end chip, and two ends of the second capacitor are respectively connected to a GND pin of the primary analog front end chip and a GND pin of the advanced analog front end chip.

The battery management system further comprises an LDO chip for supplying power to the control unit, when any analog front-end chip is awakened by an external interference signal, the analog front-end chip sends an awakening signal to the LDO chip so that the LDO chip supplies power to the control unit and the control unit works, and at the moment, the control unit sends a power-down signal to the analog front-end chip so that the analog front-end chip is powered down.

As a further improvement of the invention, the control unit is provided with a communication pin and an EN pin, the LDO chip is provided with an EN pin, the communication pin is connected to the EN pin of the LDO chip, and the EN pin of the control unit is connected to the TS pin of the analog front-end chip.

As a further improvement of the invention, the 3V3 pin of the analog front end chip is connected to the EN pin of the LDO chip through a coupled wake-up circuit.

The coupling wake-up circuit comprises a third resistor, a fourth resistor, a third capacitor and a fourth capacitor, wherein two ends of the third resistor are respectively connected to a 3V3 pin and a GND pin of one analog front-end chip, two ends of the fourth resistor are respectively connected to an EN pin of the LDO chip and a GND pin of the other analog front-end chip, one end of the third capacitor is connected to one end, close to the 3V3 pin, of the third resistor, the other end of the third capacitor is connected to the EN pin of the LDO, one end of the fourth capacitor is connected to one end, close to the GND pin, of the third resistor, the other end of the fourth capacitor is connected to the GND pin of the LDO, and the 3V3 pins of the other analog front-end chips are connected to the EN pin of the LDO chip.

As a further improvement of the invention, diodes are arranged between the 3V3 pins of the rest of the analog front-end chips and the EN pins of the LDO chips, so that current can only flow into the EN pins of the LDO chips.

As a further improvement of the invention, before the control unit sends the power-down signal, the control unit detects whether the peripheral is connected with the battery, and if not, the control unit sends the power-down signal to the analog front-end chip so as to enable the analog front-end chip to power down.

As a further improvement of the present invention, if no peripheral device is connected to the battery, the control unit waits for a preset time and then sends a downlink signal to the analog front end chip.

The invention also discloses a battery pack which comprises a plurality of batteries and the battery management system.

The battery management system has the beneficial effects that the battery management system can timely send the power-down signal to the analog front-end chip awakened by the external interference signal, so that the analog front-end chip awakened by the external interference signal can be powered down normally, and the problem of over-discharge of the battery core caused by incapability of powering down the analog front-end chip awakened by the external interference signal is avoided.

Drawings

Fig. 1 is a schematic diagram of a battery management system according to a first embodiment of the present invention.

Fig. 2 is a schematic diagram of the structure of the coupled wake-up circuit of the first embodiment.

Fig. 3 is a schematic diagram of a battery management system according to a second embodiment of the present invention.

Fig. 4 is a block diagram of a battery management system according to a third embodiment of the present invention.

Fig. 5 is a schematic diagram of a coupled wake-up circuit according to a third embodiment.

Fig. 6 is a block diagram of a battery management system according to a fourth embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.

The invention discloses a battery management system, which comprises at least two analog front end chips (AFEs) and a control unit. The analog front end chip is used for collecting output voltage, output current or working temperature of the battery. The battery can be a single battery cell or a battery cell string formed by connecting a plurality of battery cells in series or in parallel. The control unit is used for controlling the power-on and power-off of the analog front-end chip. When any one of the analog front end chips is awakened by an external interference signal, the analog front end chip directly or indirectly supplies power to the control unit so that the control unit works. At this time, the control unit detects whether there is a peripheral connected to the battery. If not, the control unit sends a power-down signal to the analog front-end chip so as to enable the analog front-end chip to be powered down, thereby avoiding the problem that the battery is over-discharged due to the fact that the analog front-end chip awakened by the external interference signal cannot be powered down. Preferably, if no peripheral device is connected to the battery, the control unit waits for a preset time and then sends a downlink signal to the analog front-end chip. The following is a detailed description of specific embodiments.

Referring to fig. 1 and 2, a battery management system 100 is disclosed for monitoring the output voltage, output current or operating temperature of a battery 70. The battery 70 includes a first battery 71 and a second battery 72. The battery management system 100 includes an analog front end chip 110, a wake-up circuit 120 to wake up the analog front end chip 110, a control unit 130, an I2C unit 140, a coupled wake-up circuit 150, and an output component 160. Referring to fig. 1, the analog front end chip 110 is configured to detect an output voltage, an output current or an operating temperature of the battery 70. Each analog front end chip 110 includes a TS pin, an SDA pin, an SCL pin, and a 3V3 pin. The analog front end chip 110 includes a primary analog front end chip 111 and at least one advanced analog front end chip 112. The primary analog front end chip 111 is used to detect the first battery 71, and the advanced analog front end chip 112 is used to detect the second battery 72. In the present embodiment, the number of the advanced analog front end chips 112 is 1, but in other embodiments, the number of the advanced analog front end chips 112 may be set depending on the number of the batteries 70. The wake-up circuit 120 includes a primary wake-up circuit 121 coupled to the primary analog front-end chip 111 and a senior wake-up circuit 122 coupled to the senior analog front-end chip 112. The primary wake-up circuit 121 and the advanced wake-up circuit 122 each have a signal output pin and an EN pin. The signal output pin of the primary wake-up circuit 121 is connected to the TS pin of the primary analog front end chip 111, and the EN pin thereof is connected to the 3V3 pin of the advanced analog front end chip 112 through the coupling wake-up circuit 150. The signal output pin of the advanced wake-up circuit 122 is connected to the TS pin of the advanced analog front end chip 112, and the EN pin thereof is connected to the EN pin of the primary wake-up circuit 121. In this embodiment, the control unit 130 is a Micro Control Unit (MCU). The micro control unit 130 is connected to SDA pin, SCL pin of the primary analog front end chip 111 to communicate with the primary analog front end chip 111. The micro control unit 130 is also connected to the SDA pin, SCL pin of the advanced analog front end chip 112 through the I2C unit 140 to communicate with the advanced analog front end chip 112. The 3V3 pin of the primary analog front end chip 111 is connected to the VCC pin of the micro control unit 130 to supply power to the micro control unit 130. One end of the coupled wake-up circuit 150 is connected to the EN pin of the primary wake-up circuit 121, and the other end is connected to the 3V3 pin of the advanced analog front end chip 112. Referring to fig. 2, the coupled wake-up circuit 150 includes a first resistor 151, a second resistor 152, a first capacitor 153 and a second capacitor 154. Two ends of the first resistor 151 are respectively connected to the 3V3 pin and the GND pin of the advanced analog front end chip 112, and two ends of the second resistor 152 are respectively connected to the TS pin and the GND pin of the primary analog front end chip 111. In this embodiment, one end of the second resistor 152 is connected to the EN pin of the primary wake-up circuit 121, so as to be connected to the TS pin of the primary analog front end chip 111 through the primary wake-up circuit 121. The two ends of the first capacitor 153 are respectively connected to the TS pin of the primary analog front end chip 111 and the 3V3 pin of the advanced analog front end chip 112, and the two ends of the second capacitor 154 are respectively connected to the GND pin of the primary analog front end chip 111 and the GND pin of the advanced analog front end chip 112. Referring to fig. 1, the output assembly 160 includes a first positive terminal 161, a first negative terminal 162, a second positive terminal 163, a second negative terminal 164, and a communication terminal 165. The first positive electrode terminal 161 and the first negative electrode terminal 162 are connected to both ends of the first battery 71, and the second positive electrode terminal 163 and the second negative electrode terminal 164 are connected to both ends of the second battery 72, so that electric power of the first battery 71 and the second battery 72 is conveniently output through the first positive electrode terminal 161, the first negative electrode terminal 162, the second positive electrode terminal 163 and the second negative electrode terminal 164. The communication terminal 165 is connected to a COM communication pin of the micro control unit 130. Preferably, the EN pin of the primary wake-up circuit 121 is connected to the KEY terminal through a first diode D1 and to the COM communication pin of the micro control unit 130 through a second diode D2. This arrangement facilitates the micro control unit 130 to wake up the primary analog front end chip 111, the advanced analog front end chip 112 directly via the COM communication pin, or the user wakes up the primary analog front end chip 111, the advanced analog front end chip 112 directly via the KEY.

Referring to fig. 1, after the micro control unit 130 is not operated and the primary analog front end chip 111 is awakened by an external interference signal, the 3V3 pin of the primary analog front end chip 111 supplies power to the micro control unit 130, so that the micro control unit 130 can operate normally. At this time, the micro control unit 130 detects whether or not a peripheral is connected to the input assembly 160. If not, the micro control unit 130 transmits a power-down signal to the primary analog front end chip 111, so that the primary analog front end chip 111 is powered down, and then the micro control unit 130 is powered down. This is the case where the primary analog front end chip 111 directly powers the micro control unit 130. Preferably, if no peripheral device is connected to the input module 60, the micro control unit 30 waits for a preset time and then sends a power-down signal to the primary analog front end chip 111. The preset time may be set by a user as desired.

When the micro control unit 130 does not work and the advanced analog front end chip 112 is awakened by the external interference signal, the 3V3 pin of the advanced analog front end chip 112 sends an awakening signal to the TS pin of the primary analog front end chip 111 through the coupling awakening circuit 150, so as to awaken the primary analog front end chip 111, and at this time, the 3V3 pin of the primary analog front end chip 111 supplies power to the micro control unit 130, so that the micro control unit 130 works normally. At this time, the micro control unit 130 detects whether or not a peripheral is connected to the input assembly 160. If not, the micro control unit 130 directly transmits a down signal to the primary analog front end chip 111, and transmits a down signal to the advanced analog front end chip 112 through the I2C unit 140, and then the micro control unit 130 is powered off. This is the case when the advanced analog front end chip 112 indirectly powers the micro control unit 130. Preferably, if no peripheral device is connected to the input module 160, the micro control unit 130 waits a preset time and then sends a down signal to the primary analog front end chip 111 and the advanced analog front end chip 112. In this embodiment, the advanced analog front end chip 112 directly sends a wake-up signal to the primary analog front end chip 111. In other embodiments, however, the advanced analog front end chip 112 may also indirectly send a wake-up signal to the primary analog front end chip 111. For example, the advanced analog front end chip 112 sends a wake-up signal to the third analog front end chip, and then sends a wake-up signal to the primary analog front end chip 111 through the third analog front end chip, thereby realizing indirect wake-up of the primary analog front end chip 111.

In this embodiment, two ends of the first battery 71 are respectively connected to the first positive terminal 161 and the first negative terminal 162, and two ends of the second battery 72 are respectively connected to the second positive terminal 163 and the second negative terminal 164, so that a user can conveniently mate with the output assembly 160 through different butt-joint terminal groups, so that the battery 70 outputs a series voltage or a parallel voltage. In other embodiments, however, the battery 70 may be configured directly to output a series voltage. Fig. 3 shows a battery management system 200 of a second embodiment. The structure of the battery management system 200 is substantially the same as that of the battery management system 100, except that the positive electrode of the first battery 71 is directly connected to the negative electrode of the second battery 72, so that the battery 70 outputs a series voltage.

Compared with the prior art, the battery management system 100 of the present invention can send the power-down signal to the analog front-end chip 110 awakened by the external interference signal in time, so that the analog front-end chip 110 awakened by the external interference signal can be powered down normally, and the problem of overdischarge of the battery cell caused by failure of the power-down of the analog front-end chip 110 awakened by the external interference signal is avoided.

Fig. 4 shows a battery management system 300 according to a third embodiment of the present invention. The battery management system 300 includes an analog front end chip 310, a wake-up circuit 320 to wake up the analog front end chip 310, a control unit 330, an I2C unit 340, a coupled wake-up circuit 350, an LDO chip 360 to power the control unit 330, and an output component 370. Referring to fig. 4, the analog front end chip 310 is configured to detect an output voltage, an output current, or an operating temperature of the battery 70. Each analog front end chip 310 includes a TS pin, an SDA pin, an SCL pin, and a 3V3 pin. The analog front end chip 310 includes a first analog front end chip 311 and a second analog front end chip 312. The first analog front end chip 311 is used for detecting the first battery 71, and the second analog front end chip 312 is used for detecting the second battery 72. In the present embodiment, the number of the analog front end chips 310 is 2, but in other embodiments, the number of the analog front end chips 310 may be set depending on the number of the batteries 70. The wake-up circuit 320 includes a first wake-up circuit 321 coupled to the first analog front-end chip 311 and a second wake-up circuit 322 coupled to the second analog front-end chip 312. The first wake-up circuit 321 and the second wake-up circuit 322 both have a signal output pin and an EN pin. The signal output pin of the first wake-up circuit 321 is connected to the TS pin of the first analog front-end chip 311, and the signal output pin of the second wake-up circuit 322 is connected to the TS pin of the second analog front-end chip 312. The EN pins of the first and second wake-up circuits 321 and 322 are commonly connected to the EN pin of the control unit 330, so that the control unit 330 can wake up the first and second analog front-end chips 311 and 312. In this embodiment, the control unit 330 is a Micro Control Unit (MCU). The control unit 330 is connected to the SDA pin and the SCL pin of the first analog front end chip 311 so as to communicate with the first analog front end chip 311. The control unit 330 is further connected to the SDA pin and the SCL pin of the second analog front end chip 312 through the I2C unit 340 to communicate with the second analog front end chip 312. The coupled wake-up circuit 350 comprises a signal input and a signal output. The 3V3 pins of the first analog front end chip 311 and the second analog front end chip 312 are connected to the signal input terminal of the coupling wake-up circuit 350, and the signal output terminal of the coupling wake-up circuit 350 is connected to the LDO chip 360. the LDO chip 360 is configured to supply power to the control unit 330. The LDO chip 360 includes a BAT pin, an EN pin, and a 3V3 pin. The BAT pin of the LDO chip 360 is connected to a power supply, the EN pin is connected to the signal output terminal of the coupled wake-up circuit 350, and the 3V3 pin is connected to the VCC pin of the control unit 330. The output assembly 370 includes a positive terminal 371, a negative terminal 372, and a communication terminal 373. The positive terminal 371 is connected to the positive electrode of the second battery 72, the negative electrode of the second battery 72 is connected to the positive electrode of the first battery 71, the negative electrode of the first battery 71 is connected to the negative terminal 372, and the communication terminal 373 is connected to the COM communication pin of the control unit 330.

Referring to fig. 5, the coupled wake-up circuit 350 includes a third resistor 351, a fourth resistor 352, a third capacitor 353 and a fourth capacitor 354. Two ends of the third resistor 351 are respectively connected to the 3V3 pin and the GND pin of the second analog front-end chip 312, one end of the fourth resistor 352 is connected to the GND pin of the first analog front-end chip 311, and the other end is connected to the EN pin of the LDO chip 360. Two ends of the third capacitor 353 are respectively connected to the 3V3 pin of the second analog front end chip 312 and the EN pin of the LDO chip 360, and two ends of the fourth capacitor 354 are respectively connected to the GND pin of the first analog front end chip 311 and the GND pin of the second analog front end chip 312. The 3V3 pin of the first analog front end chip 311 is connected to the EN pin of the LDO chip 360. Preferably, the first analog front end chip 311 is connected to the EN pin of the LDO chip 360 through a sixth diode D6, so that current can only flow into the EN pin of the LDO chip 360.

Preferably, the EN pin of the LDO chip is connected to the COM communication pin of the control unit 330 through a fourth diode D4, so that the control unit 330 wakes up the LDO chip 360. The EN pin of the LDO chip 360 is also connected to the KEY through a fifth diode D5 so that the user wakes up the LDO chip 360 directly through the KEY.

Referring to fig. 4, when the control unit 330 is not operating and any one of the analog front-end chips 310 is awakened by an external interference signal, the 3V3 pin of the analog front-end chip 310 sends a signal to the coupling awakening circuit 350, so as to awaken the LDO chip 360, and at this time, the LDO chip 360 supplies power to the control unit 330, so that the control unit 330 operates normally. Then, the control unit 330 detects whether there is a peripheral connected to the battery 70. If not, the control unit 330 sends a power-down signal to the analog front end chip 310, so that the analog front end chip 310 is powered down.

In the present embodiment, the first and second batteries 71 and 72 are directly connected in series, so that only a series voltage can be output. In other embodiments, however, the first and second batteries 71, 72 may be configured to output a parallel voltage. Fig. 6 shows a battery management system 400 according to a fourth embodiment of the present invention, which has substantially the same structure as the battery management system 300, except that the first battery 71 and the second battery 72 are independent from each other. The first battery 71 outputs power through the first and second terminals 461 and 462, and the second battery 72 outputs power through the third and fourth terminals 463 and 464. So configured, a user may conveniently mate with the first, second, third, and fourth terminals 461, 462, 463, 464 through different docking terminals, such that the battery 70 outputs a series voltage or a parallel voltage.

The invention also discloses a battery pack, which comprises a battery 70 and a battery management system 100/200/300/400 for monitoring the battery 70.

The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A battery management system, comprising:

At least two analog front-end chips, the analog front-end chips are used to collect the output voltage, output current or operating temperature of the battery; and

A control unit, the control unit controls powering on and powering off the analog front-end chip;

When any analog front-end chip is awakened by an external interference signal, the analog front-end chip directly or indirectly supplies power to the control unit to enable the control unit to operate. At this time, the control unit sends a power-off signal to the analog front-end chip to power off the analog front-end chip;

The at least two analog front-end chips include a primary analog front-end chip and at least one advanced analog front-end chip; when the advanced analog front-end chip is awakened by an external interference signal, the advanced analog front-end chip directly or indirectly sends a wake-up signal to the primary analog front-end chip to wake up the primary analog front-end chip, and then the primary analog front-end chip supplies power to the control unit to enable the control unit to work; at this time, the control unit sends a power-off signal to the primary analog front-end chip and the advanced analog front-end chip to power off the primary analog front-end chip and the advanced analog front-end chip;

The battery includes a first battery and a second battery. The primary analog front-end chip is used to detect the first battery, and the advanced analog front-end chip is used to detect the second battery.

2. The battery management system as described in claim 1 is characterized in that: the control unit has a communication pin; the analog front-end chip has a TS pin connected to the communication pin; the control unit sends a wake-up signal to the TS pin through the communication pin, thereby waking up the analog front-end chip.

3. The battery management system as described in claim 1 is characterized in that: the battery management system includes a coupling wake-up circuit, the analog front-end chip has a 3V3 pin and a TS pin, and the control unit has a VCC pin; the 3V3 pin of the primary analog front-end chip is connected to the VCC pin of the control unit, and the 3V3 pin of the advanced analog front-end chip is connected to the TS pin of the primary analog front-end chip through the coupling wake-up circuit.

4. The battery management system as described in claim 3 is characterized in that: the analog front-end chip also includes a GND pin, and the coupling wake-up circuit includes a first resistor, a second resistor, a first capacitor and a second capacitor; the two ends of the first resistor are respectively connected to the 3V3 pin and the GND pin of the advanced analog front-end chip; the two ends of the second resistor are respectively connected to the TS pin and the GND pin of the primary analog front-end chip; the two ends of the first capacitor are respectively connected to the TS pin of the primary analog front-end chip and the 3V3 pin of the advanced analog front-end chip; the two ends of the second capacitor are respectively connected to the GND pin of the primary analog front-end chip and the GND pin of the advanced analog front-end chip.

5. The battery management system as described in claim 1 is characterized in that: the battery management system also includes an LDO chip for powering the control unit; when any analog front-end chip is awakened by an external interference signal, the analog front-end chip sends a wake-up signal to the LDO chip so that the LDO chip powers the control unit, thereby enabling the control unit to work; at this time, the control unit sends a power-off signal to the analog front-end chip so that the analog front-end chip is powered off.

6. The battery management system as claimed in claim 5 is characterized in that: the control unit has a communication pin and an EN pin, and the LDO chip has an EN pin; the communication pin is connected to the EN pin of the LDO chip; the EN pin of the control unit is connected to the TS pin of the analog front-end chip.

7 . The battery management system according to claim 5 , wherein the 3V3 pin of the analog front-end chip is connected to the EN pin of the LDO chip through a coupling wake-up circuit.

8. The battery management system as claimed in claim 7 is characterized in that: the coupling wake-up circuit includes a third resistor, a fourth resistor, a third capacitor and a fourth capacitor; the two ends of the third resistor are respectively connected to the 3V3 pin and the GND pin of an analog front-end chip; the two ends of the fourth resistor are respectively connected to the EN pin of the LDO chip and the GND pin of another analog front-end chip; one end of the third capacitor is connected to one end of the third resistor close to the 3V3 pin, and the other end is connected to the EN pin of the LDO; one end of the fourth capacitor is connected to one end of the third resistor close to the GND pin, and the other end is connected to the GND pin of the LDO; the 3V3 pins of the remaining analog front-end chips are connected to the EN pin of the LDO chip.

9. The battery management system as claimed in claim 8, characterized in that: a diode is further arranged between the 3V3 pin of the other analog front-end chips and the EN pin of the LDO chip, so that the current can only flow into the EN pin of the LDO chip.

10. The battery management system as claimed in claim 1 is characterized in that: before the control unit sends a power-off signal, the control unit detects whether a peripheral device is connected to the battery; if not, the control unit sends a power-off signal to the analog front-end chip to power off the analog front-end chip.

11. The battery management system according to claim 10, wherein if no peripheral device is connected to the battery, the control unit waits for a preset time before sending a power-off signal to the analog front-end chip.

12. A battery pack, comprising:

Batteries; and

A battery management system as claimed in any one of claims 1 to 11.