CN112271233A - Preparation method of silicon-based back-illuminated PIN device structure - Google Patents
Preparation method of silicon-based back-illuminated PIN device structure Download PDFInfo
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- H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
- H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
- H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
- H10F30/22—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
- H10F30/223—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PIN barrier
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Abstract
The invention discloses a preparation method of a silicon-based back-illuminated PIN device structure, which comprises the following steps: taking a substrate, cleaning the substrate, P + photoetching, injection, P + main expansion, epitaxial layer growth, initial oxidation, P trap photoetching, injection and well pushing, N-ring photoetching and injection, P isolation photoetching, injection and well pushing, N-photosensitive region photoetching, injection and oxidation, hole photoetching, front metallization, back thinning, anti-reflection film deposition and back metallization to obtain a silicon-based back-illuminated PIN device structure; according to the method, the size of the PIN photoelectric detector assembly is reduced by at least two thirds in a back-illuminated PIN structure ball-planting pressure welding mode, the PIN photoelectric detectors P + and N + are transversely interconnected, based on the back-illuminated PIN structure, the integration of the PIN structure photoelectric detector system is completed, and meanwhile, the photoelectric performance requirement is met.
Description
Technical Field
The invention relates to the technical field of semiconductor photoelectricity, in particular to a preparation method of a silicon-based back-illuminated PIN device structure.
Background
Depletion mode photodetector PIN photodiodes are often used in laser azimuthal detection, so this device is called a PIN photodiode, mainly because of an intrinsic layer (I-layer) between the P-N junctions.
The PIN structure photoelectric detector has the characteristics of high sensitivity and high resolution, low power consumption, high response speed and the like, and is widely applied to the fields of optical communication and other quick photoelectric automatic control equipment systems; due to the structural superiority and good photoelectric response characteristic of the PIN photodiode, the PIN photodiode has important applications in the aspects of optical communication, optical ranging, photometric measurement, photoelectric control and the like.
In order to improve the wavelength range and frequency response, the thickness of the intrinsic layer is controlled effectively, so as to reduce the gap between the intrinsic layer and the depletion layer width under reverse bias. The sensitivity and frequency response of the device is strongly dependent on the intrinsic layer in the PIN photodiode. This is mainly because the intrinsic layer is a high resistance region compared to the P region and the N region, and the intrinsic layer is a region where reverse bias is concentrated, and because of this, a high electric field region is formed in this region, and the resistance of the high electric field region is large, so that the dark current is reduced. The intrinsic layer can enlarge the depletion layer area after being introduced, so that the effective area of photoelectric conversion is increased, and the sensitivity of the photoelectric conversion is obviously improved.
The P-region is very thin and, in addition to the intrinsic layer, the incident photons are all absorbed within the intrinsic layer, thus forming electron-hole pairs. Under the action of a strong electric field, the photogenerated carriers accelerate, and therefore the transit time of the carriers is shortened. Due to the widening of the depletion layer, the junction capacitance C is causeddThe reduction and thus the corresponding reduction in the capacitance time constant results in a good improvement in the frequency response of the photodiode. If the photodiode is performing well, it will typically have a 10 th-10s magnitude diffusion and drift time, so that the circuit time constant is the main factor affecting the photodiode frequency response, generally speaking, the junction of the photodiodeThe capacitance is typically several picofarads. If the reverse bias voltage is increased appropriately, it is also decreased. In order to obtain high response frequency performance, in practical applications, it is necessary to pay attention to the reasonable selection of the load resistance.
At present, a plurality of PIN photoelectric detectors are widely applied, and the existing PIN photoelectric detectors are all of a front-illuminated type and are assembled by various components, so that the size is large, and the PIN photoelectric detectors cannot be applied to complex environments.
Disclosure of Invention
The invention aims to provide a preparation method of a silicon-based backside illuminated PIN device structure, which at least reduces the volume of a PIN photoelectric detector component by two thirds in a backside illuminated PIN structure ball-planting pressure welding mode, realizes that P + and N + of the PIN photoelectric detector are transversely interconnected, completes the integration of a PIN structure photoelectric detector system based on the backside illuminated PIN structure, and simultaneously meets the photoelectric performance requirement.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a preparation method of a silicon-based back-illuminated PIN device structure comprises the following steps:
s1, taking a P-type silicon wafer as a substrate;
s2, cleaning the substrate and removing dirt on the surface of the substrate;
s3, performing P + photoetching on the front side of the substrate through a photoetching process;
s4, performing P + ion implantation in the P + photoetching area;
s5, performing P + ion main diffusion through oxidation diffusion;
s6, growing an epitaxial layer on the surface of the substrate;
s7, carrying out initial oxidation on the surface of the epitaxial layer to obtain an oxide layer;
s8, performing P-well photoetching through a photoetching process, wherein the photoetching position of the P-well corresponds to the photoetching position of P < + >;
s9, performing P-well injection and drive-in at the P-well photoetching position;
s10, carrying out N-ring photoetching through a photoetching process to form an N-protection ring area pattern;
s11, performing N-ring implantation by an ion implantation technology;
s12, carrying out P isolation photoetching through a photoetching process to form a P isolation region pattern;
s13, performing P isolation injection and propulsion in the P isolation region;
s14, carrying out N-photosensitive area photoetching through a photoetching process to form an N-photosensitive area pattern;
s15, injecting an N-photosensitive area and performing N-oxidation;
s16, carrying out hole photoetching through a photoetching process to form a lead hole pattern;
s17, front metallization, forming an aluminum lead at the pattern position of the lead hole by utilizing sputtering and photoetching processes, and realizing self-connection and interconnection of the device structure;
s18, thinning the back of the substrate;
s19, depositing an anti-reflection film on the back of the substrate;
and S20, carrying out metallization treatment on the back surface, and carrying out four-quadrant isolation on the photosensitive area to obtain the silicon-based back-illuminated PIN device.
Further, in the step S1, the substrate is selected to be a P-type (100) 6-inch silicon wafer, the resistivity is 8-13 omega-cm, and the thickness is 675 +/-15 mu m.
Further, the P + lithography of step S3 is performed according to the following steps:
s31, homogenizing glue, namely selecting a positive photoresist, tackifying the surface of the silicon wafer by using HMDS, and then rotationally gluing the silicon wafer to obtain glue with the thickness of 1.0 +/-0.1 mu m;
s32, prebaking, namely setting the temperature of the silicon wafer coated with the photoresist on a heat release plate to be (100 +/-5) DEG C for 1 min;
s33, exposure, namely performing pattern registration exposure on a photoetching mask on a photoetching machine, wherein the registration precision is +/-0.5 mu m;
s34, developing, wherein the developing temperature is 20 +/-DEG C; developing for 1 + -0.1 min; washing with deionized water, centrifuging and drying, wherein the resistivity of the deionized water is more than or equal to 18 MOmega.cm;
s35, post-baking, namely putting the developed silicon wafer into a nitrogen-filled oven, and keeping the temperature at 120 +/-5 ℃ for 30 +/-2 min.
Further, the P + ion implantation of step S4 is performed by using an ion implantation technique to implant boron impurities with a dose of 3E15 and an implantation energy of 70 Kev.
Further, the implantation of the N-photosensitive region in step S15 utilizes an ion implantation technique to implant P with a dose of 7E1231 ＋Impurity, implant energy 250 Kev.
Further, step S18 thins the substrate to 200 μm + -10 μm.
The invention has the advantages that the traditional PIN photoelectric detector assembly is assembled in a large volume for microsystemization integration, the volume of the PIN photoelectric detector assembly is reduced by at least two thirds in a back-illuminated PIN structure ball-planting pressure welding mode, the PIN photoelectric detectors P + and N + are transversely interconnected, the PIN structure photoelectric detector system integration is completed based on the back-illuminated PIN structure, and meanwhile, the photoelectric performance parameters meet the design requirements.
Drawings
The invention is further illustrated with reference to the following figures and examples:
FIG. 1 is a schematic representation of step S1 of the present invention;
FIG. 2 is a schematic diagram of step S3 of the present invention;
FIG. 3 is a schematic diagram of steps S4 and S5 according to the present invention;
FIG. 4 is a schematic representation of step S6 of the present invention;
FIG. 5 is a schematic representation of step S7 of the present invention;
FIG. 6 is a schematic representation of step S8 of the present invention;
FIG. 7 is a schematic representation of step S9 of the present invention;
FIG. 8 is a schematic diagram of steps S10 and S11 according to the present invention;
FIG. 9 is a schematic representation of step S12 of the present invention;
FIG. 10 is a schematic representation of step S13 of the present invention;
FIG. 11 is a schematic representation of step S14 of the present invention;
FIG. 12 is a schematic representation of step S15 of the present invention;
FIG. 13 is a schematic representation of step S16 of the present invention;
FIG. 14 is a schematic representation of step S17 of the present invention;
FIG. 15 is a schematic representation of step S18 of the present invention;
FIG. 16 is a schematic representation of step S19 of the present invention;
fig. 17 is a schematic diagram of step S20 of the present invention.
Detailed Description
The invention provides a preparation method of a silicon-based back-illuminated PIN device structure, which comprises the following steps:
s1, as shown in figure 1, taking a P-type silicon wafer as a substrate 1; selecting a P-type (100) 6-inch silicon wafer, wherein the resistivity is 8-13 omega-cm, and the thickness is 675 +/-15 mu m;
s2, cleaning the substrate 1 and removing dirt on the surface of the substrate;
by adopting standard RCA cleaning, impurity pollutants on the surface of the wafer can be effectively removed, and the quality of an oxide layer of the wafer can be effectively improved;
the proportion of chemical reagents in the RCA cleaning process and the environmental temperature are as follows:
1. name: SC-1, RCA-1, chemical composition: NH4 OH: H2O2, H2O, the mixture ratio is as follows: 1: 2: 12.5, 65 ℃;
2. name: SC-2, RCA-2, chemical composition: HCL: H2O2, H2O, the mixture ratio is as follows: 1: 2: 12.5, 65 ℃;
3. name: SPM, chemical composition: h2SO 4: H2O2, proportioning: 4:1, 65 ℃;
4. name: diluted HF, chemical composition: H2O, and the proportion is as follows: 1: 100, 23 ℃;
s3, with reference to the graph shown in FIG. 2, performing P + photoetching on the front side of the substrate 1 through a photoetching process to form a P + graph 2;
p + lithography is performed as follows:
s31, glue homogenizing, namely selecting a positive photoresist 3, tackifying the surface of the silicon wafer by using HMDS, and then rotationally gluing the silicon wafer to obtain glue with the thickness of 1.0 +/-0.1 microns;
s32, prebaking, namely setting the temperature of the silicon wafer coated with the photoresist on a heat release plate to be (100 +/-5) DEG C for 1 min;
s33, exposure, namely performing pattern registration exposure on a photoetching mask on a photoetching machine, wherein the registration precision is +/-0.5 mu m;
s34, developing, wherein the developing temperature is 20 +/-DEG C; developing for 1 + -0.1 min; washing with deionized water, centrifuging and drying, wherein the resistivity of the deionized water is more than or equal to 18 MOmega.cm;
s35, post-baking, namely putting the developed silicon wafer into a nitrogen-filled oven, and keeping the temperature at 120 +/-5 ℃ for 30 +/-2 min;
s4, as shown in fig. 3, implanting P + ions 4 into the P + lithography area;
implanting boron impurities with the dose of 3E15 by using an ion implantation technology, wherein the implantation energy is 70 Kev;
s5, performing P + ion main diffusion through oxidation diffusion;
under the condition of temperature rise and temperature reduction of an oxidation diffusion furnace at 800-1130-800 ℃, 50min (N) is adopted2＋O2) Heating and stabilizing, and passing through 60minN2＋5minO2+N2(cooling to 800 ℃) so that the injected boron impurities are redistributed to a certain junction depth;
s6, growing an epitaxial layer 5 on the surface of the substrate, as shown in fig. 4;
and (3) polishing and corroding silicon by using HCL (hydrogen chloride), wherein the growth parameter is rho: >8000 omega-cm, w: the thickness is 80 mu m plus or minus 5 mu m;
s7, referring to FIG. 5, the initial oxidation is performed on the surface of the epitaxial layer 5 to obtain SO2An oxide layer 6;
the oxidation temperature is controlled to be 920 +/-0.5 ℃, and the oxidation time is as follows: 5 min (dry oxygen) + 30 min (DCE + O)2) + 5 minutes (dry oxygen); the thickness of the oxide layer is 50 +/-5 nm;
s8, as shown in fig. 6, performing P-well lithography through a lithography process, where the P-well lithography region 7 corresponds to the P + lithography position;
s9, with reference to fig. 7, performing implantation and drive-in of the P-well 8 at the P-well lithography position;
step-type ion implantation is adopted, namely the implantation energy is 800Kev, 2E14, and the + energy is 120Kev, 5E 15;
under the condition of temperature rise and temperature reduction of an oxidation diffusion furnace at the temperature of 800-1180-800 ℃, adopting (N2+ O)2) Heating, and performing 10minO2+840minN2＋N2Cooling to 800 deg.C to redistribute and diffuse the injected boron impurities to form a certain junctionDeep;
s10, combining with the figure 8, carrying out N-ring photoetching through a photoetching process to form an N-protection ring area figure 9;
s11, performing N-ring implantation by an ion implantation technology;
by using ion implantation technology, the implantation dosage is P31 of 4E15＋Impurity, the implantation energy is 120 Kev;
s12, as shown in fig. 9, performing P isolation photolithography by photolithography to form a P isolation region pattern 10;
s13, with reference to fig. 10, performing P isolation implantation and propulsion in the P isolation region to obtain an N + guard ring 11;
by using ion implantation technology, the implantation dosage is 2.5E 15B11 ＋Impurity with implantation energy of 50 Kev;
under the condition of raising and lowering temperature of oxidation diffusion furnace at 800-1130-920-800 deg.C, (N) is used2+O2) Heating for +1h and then N2+80minN2(the temperature is reduced to 920 ℃) and then 10minO2＋50min（H2+O2）＋10minO2＋15min N2Then N is2Cooling (to 800 ℃) to activate the injected N + protection ring and the P + isolation impurities and form a certain junction depth;
s14, as shown in the figure 11, carrying out N-photosensitive area photoetching through a photoetching process to form an N-photosensitive area pattern 11;
s15, as shown in fig. 12, performing N-photosensitive region implantation and N-oxidation to obtain an N-photosensitive layer 13;
using ion implantation technology, the implantation dosage is P of 7E1231 ＋Impurity, implantation energy is 250 Kev;
under the condition of temperature rise and temperature reduction of an oxidation diffusion furnace at the temperature of 800-920-800 ℃, adopting (N)2+O2) Heating, and then adding 10minO2＋10min（DCE+O2）＋10minO2＋50min（DCE+O2）＋10minO2+15min N2Then N is2Cooling (to 800 ℃); activating the injected N-impurities and forming a certain junction depth, and simultaneously forming an oxide film of the photosensitive area;
s16, as shown in fig. 13, performing hole lithography through a lithography process to form a lead hole pattern 14;
s17, with reference to fig. 14, forming an aluminum lead 15 at the position of the lead hole pattern by sputtering and photolithography processes to implement self-connection and interconnection of the device structure;
s18, referring to fig. 15, thinning the back surface of the substrate 1; thinning the substrate to 200 mu m +/-10 mu m;
s19, with reference to fig. 16, depositing an anti-reflection film 16 on the back side of the substrate; the photoelectric conversion efficiency is improved;
s20, with reference to fig. 17, performing metallization processing on the back surface, and performing four-quadrant isolation on the photosensitive region through the Al isolation layer 17 to obtain the silicon-based back-illuminated PIN device.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner; those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent replacement, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention.
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|---|---|---|---|---|
| US20050253132A1 (en) * | 2002-07-11 | 2005-11-17 | Marshall Gillian F | Photodetector circuits |
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| US20160307994A1 (en) * | 2013-10-23 | 2016-10-20 | Csmc Technologies Fab2 Co., Ltd. | Method for preparing power diode |
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| US20050253132A1 (en) * | 2002-07-11 | 2005-11-17 | Marshall Gillian F | Photodetector circuits |
| US7576371B1 (en) * | 2006-03-03 | 2009-08-18 | Array Optronix, Inc. | Structures and methods to improve the crosstalk between adjacent pixels of back-illuminated photodiode arrays |
| CN102110738A (en) * | 2009-12-25 | 2011-06-29 | 华东光电集成器件研究所 | Method for manufacturing double-sided phase-sensitive detector (PSD) device |
| CN102176470A (en) * | 2011-03-26 | 2011-09-07 | 电子科技大学 | Back-illuminated Si-PIN photoelectric detector taking black silicon material as photosensitive layer and manufacturing method thereof |
| US20160307994A1 (en) * | 2013-10-23 | 2016-10-20 | Csmc Technologies Fab2 Co., Ltd. | Method for preparing power diode |
| US20190067500A1 (en) * | 2017-08-28 | 2019-02-28 | Quantum Nanophotonics LLC | Quantum NPS Photodetector |
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| CN115308998A (en) * | 2021-05-07 | 2022-11-08 | 沈阳芯源微电子设备股份有限公司 | Tackifying unit with magnetic coupling PIN |
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| CN112271233B (en) | 2023-04-07 |
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