Detailed Description
Embodiments of the invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments discussed and disclosed are merely illustrative and are not intended to limit the scope of the invention.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions and/or sections, these elements, components, regions and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region and/or section from another element, component, region and/or section.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. The singular forms "a", "an" and "the" are intended to mean "a plurality of" unless otherwise limited. Furthermore, the spatially relative terms are used to describe various orientations of the elements in use or operation and are not intended to be limited to the orientations shown in the figures. Elements may also be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted in a similar manner.
As used herein, the term "coupled" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and "coupled" may mean that two or more elements are in operation or act with each other.
Reference numerals and/or letters may be repeated among the various embodiments for simplicity and clarity of illustration, but are not intended to indicate a resulting relationship between the various embodiments and/or configurations discussed.
Fig. 1A is a schematic diagram of a reflective display panel 100 according to an embodiment of the invention. The reflective display panel 100 may be various types of liquid crystal display panels such as a Twisted Nematic (TN) type, an in-plane switching (IPS) type, or a Vertical Alignment (VA) type, but is not limited thereto. The reflective display panel 100 has an active area AA having a plurality of pixel cells arranged in an array, and a peripheral area PA having a driving circuit for providing image data signals and scan signals to the pixel cells in the active area AA to display an image.
In addition, fig. 1B is a schematic diagram of light incidence and light reflection of the reflective display panel 100. As shown in fig. 1B, the incident light L from the external light source enters the reflective display panel 100 along the top view direction (direction D) of the reflective display panel 100, and the reflective display panel 100 generates the reflected light RL by the internal light reflection structure. In this way, the image displayed by the reflective display panel 100 can be viewed in an environment with an external light source.
Fig. 2A is an example of a pixel structure PM in an active area AA of the reflective display panel 100, and fig. 2B is an enlarged schematic diagram of a pixel unit PX in the pixel structure PM of fig. 2A. As shown in fig. 2A and 2B, the pixel structure PM is a matrix composed of a plurality of pixel units PX, and each pixel unit PX is composed of a color sub-pixel R and a black-and-white sub-pixel BW which are adjacent to each other. In each pixel unit PX, the color sub-pixel R is located on the left side of the black-and-white sub-pixel BW. The color sub-pixel R is used for generating color reflection light according to incident light, and the black-white sub-pixel BW is used for generating black-white reflection light according to incident light. The color sub-pixel R may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, a yellow sub-pixel, a cyan sub-pixel, or a magenta sub-pixel. The area of the color sub-pixel R is not larger than the area of the black and white sub-pixel BW. In some embodiments, the area ratio of the color sub-pixel R to the black and white sub-pixel BW is 0.5 to 1. Further, in a specific embodiment, the area ratio of the color sub-pixel R to the black and white sub-pixel BW is 4 to 5. In some embodiments, the pixel structure PM may include more than two different color sub-pixels R according to the application requirement.
Each pixel unit PX in the pixel structure PM includes a first data line DL1 electrically connected to the color sub-pixel R and a second data line DL2 electrically connected to the black and white sub-pixel BW. As shown in fig. 2B, the first data line DL1 and the second data line DL2 are respectively located at two opposite left and right sides of the pixel unit PX, wherein the first data line DL1 overlaps the color sub-pixel R in the top view direction of the pixel structure PM, and the second data line DL2 overlaps the black and white sub-pixel BW in the top view direction of the pixel structure PM. In other embodiments, the first data line DL1 may be located at the left side of the color sub-pixel R in the top down direction of the pixel structure PM, i.e. between the color sub-pixel R and the black-white sub-pixel BW of the left pixel unit PX, and/or the second data line DL2 may be located at the right side of the black-white sub-pixel BW in the top down direction of the pixel structure PM, i.e. between the black-white sub-pixel BW and the color sub-pixel R of the right pixel unit PX.
The planar distance L1 between the first data line DL1 and the black-and-white sub-pixel BW is at least 2.5 micrometers, so as to avoid crosstalk of the black-and-white sub-pixel BW caused by the first data line DL 1. Similarly, the planar distance L2 between the second data line DL2 and the color sub-pixel R is at least 2.5 μm, so as to prevent the second data line DL2 from causing crosstalk to the color sub-pixel R.
In the pixel unit PX shown in fig. 2B, the planar pattern of the color sub-pixel R is T-shaped, and the planar pattern of the black-and-white sub-pixel BW corresponds to U-shaped. Compared with the conventional stripe-shaped sub-pixel structure, the pixel structure PM formed by the T-shaped color sub-pixel R and the U-shaped black and white sub-pixel BW shown in fig. 2B can avoid the display problems such as color spots and/or bright and dark stripes of the reflective display panel 100.
Fig. 3A is another example of the pixel structure PM in the active area AA of the reflective display panel 100, and fig. 3B is an enlarged schematic diagram of the pixel unit PX in the pixel structure PM of fig. 3A. As shown in fig. 3A and 3B, the pixel structure PM is a matrix composed of a plurality of pixel units PX, and each pixel unit PX is composed of a color sub-pixel R and a black-and-white sub-pixel BW which are adjacent to each other. Fig. 3B is different from fig. 2B in that, in the plane pattern shown in fig. 3B, the plane pattern of the color sub-pixel R is L-shaped, and the plane pattern of the black-and-white sub-pixel BW is also L-shaped. Similarly, compared to the conventional stripe-shaped sub-pixel structure, the pixel structure PM formed by the L-shaped color sub-pixel R and the L-shaped black-white sub-pixel BW shown in fig. 3B can avoid the display problems such as color spots and/or bright and dark stripes of the reflective display panel 100. Other technical features of the color sub-pixel R, the black-and-white sub-pixel BW, the first data line DL1 and the second data line DL2 in fig. 3B are the same as those in the example in fig. 2B, so that please refer to the previous paragraphs for related description, which is not repeated herein.
Fig. 4A is a schematic view of another example of the pixel structure PM in the active area AA of the reflective display panel 100, and fig. 4B is an enlarged schematic view of the pixel unit PX in the pixel structure PM of fig. 4A. As shown in fig. 4A and 4B, the pixel structure PM is a matrix made up of a plurality of pixel units PX, and each pixel unit PX is made up of a color sub-pixel R and a black-and-white sub-pixel BW which are adjacent to each other. Fig. 4B is different from fig. 2B in that, in the planar pattern shown in fig. 4B, the planar pattern of the color sub-pixel R is Γ -shaped, and the planar pattern of the black-and-white sub-pixel BW is also Γ -shaped. Similarly, compared to the conventional stripe-shaped sub-pixel structure, the pixel structure PM formed by the Γ -shaped color sub-pixel R and the Γ -shaped black and white sub-pixel BW shown in fig. 4B can avoid the display problems such as color unevenness and/or bright and dark stripes of the reflective display panel 100. Other technical features of the color sub-pixel R, the black-and-white sub-pixel BW, the first data line DL1 and the second data line DL2 in fig. 4B are the same as those in the example of fig. 2B, so that please refer to the previous paragraphs for related description, which is not repeated herein.
Fig. 5A is a schematic view of another example of the pixel structure PM in the active area AA of the reflective display panel 100, and fig. 5B is an enlarged schematic view of the pixel unit PX in the pixel structure PM of fig. 5A. As shown in fig. 5A and 5B, the pixel structure PM is a matrix made up of a plurality of pixel units PX, and each pixel unit PX is made up of a color sub-pixel R and a black-and-white sub-pixel BW which are adjacent to each other. Fig. 5B is different from fig. 2B in that, in the planar pattern shown in fig. 5B, the color sub-pixel R is located on the right side of the black-and-white sub-pixel BW, the first data line DL1 overlaps the black-and-white sub-pixel BW in the top down direction of the pixel structure PM, and the second data line DL2 overlaps the color sub-pixel R in the top down direction of the pixel structure PM. In other embodiments, the first data line DL1 may be located at the left side of the black-and-white sub-pixel BW in the top-down direction of the pixel structure PM, i.e. between the black-and-white sub-pixel BW and the color sub-pixel R of the left pixel unit PX, and/or the second data line DL2 may be located at the right side of the color sub-pixel R in the top-down direction of the pixel structure PM, i.e. between the color sub-pixel R and the black-and-white sub-pixel BW of the right pixel unit PX. The planar distance L1' between the first data line DL1 and the color sub-pixel R is at least 2.5 microns to avoid crosstalk of the first data line DL1 to the color sub-pixel R. Similarly, the planar distance L2' between the second data line DL2 and the black-and-white sub-pixel BW is also at least 2.5 micrometers, so as to avoid the second data line DL2 from causing crosstalk to the black-and-white sub-pixel BW.
Fig. 6A is a schematic view of another example of the pixel structure PM in the active area AA of the reflective display panel 100, and fig. 6B is an enlarged schematic view of the pixel unit PX in the pixel structure PM of fig. 6A. As shown in fig. 6A and 6B, the pixel structure PM is a matrix made up of a plurality of pixel units PX, and each pixel unit PX is made up of a color sub-pixel R and a black-and-white sub-pixel BW which are adjacent to each other. Fig. 6B is different from fig. 2B in that, in the plane pattern shown in fig. 6B, the plane pattern of the color sub-pixel R is trapezoidal, and the plane pattern of the black-and-white sub-pixel BW is also correspondingly trapezoidal. As shown in fig. 6B, the width of the color sub-pixel R is gradually decreased from top to bottom, and the width of the black-white sub-pixel BW is gradually increased from top to bottom. In other embodiments, the width of the color sub-pixel R may increase from top to bottom, and the width of the black-white sub-pixel BW may decrease from top to bottom. Similarly, compared to the conventional stripe-shaped pixel structure, the pixel structure PM formed by the trapezoidal color sub-pixel R and the trapezoidal black-white sub-pixel BW shown in fig. 6B can avoid the display problems such as color spots and/or bright dark stripes of the reflective display panel 100. Other technical features of the color sub-pixel R, the black-and-white sub-pixel BW, the first data line DL1 and the second data line DL2 in fig. 6B are the same as those in the example of fig. 2B, so that please refer to the previous paragraphs for related description, which is not repeated herein.
Fig. 7A is an example of a cross-sectional view of the corresponding color sub-pixel R of the reflective display panel 100. As shown in fig. 7A, the reflective display panel 100 includes an active array substrate 100A and a color filter substrate 100B disposed opposite to each other, and a display medium layer 100C disposed between the active array substrate 100A and the color filter substrate 100B, wherein a substrate 102 in the active array substrate 100A and a substrate 122 in the color filter substrate 100B are disposed at the outermost side of the reflective display panel 100.
In the active array substrate 100A, a first metal layer 104 is located on the substrate 102, which includes the gate and the scan lines. A gate insulating layer 106, a semiconductor layer 108A and a doped semiconductor layer 108B are sequentially located on the substrate 102 and the gate. A second metal layer 110 is located on the gate insulating layer 106, the semiconductor layer 108A, and the doped semiconductor layer 108B, which includes a source electrode, a drain electrode, and a data line. The gate, the source, the drain, the semiconductor layer 108A, the doped semiconductor layer 108B, and a portion of the gate insulating layer 106 constitute a thin film transistor TFT, and the first metal layer 104, the gate insulating layer 106, the semiconductor layer 108A, the doped semiconductor layer 108B, and the second metal layer 110 are collectively referred to as an active element layer herein.
A protective layer 112 is located on the first metal layer 104, the gate insulating layer 106, and the second metal layer 110, and a transparent conductive layer 114 is located on the protective layer 112 and contacts the drain electrode through a through hole in the protective layer 112. Coating 116 is located on protective layer 112 and transparent conductive layer 114, and third metal layer 118 is located on coating 116 and contacts transparent conductive layer 114 through perforations in coating 116. The third metal layer 118 is used as a reflective layer of the reflective display panel 100, the surface of the coating layer 116 away from the substrate 102 has a plurality of protruding structures 116A, the protruding structures 116A are arranged in a honeycomb shape in the top view direction of the reflective display panel 100, and the third metal layer 118 overlaps the protruding structures 116A in the top view direction of the reflective display panel 100 and is conformal with the protruding structures 116A, which provides scattering and diffusing effects to increase the reflection amount of light incident into the reflective display panel 100, thereby improving the brightness of the reflective display panel 100.
The substrate 102 may be made of glass, quartz, ceramic, a combination thereof, or other similar insulating materials, and may be a flexible substrate including, but not limited to, Polyimide (PI) or polyethylene terephthalate (PET). The materials of the first metal layer 104, the second metal layer 110, and the third metal layer 118 may include, but are not limited to, chromium, tungsten, tantalum, titanium, molybdenum, aluminum, copper, and other metal elements, or other similar elements, or alloys or compounds formed by any combination of the above metal elements. The material of the gate insulating layer 106 and the protective layer 112 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric material. The material of the semiconductor layer 108A may be amorphous silicon, single crystal silicon, polycrystalline silicon, or other similar materials, and the material of the doped semiconductor layer 108B may be correspondingly doped amorphous silicon, doped single crystal silicon, doped polycrystalline silicon, or other similar materials. The material of the transparent conductive layer 114 may be, for example, a transparent conductive material such as indium tin oxide and indium zinc oxide, but is not limited thereto. In addition, the material of the coating 116 may be an organic or inorganic dielectric material.
Referring to fig. 7A, in the color filter substrate 100B, a filter element 124 is disposed on the substrate 122 for passing light of a specific color, such as red light, green light, blue light, yellow light, cyan light, magenta light or other colors, which can be set according to the application requirements of the reflective display panel 100. The color filter substrate 100B further includes a black matrix layer (not shown) disposed on the substrate 122 and used for defining the area of each sub-pixel in the reflective display panel 100. For example: a patterned black matrix layer is formed on the substrate 122, and then the filter element 124 is formed on the patterned black matrix layer or filled into the gap of the patterned black matrix layer to define the region of the color sub-pixel R. The coating 126 and the transparent conductive layer 128 are sequentially located on the filter element 124. The material of the coating 126 may be an organic or inorganic dielectric material. In addition, the material of the transparent conductive layer 128 may be, for example, a transparent conductive material such as indium tin oxide and indium zinc oxide, but is not limited thereto.
The display medium layer 100C may be a liquid crystal layer or a medium layer made of other non-self-luminous display medium materials. Taking the liquid crystal layer as an example, the display medium layer 100C includes a plurality of liquid crystal molecules LC, which may be, for example, nematic liquid crystal molecules, cholesteric liquid crystal molecules, or other liquid crystal molecules having reflective properties. In addition, in some embodiments, as shown in fig. 7A, the display medium layer 100C may further include a spacer 130 sandwiched between the third metal layer 118 in the active array substrate 100A and the transparent conductive layer 128 in the color filter substrate 100B, so that the active array substrate 100A and the color filter substrate 100B have a predetermined spacing.
Fig. 7B is an example of a cross-sectional view of the black-and-white sub-pixel BW of the reflective display panel 100. Compared with the cross-sectional view of the corresponding color sub-pixel R shown in fig. 7A, in the cross-sectional view of the corresponding black and white sub-pixel BW shown in fig. 7B, the color filter substrate 100B does not include a filter element, and the rest is the same as the description of fig. 7A, so the description thereof is omitted.
Fig. 8A is another example of a cross-sectional view of the corresponding color sub-pixel R of the reflective display panel 100. Fig. 8A is different from fig. 7A in that, in the cross-sectional view of the corresponding color sub-pixel R shown in fig. 8A, the transparent conductive layer 114 and the third metal layer 118 are sequentially located on the coating layer 116, and the transparent conductive layer 114 contacts the drain electrode of the thin film transistor TFT through the coating layer 116 and the through hole in the protection layer 112. In addition, the transparent conductive layer 114 and the third metal layer 118 are conformal with the protrusion structure 116A, which provides scattering and diffusion effects to increase the reflection amount of light incident into the reflective display panel 100, thereby improving the brightness of the reflective display panel 100. Similar to fig. 7A, the color filter substrate 100B further includes a black matrix layer (not shown) on the substrate 122 for defining the area of each sub-pixel in the reflective display panel 100.
Fig. 8B is another example of a cross-sectional view of the corresponding black-and-white sub-pixel BW of the reflective display panel 100. Compared with the cross-sectional view of the corresponding color sub-pixel R shown in fig. 8A, in the cross-sectional view of the corresponding black and white sub-pixel BW shown in fig. 8B, the color filter substrate 100B does not include a filter element, and the rest is the same as the description of fig. 8A, so the description thereof is omitted.
Fig. 9A is an example of an equivalent circuit of a sub-pixel of the reflective display panel 100 of the liquid crystal type. The sub-pixel of fig. 9A may be a color sub-pixel R or a black and white sub-pixel BW. The sub-pixel comprises a thin film transistor TFT and a liquid crystal capacitor CLCAnd a storage capacitor CS. The source and gate of the TFT are respectively coupled to the data line DL and the scan line SL, and are used for controlling the image data signal provided by the data line DL to be written into the liquid crystal capacitor C at a specific time according to the scan signal provided by the scan line SLLCTo control the display period and the gray scale value of the sub-pixel. Liquid crystal capacitor CLCOne terminal of and a storage capacitor CSOne terminal of the storage capacitor is coupled to the drain electrode of the thin film transistor TFT and the storage capacitor CSThe other end of the first electrode is coupled to the common line CL, and the liquid crystal capacitor CLCIs coupled to a common voltage V at the other endCOM. In some embodiments, the common line CL also provides the common voltage VCOM。
Fig. 9B is another example of an equivalent circuit of a sub-pixel of the reflective display panel 100 of the liquid crystal type. Compared with the equivalent circuit shown in fig. 9A, in the equivalent circuit shown in fig. 9B, the sub-pixel has two serially connected TFTs 1 and 2, and the gates thereof are respectively coupled to the scan lines SL1 and SL 2. The thin film transistors TFT1 and TFT2 can step down the sub-pixels in turn, and can effectively reduce the generation of leakage current, thereby reducing the overall power consumption of the reflective display panel 100. In some embodiments, for the sub-pixels coupled to the same data line DL and adjacent to each other up and down, the scan line SL2 of the upper sub-pixel and the scan line SL1 of the lower sub-pixel provide the same scan signal.
Fig. 10 is an example of a system block diagram of the reflective display panel 100 of fig. 1A. As shown in fig. 10, the reflective display panel 100 further includes a source driver circuit SD and gate driver circuits GD1, GD2, which are located in the peripheral region PA of the reflective display panel 100. The source driving circuit SD transmits a data signal to each pixel cell PX in the active area AA of the reflective display panel 100 through the data lines D (1) -D (m), and the gate driving circuits GD1, GD2 transmit a scan signal to each pixel cell PX in the active area AA of the reflective display panel 100 through the odd scan lines S (1), S (3), S (5), S (7) … and the even scan lines S (2), S (4), S (6), S (8) …, respectively. In some embodiments, the source driving circuit SD and the gate driving circuits GD1, GD2 may be integrated in a single driving chip.
Specifically, in the odd-numbered rows of pixel units PX, the 1 st pixel row (i.e., the pixel row formed by the 1 st row of pixel units PX in the active area AA) is coupled to the scan lines S (1), S (3), the 3 rd pixel row is coupled to the scan lines S (3), S (5), the 5 th pixel row is coupled to the scan lines S (5), S (7), and so on, while in the even-numbered rows of pixel units PX, the 2 nd pixel row is coupled to the scan lines S (2), S (4), the 4 th pixel row is coupled to the scan lines S (4), S (6), the 6 th pixel row is coupled to the scan lines S (6), S (8), and so on. In brief, in the reflective display panel 100, the nth pixel row is coupled to the scan lines S (n), S (n + 2).
Each pixel unit PX in fig. 10 may be, for example, the pixel unit PX shown in fig. 2B, fig. 3B, fig. 4B, fig. 5B, or fig. 6B, but is not limited thereto. Taking the pixel unit PX in the m-th column and the n-th row as an example, the color sub-pixel R and the black-and-white sub-pixel BW in the pixel unit PX in the m-th column and the n-th row are coupled to the scan lines S (n), S (n +2), and are coupled to the data lines D (2m-1), D (2m), respectively.
Fig. 11A to 11C are signal timing diagrams of the reflective display panel 100 shown in fig. 10. As shown in fig. 11A, when the reflective display panel 100 enters from the (i-1) th frame (not shown) to the i-th frame, the common voltage is inverted from the low potential to the high potential, and in the i-th frame, the data signal is raised from the low potential to the high potential when the scan signal is lowered from the high potential to the low potential, and when the reflective display panel 100 enters from the i-th frame to the (i +1) th frame, the common voltage is inverted from the high potential to the low potential, and in the (i +1) th frame, the data signal is lowered from the high potential to the low potential when the scan signal is lowered from the high potential to the low potential, and so on. Note that the scanning signal shown in fig. 11A is at a high potential represents that the potential of at least one of the scanning lines S (1), S (2) … is at a high potential. In addition, the frame period of the reflective display panel 100 may be 1/60 seconds, but is not limited thereto, or the frame period of the reflective display panel 100 may be adjustable.
In addition, as shown in fig. 11B, in the j-th frame or (j +1) -th frame, the potentials of the scan lines S (1) and S (3) are first switched from the low potential to the high potential, then the potentials of the scan lines S (1) and S (3) are switched from the high potential to the low potential, and the potentials of the scan lines S (2) and S (4) are switched from the low potential to the high potential, then the potentials of the scan lines S (2) and S (4) are switched from the high potential to the low potential, and the potentials of the scan lines S (3) and S (5) are switched from the low potential to the high potential, and so on until the potentials of all the scan lines return to the low potential.
Further, the reflective display panel 100 also has a stress (stress) removing function to reduce the leakage current of the thin film transistor and reduce the trimming power consumption of the reflective display panel 100. The reflective display panel 100 may perform a stress relieving operation during a specific frame. As shown in fig. 11C, the k-th frame includes a data writing period and a stress relief period. In the data writing period, the high-low potential switching timing of the scan lines S (1), S (2) … is similar to the high-low potential switching timing of the scan lines S (1), S (2) … in the j-th frame or (j +1) th frame shown in fig. 11B, and in the stress relieving period, the pulse signals are generated by the scan lines S (2x-1), S (2x +2), and then the pulse signals (x is an odd number) are generated by the scan lines S (2x +1), S (2x +2) to reduce the negative bias stress of the gate transistor of each sub-pixel on the gate. It should be noted that the pulse signals generated by the scanning lines S (2x-1) and S (2x) do not overlap with the pulse signals generated by the scanning lines S (2x +1) and S (2x +2) in timing. In the (k +1) th frame, the reflective display panel 100 does not perform the stress relieving operation, and the high-low potential switching timing of the scan lines S (1) and S (2) … is substantially the same as the high-low potential switching timing of the scan lines S (1) and S (2) … in the j-th frame or the (j +1) th frame shown in fig. 11B. The reflective display panel 100 may be periodically subjected to a stress relieving operation. That is, every several frames of the reflective display panel 100 include a data writing period and a stress relieving period. In some embodiments, the reflective display panel 100 performs the stress relieving operation every 4 seconds, i.e., every 4 seconds has a frame including a data writing period and a stress relieving period.
As can be seen from the above description, according to the embodiments of the present invention, the reflective display panel can avoid the display problems such as color spots and/or bright and dark stripes, so as to improve the image display quality.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.