CN112309995B - Ceramic tube shell of voltage regulator, packaging structure and manufacturing method thereof - Google Patents
Ceramic tube shell of voltage regulator, packaging structure and manufacturing method thereof Download PDFInfo
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- 239000000919 ceramic Substances 0.000 title claims abstract description 82
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000005070 sampling Methods 0.000 claims abstract description 40
- 230000003071 parasitic effect Effects 0.000 abstract description 43
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4817—Conductive parts for containers, e.g. caps
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- H—ELECTRICITY
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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Abstract
The invention relates to the field of integrated circuits, in particular to a voltage regulator ceramic tube shell, a packaging structure and a manufacturing method thereof. In order to achieve the purpose of improving the output voltage precision of the voltage regulator, the power output pin adopts a double bonding finger structure, a bonding pad at the back of the power output pin is connected with a first bonding finger and a second bonding finger, the back bonding pad is connected with the first bonding finger and the second bonding finger through two independent wiring channels inside a multilayer ceramic tube shell, the first bonding finger is bonded with the drain electrode output end of the power tube in the voltage regulator through a first binding wire, and the second bonding finger is bonded with the sampling end of a first feedback sampling resistor through a second binding wire. Compared with the common ceramic tube shell and packaging structure, the ceramic tube shell can effectively reduce the line loss on the output large current path and eliminate the parasitic resistance R of the ceramic tube shell C The influence on the load adjustment rate of the voltage regulator improves the output voltage precision of the voltage regulator.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuit packaging, in particular to a voltage regulator ceramic tube shell for improving the output voltage precision of a voltage regulator, a packaging structure and a manufacturing method thereof.
Background
The main packaging forms of the integrated circuit include plastic packaging, ceramic packaging, metal packaging and the like, the plastic packaging is the most widely used at present, and the plastic packaging is non-airtight packaging and is widely applied to the fields of consumption, communication and industry. However, in some high reliability applications, it is necessary to use hermetically sealed components, which prohibit the use of plastic packaged components, and ceramic packages or metal packages are required to replace plastic packages. The ceramic package mainly comprises a ceramic tube shell, a chip, binding wires and a cover plate.
The conventional ceramic package structure mainly comprises a multilayer ceramic body 11, a cavity 12, bonding fingers 13, a back pad 14 and wiring and via holes inside the multilayer ceramic body, as shown in fig. 1. Each bond finger is connected to the backside pad through wiring and vias inside the multilayer ceramic body. Tungsten paste is used for wiring and via holes between the multilayer ceramics, and parasitic resistance of the package is introduced. The parasitic resistance of the ceramic tube shell is an order of magnitude larger than the parasitic resistance of the frame of the plastic package, and the load adjustment rate of the voltage regulator can be greatly influenced in the process of replacing the plastic package with the ceramic package. Ceramic package parasitic resistance R due to slurry material and wiring width limitations C For chips such as voltage regulators, the variation of the load adjustment rate introduced by the package parasitic resistor is 50mV when the load current is 1A, and is 100mV when the load current is 2A, if the load current is larger, the influence on the load adjustment rate parameter is larger, and the output voltage precision of the voltage regulator is greatly reduced. Therefore, a new ceramic tube shell packaging structure design is needed to reduce the influence of the parasitic resistance of the common ceramic tube shell on the load adjustment rate parameter of the voltage regulator, and the problem of the reduction of the output voltage precision of the voltage regulator caused by adopting the common ceramic tube shell is solved.
Disclosure of Invention
Therefore, the main purpose of the invention is to reduce the influence of the parasitic resistance of the tube shell on the load adjustment rate and improve the output voltage precision of the voltage regulator.
The invention provides a voltage regulator ceramic tube shell, which comprises a multilayer ceramic tube shell body and is characterized in that a power output pin comprises a back bonding pad, a first bonding finger and a second bonding finger, wherein the back bonding pad is connected with the first bonding finger and the second bonding finger in a cavity of the multilayer ceramic tube shell, the back bonding pad is connected with the first bonding finger and the second bonding finger through two independent wiring channels in the multilayer ceramic tube shell body, the first bonding finger is used for being connected with a drain electrode output end of a power tube in the voltage regulator through a first binding wire, and the second bonding finger is used for being connected with a sampling end of a first feedback sampling resistor through a second binding wire.
Furthermore, the invention also provides a voltage regulator packaging structure, which comprises a multilayer ceramic body, a cavity, bonding fingers, a back bonding pad and wiring and a via hole inside the multilayer ceramic body, and is characterized in that a unit related to power output pin output comprises an error amplifier, a bias current module, a power tube, a first binding wire, a second binding wire, a first feedback sampling resistor and a second feedback sampling resistor; the non-inverting input end of the error amplifier is connected with a reference voltage, and the output end of the error amplifier is connected with the grid electrode of the power tube; the input voltage is input into a bias current module, and the bias current module provides bias current for the error amplifier; the source electrode of the power tube is connected with an input voltage; the non-sampling end of the first feedback sampling resistor is connected with the reverse input end of the error amplifier, and one end of the second feedback sampling resistor is connected with the reverse input end of the error amplifier, and the other end of the second feedback sampling resistor is grounded; the power output pin adopts a double bonding finger structure, a back bonding pad of the power output pin is connected with a first bonding finger and a second bonding finger in the cavity, the back bonding pad is connected with the first bonding finger and the second bonding finger through two independent wiring channels in the multilayer ceramic tube shell, the first bonding finger is bonded with the drain electrode output end of the power tube in the voltage regulator through a first binding wire, and the second bonding finger is bonded with the sampling end of the first feedback sampling resistor through a second binding wire.
Furthermore, the invention also provides a manufacturing method of the voltage regulator packaging ceramic tube shell, which comprises the following steps:
forming a power output pin back bonding pad on the back of the multilayer ceramic tube shell body;
and forming a multilayer wiring and a via inside the multilayer ceramic package body, wherein the multilayer wiring and the via comprise two independent wiring channels between the back bonding pad and the first bonding finger and the second bonding finger.
And forming a first bonding finger and a second bonding finger of the power output pin in the cavity of the multilayer ceramic tube body.
Further, the invention also provides a manufacturing method of the voltage regulator packaging structure, which comprises the following steps:
forming a power output pin back bonding pad on the back of the multilayer ceramic tube shell body;
and forming a multilayer wiring and a via inside the multilayer ceramic package body, wherein the multilayer wiring and the via comprise two independent wiring channels between the back bonding pad and the first bonding finger and the second bonding finger.
Forming a first bonding finger and a second bonding finger of a power output pin in a cavity of the multilayer ceramic tube body;
the drain electrode output end of the voltage regulator chip power tube is bonded with the first bonding finger through the first binding wire;
and bonding the first feedback sampling resistor sampling end in the voltage regulator with the second bonding finger through the second binding wire.
Advantageous effects
Compared with the common ceramic tube shell and packaging structure, the ceramic tube shell and packaging structure of the voltage regulator provided by the invention can effectively reduce the line loss on the output large current path and eliminate the parasitic resistance R of the ceramic tube shell C The influence on the load adjustment rate of the voltage regulator improves the output voltage precision of the voltage regulator.
Drawings
Fig. 1 is a diagram of a general ceramic package structure.
Fig. 2 is an equivalent circuit diagram of a common ceramic envelope voltage regulator.
Fig. 3 is a schematic diagram of the ceramic envelope and package of the voltage regulator of the present invention.
Fig. 4 is an equivalent circuit diagram of a ceramic package structure of a voltage regulator according to the present invention.
Fig. 5 is a three-dimensional comparative diagram of a common ceramic tube shell and a package structure of the voltage regulator, and a ceramic tube shell and a package structure of the voltage regulator, (a) is a three-dimensional diagram of a common ceramic tube shell and a package structure, and (b) is a three-dimensional diagram of a ceramic tube shell and a package structure of the voltage regulator.
Detailed Description
The double bonding finger ceramic package structure of the present invention will be described in detail with reference to the accompanying drawings.
Common ceramic tube shell packaging structure is shown in fig. 1 and fig. 5 (a), and the drain electrode output end V of the power tube Mp is O 15 and a first feedback sampling resistor R f1 Sampling end R F 16 are bonded to the same bonding finger (number 5) of the common ceramic envelope through the first binding wire b1 and the second binding wire b2, respectively. The equivalent circuit of the common ceramic shell-and-tube voltage regulator is shown in figure 2, and the chip part comprises a bias current I B Reference voltage V ref Error amplifier, power tube Mp first feedback sampling resistor R f1 And a second feedback sampling resistor R f2 The method comprises the steps of carrying out a first treatment on the surface of the The package part includes a parasitic resistance R of the first binding wire b1 b1 Parasitic resistance R of the second binding wire b2 b2 And parasitic resistance R of the tube shell C The method comprises the steps of carrying out a first treatment on the surface of the The circuit board part comprises a PCB parasitic resistor R P Output capacitance C O And load current I load . The specific connection relation is as follows: bias current I B One end is connected with an input voltage V IN The other end is connected with an error amplifier; reference voltage V ref The same-direction input end of the error amplifier is connected; first feedback sampling resistor R f1 A parasitic resistance R of a terminal connected with the second binding wire b2 b2 The other end is connected with the reverse input end of the error amplifier; second feedback sampling resistor R f2 One end of the input end is connected with the reverse input end of the error amplifier, and the other end of the input end is grounded; error amplifier output V G The PMOS power tube Mp grid is connected, the PMOS power tube source electrode is connected with the input voltage V IN The drain electrode of the PMOS power tube is connected with the parasitic resistor R of the first binding wire b1 b1 A non-bonding end; first binding wire b1 parasitic resistance R b1 Bonding terminal and parasitic resistance R of second binding wire b2 b2 The bonding ends are connected with the parasitic resistor R of the tube shell C Parasitic resistance R of tube shell C The other end is connected to the parasitic resistance R of the PCB P ，R P The other end is connected with a conveying deviceOutput capacitor C O And load current I load 。
From the equivalent circuit diagram connection relationship shown in fig. 2, we can derive:
V OUT ＝V S -(R c +R p )×I load (2)
from the formulas (1) and (2):
the load regulation parameter of the voltage regulator is defined as the variation of the output voltage along with the load current, so there is
ΔV OUT ＝(R c +R p )×ΔI load (4)
Therefore, the common ceramic shell packaging structure is adopted, and the variation of the output voltage along with the load current is influenced by the parasitic resistance R of the ceramic shell C And PCB parasitic resistance R P Influence.
The package structure for improving the output precision of the voltage regulator is shown in fig. 3 and 5 (b), wherein fig. 3 shows a top view and a bottom view of a ceramic tube shell and the package structure, and fig. 5 (b) shows a three-dimensional view of the ceramic tube shell and the package structure, the package structure adopts a double-bonding finger ceramic tube shell package structure, and a drain electrode output end V of a power tube Mp O 25 and a first feedback sampling resistor R f1 Sampling end R F 26 are bonded to two bonding fingers (numbered 5 and 5') by binding wire first binding wire b1, second binding wire b2, respectively. The equivalent circuit of the packaging structure for improving the output precision of the voltage regulator is shown in fig. 4, and the chip part comprises bias current I B Reference voltage V ref Error amplifier, power tube Mp first feedback sampling resistor R f1 And a second feedback sampling resistor R f2 The method comprises the steps of carrying out a first treatment on the surface of the The package part includes a parasitic resistance R of the first binding wire b1 b1 Mailing of the second binding wire b2Resistor R b2 Parasitic resistance R of first tube shell C1 Parasitic resistance R of the second tube shell C2 The method comprises the steps of carrying out a first treatment on the surface of the The circuit board part comprises a PCB parasitic resistor R P Output capacitance C O And load current I load . The specific connection relation is as follows: bias current I B One end is connected with an input voltage V IN The other end is connected with an error amplifier; reference voltage V ref The same-direction input end of the error amplifier is connected; first feedback sampling resistor R f1 A parasitic resistance R of a terminal connected with the second binding wire b2 b2 The other end is connected with the reverse input end of the error amplifier, and the second feedback sampling resistor R f2 One end of the input end is connected with the reverse input end of the error amplifier, and the other end of the input end is grounded; error amplifier output V G The PMOS power tube Mp grid is connected, the PMOS power tube source electrode is connected with the input voltage V IN The drain electrode of the PMOS power tube is connected with the parasitic resistor R of the first binding wire b1 b1 Parasitic resistance R of the first binding wire b1 b1 The bonding end is connected with the parasitic resistor R of the first tube shell C1 Parasitic resistance R of second binding wire b2 b2 The bonding end is connected with the parasitic resistor R of the second tube shell C2 First tube parasitic resistance R C1 And a second parasitic resistance R of the package C2 The other end (voltage is V) S ) Together connected to PCB parasitic resistance R P ，R P The other end is connected with an output capacitor C O And load current I load 。
From the equivalent circuit diagram connection relationship shown in fig. 4, we can derive:
V OUT ＝V S -R p ×I load (6)
from formulas (5) and (6):
the load regulation parameter of the voltage regulator is defined as the variation of the output voltage along with the load current, so there is
ΔV oUT ＝R p ×ΔI load (8)
Therefore, the variation of output voltage along with load current and the parasitic resistance R of the ceramic tube shell can be realized by adopting the packaging structure C Independently of the parasitic resistance R of the PCB P In relation, the parasitic resistance R of the ceramic envelope can be eliminated C The influence on the load adjustment rate of the voltage regulator greatly improves the output voltage precision of the voltage regulator.
Examples
Taking CLCC05 ceramic tube shell as an example, adopting a common ceramic tube shell packaging structure, and parasitic impedance R of the tube shell C 63mΩ, parasitic impedance R of PCB P When the load current is changed from no load to 2A, the change amount of the output voltage is 5mΩ:
ΔV OUT ＝(63mΩ+5mΩ)×2A＝136mV
taking CLCC05 ceramic tube shell as an example, the package structure of the invention is adopted, and the parasitic impedance R of the tube shell C1 And R is C2 61mΩ and 72mΩ, respectively, parasitic impedance R of PCB P When the load current is changed from no load to 2A, the change amount of the output voltage is 5mΩ:
ΔV OUT ＝5mΩ×2A＝10mV
the comparison can be achieved, the load adjustment rate of the packaging structure is irrelevant to the parasitic impedance of the tube shell, and the output voltage precision of the voltage regulator can be greatly improved.
The invention relates to a manufacturing method of a voltage regulator packaging ceramic tube shell, which comprises the following steps:
forming a power output pin back bonding pad on the back of the multilayer ceramic tube shell body;
and forming a multilayer wiring and a via inside the multilayer ceramic package body, wherein the multilayer wiring and the via comprise two independent wiring channels between the back bonding pad and the first bonding finger and the second bonding finger.
And forming a first bonding finger and a second bonding finger of the power output pin in the cavity of the multilayer ceramic tube body.
The manufacturing method of the voltage regulator packaging structure of the invention comprises the following steps:
forming a power output pin back bonding pad on the back of the multilayer ceramic tube shell body;
and forming a multilayer wiring and a via inside the multilayer ceramic package body, wherein the multilayer wiring and the via comprise two independent wiring channels between the back bonding pad and the first bonding finger and the second bonding finger.
Forming a first bonding finger and a second bonding finger of a power output pin in a cavity of the multilayer ceramic tube body;
the drain electrode output end of the voltage regulator chip power tube is bonded with the first bonding finger through the first binding wire;
and bonding the first feedback sampling resistor sampling end in the voltage regulator with the second bonding finger through the second binding wire.
The above embodiments are only preferred embodiments of the present invention, and are not intended to limit the present invention, but any modifications, equivalents, improvements, etc. within the principle of the idea of the present invention should be included in the scope of protection of the present invention.
Claims (4)
1. The utility model provides a voltage regulator pottery shell, includes multilayer ceramic shell body, its characterized in that power output pin includes a back pad, first bonding finger and second bonding finger in the multilayer ceramic shell cavity are connected to a back pad, link to each other through inside two independent wiring passageway of multilayer ceramic shell body between a back pad and first, the second bonding finger, first bonding finger is used for connecting the drain electrode output of the power tube in the voltage regulator through first wiring, the second bonding finger is used for connecting the sampling end of first feedback sampling resistance through the second wiring.
2. The voltage regulator packaging structure comprises a multilayer ceramic body, a cavity, bonding fingers, a back bonding pad and wiring and a via hole inside the multilayer ceramic body, and is characterized in that a unit related to output of a power output pin comprises an error amplifier, a bias current module, a power tube, a first binding wire, a second binding wire, a first feedback sampling resistor and a second feedback sampling resistor; the non-inverting input end of the error amplifier is connected with a reference voltage, and the output end of the error amplifier is connected with the grid electrode of the power tube; the input voltage is input into a bias current module, and the bias current module provides bias current for the error amplifier; the source electrode of the power tube is connected with an input voltage; the non-sampling end of the first feedback sampling resistor is connected with the reverse input end of the error amplifier, and one end of the second feedback sampling resistor is connected with the reverse input end of the error amplifier, and the other end of the second feedback sampling resistor is grounded; the power output pin adopts a double bonding finger structure, the power output pin comprises a back bonding pad, a first bonding finger and a second bonding finger, the back bonding pad is connected with the first bonding finger and the second bonding finger in the cavity, the back bonding pad is connected with the first bonding finger and the second bonding finger through two independent wiring channels in the multilayer ceramic tube shell, the first bonding finger is bonded with the drain electrode output end of the power tube in the voltage regulator through a first binding wire, and the second bonding finger is bonded with the sampling end of the first feedback sampling resistor through a second binding wire.
3. A method of manufacturing a voltage regulator ceramic package according to claim 1, comprising:
forming a back bonding pad of the power output pin on the back of the multilayer ceramic tube shell body;
forming a multilayer wiring and a via inside the multilayer ceramic package body, the multilayer wiring and the via including two independent wiring channels between the one back pad and the first and second bonding fingers;
and forming a first bonding finger and a second bonding finger of the power output pin in the cavity of the multilayer ceramic tube body.
4. A method of manufacturing the voltage regulator package of claim 2, comprising:
forming a back bonding pad of the power output pin on the back of the multilayer ceramic tube shell body;
forming a multilayer wiring and a via inside the multilayer ceramic package body, the multilayer wiring and the via including two independent wiring channels between the one back pad and the first and second bonding fingers;
forming a first bonding finger and a second bonding finger of a power output pin in a cavity of the multilayer ceramic tube body;
the drain electrode output end of the voltage regulator chip power tube is bonded with the first bonding finger through the first binding wire;
and bonding the first feedback sampling resistor sampling end in the voltage regulator with the second bonding finger through the second binding wire.
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| CN205792191U (en) * | 2016-05-31 | 2016-12-07 | 深圳市国微电子有限公司 | A kind of high-performance power supply module |
| CN107092296A (en) * | 2017-04-28 | 2017-08-25 | 成都华微电子科技有限公司 | A kind of fast transient response low-voltage difference adjustor |
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| US4310792A (en) * | 1978-06-30 | 1982-01-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor voltage regulator |
| KR100594872B1 (en) * | 2002-10-04 | 2006-06-30 | 롬 씨오.엘티디 | Semiconductor device having voltage feedback circuit therein, and electronic apparatus using the same |
| US20060097704A1 (en) * | 2004-11-05 | 2006-05-11 | Wetherill Associates, Inc. | Voltage regulator and method using substrate board with insulator layer and conductive traces |
| JP4885635B2 (en) * | 2006-07-25 | 2012-02-29 | ローム株式会社 | Semiconductor device |
| US7629711B2 (en) * | 2007-03-23 | 2009-12-08 | Freescale Semiconductor, Inc. | Load independent voltage regulator |
| JP5405785B2 (en) * | 2008-09-19 | 2014-02-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP2013004683A (en) * | 2011-06-15 | 2013-01-07 | Hiroshi Miyoshi | Power converter of printed board |
| CN202771297U (en) * | 2012-08-28 | 2013-03-06 | 无锡天和电子有限公司 | Installment structure for integrated low-dropout three-terminal regulator |
| US9564892B2 (en) * | 2015-03-06 | 2017-02-07 | Skyworks Solutions, Inc. | Apparatus and methods for radio frequency PIN diode switches |
| CN206595900U (en) * | 2017-03-28 | 2017-10-27 | 浙江云迪电气科技有限公司 | A kind of electric machine controller IGBT driving voltage mu balanced circuits |
| CN109270978B (en) * | 2017-07-18 | 2020-12-22 | 华润微电子（重庆）有限公司 | Low dropout linear voltage stabilizing circuit, voltage regulation rate compensation unit and method |
| CN107658270B (en) * | 2017-10-13 | 2020-06-30 | 中国电子科技集团公司第十三研究所 | Ceramic Cases for Power Converters |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205792191U (en) * | 2016-05-31 | 2016-12-07 | 深圳市国微电子有限公司 | A kind of high-performance power supply module |
| CN107092296A (en) * | 2017-04-28 | 2017-08-25 | 成都华微电子科技有限公司 | A kind of fast transient response low-voltage difference adjustor |
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