CN112327553B

CN112327553B - Array substrate, manufacturing method thereof and display device

Info

Publication number: CN112327553B
Application number: CN202011291186.2A
Authority: CN
Inventors: 李明娟
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2020-11-18
Filing date: 2020-11-18
Publication date: 2022-04-26
Anticipated expiration: 2040-11-18
Also published as: CN112327553A

Abstract

The application provides an array substrate, a manufacturing method thereof and a display device. The array substrate includes: a data line extending in a first direction; a scan line extending in a second direction intersecting the first direction; the pixel electrode is positioned in a region enclosed by the scanning line and the data line; and a thin film transistor electrically connected between the data line and the pixel electrode, wherein the thin film transistor includes: an active layer including a conductor region and a channel region connected, the conductor region being electrically connected to the data line, the channel region being electrically connected to the pixel electrode; and a gate electrode electrically connected to the scan line and disposed corresponding to the channel region.

Description

Array substrate, manufacturing method thereof and display device

Technical Field

The present disclosure relates to the field of display, and more particularly, to an array substrate, a method for manufacturing the same, and a display device.

Background

With the development of display technology, high-resolution displays are becoming one of the development trends in the display field. The resolution of existing displays is limited by various factors, and the development of high-resolution displays is a difficult problem.

Disclosure of Invention

In view of the foregoing, an object of the present invention is to provide an array substrate capable of improving resolution, a method for manufacturing the same, and a display device.

The application provides an array substrate, it includes:

a data line extending in a first direction;

a scan line extending in a second direction intersecting the first direction;

the pixel electrode is positioned in a region enclosed by the scanning line and the data line; and

a thin film transistor electrically connected between the data line and the pixel electrode, wherein the thin film transistor includes:

an active layer including a conductor region and a channel region connected, the conductor region being electrically connected to the data line, the channel region being electrically connected to the pixel electrode; and

and the grid electrode is electrically connected with the scanning line and is arranged corresponding to the channel region.

In one embodiment, an orthographic projection of the channel region on the plane of the gate completely covers the gate.

In one embodiment, the channel region is substantially triangular in shape.

In one embodiment, the conductor region has a substantially triangular shape, and the channel region and the conductor region have a common side, and an orthographic projection of the common side on the pixel electrode divides a top corner of the pixel electrode into two parts.

In one embodiment, the thin film transistor is a top gate type thin film transistor, the active layer has a first side and a second side opposite to the first side, the data line is located at the first side, the pixel electrode is located at the second side, and the pixel electrode is located between the active layer and the gate electrode.

In one embodiment, a first insulating layer is disposed between the conductor region and the data line, a first via hole is formed in the first insulating layer, the conductor region and the data line are electrically connected through the first via hole, a second insulating layer is disposed between the channel region and the pixel electrode, a second via hole is formed in the second insulating layer, and the pixel electrode and the channel region are electrically connected through the second via hole.

In one embodiment, the thin film transistor is a bottom gate thin film transistor, the active layer has a first side and a second side opposite to the first side, the gate electrode is located at the first side, the data line is located between the active layer and the gate electrode, and the pixel electrode is located at the second side.

In one embodiment, the first insulating layer is provided between the conductor region and the data line, a first via hole is formed in the first insulating layer, the conductor region is electrically connected to the data line via the first via hole, a second insulating layer is provided between the channel region and the pixel electrode, the second via hole is formed in the second insulating layer, and the pixel electrode is electrically connected to the channel region via the second via hole.

The application provides a manufacturing method of an array substrate, which comprises the following steps:

providing a substrate;

forming a data line, a semiconductor layer and a pixel electrode extending in a first direction on the substrate, the semiconductor layer being electrically connected to the data line and the pixel electrode;

doping the semiconductor layer to form a conductor region and a channel region which are connected, wherein the conductor region is electrically connected with the data line, and the channel region is electrically connected with the pixel electrode;

the array substrate manufacturing method further comprises: and forming a gate electrode disposed corresponding to the channel region and a scan line electrically connected to the gate electrode, the scan line extending in a second direction intersecting the first direction.

In one embodiment, the doping the semiconductor layer to form a conductor region and a channel region connected to each other, the conductor region being electrically connected to the data line, and the channel region being electrically connected to the pixel electrode includes:

and doping the semiconductor layer by taking the grid electrode as a shielding layer, so that the semiconductor layer shielded by the grid electrode forms a channel region, and the semiconductor layer not shielded by the grid electrode forms a conductor region.

The application provides a display device, which comprises the array substrate.

In one embodiment, the display device includes a liquid crystal display panel and a laser backlight source for providing a laser beam to the liquid crystal display panel, where the liquid crystal display panel includes the array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the color filter substrate and the array substrate.

The application provides an array substrate, it includes: a data line extending in a first direction; a scan line extending in a second direction intersecting the first direction; the pixel electrode is positioned in a region enclosed by the scanning line and the data line; and a thin film transistor electrically connected between the data line and the pixel electrode, wherein the thin film transistor includes: an active layer including a conductor region and a channel region connected, the conductor region being electrically connected to the data line, the channel region being electrically connected to the pixel electrode; and the grid electrode is electrically connected with the scanning line and is arranged corresponding to the channel region. The array substrate utilizes the conductor region of the active layer to be directly connected with the data line, and utilizes the channel region of the active layer to be directly connected with the pixel electrode, so that a source electrode and a drain electrode in the existing thin film transistor structure are omitted, the thin film transistor structure is simplified on the premise of realizing the switching function of the thin film transistor, the size of the thin film transistor is reduced, the size of a driving unit of the array substrate is reduced, and the resolution ratio is improved.

By using the array substrate, the size of a pixel unit can be reduced, and a high-resolution display device is obtained.

According to the manufacturing method of the array substrate, the array substrate with high resolution can be obtained.

Drawings

In order to more clearly illustrate the technical solutions in the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a top view of an array substrate provided in the present application.

Fig. 2 is a cross-sectional view of the array substrate provided by the present application along the line a-a of fig. 1.

Fig. 3 is a cross-sectional view of an array substrate of another structure provided in the present application, taken along the line a-a of fig. 1.

Fig. 4 is a schematic top view illustrating an active layer and a pixel electrode of the array substrate of fig. 1 according to the present application.

Fig. 5 is a flowchart of a method for manufacturing an array substrate according to the present application.

Fig. 6 is a flowchart of a method for manufacturing an array substrate according to another embodiment of the present disclosure.

Fig. 7 is a schematic structural diagram of a display device provided in the present application.

Detailed Description

The technical solution in the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any inventive step based on the embodiments in the present application, are within the scope of protection of the present application.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise the first and second features being directly adjacent or may comprise the first and second features being not in direct contact but in contact with each other by means of further features between them. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

Referring to fig. 1 and 2, an array substrate 10 is provided. The array substrate 10 may be used in a display device. The array substrate 10 includes a substrate 11 and the following elements disposed on the substrate 11: a data line DL extending in a first direction D1; a scanning line GL extending in a second direction D2 intersecting the first direction D1; a pixel electrode PX located in a region surrounded by the scanning line GL and the data line DL; and a thin film transistor 12 electrically connected between the data line DL and the pixel electrode PX. It is understood that the array substrate 10 includes a plurality of data lines DL disposed at intervals, and a plurality of scan lines GL disposed at intervals. The first direction D1 intersects the second direction D2. In some embodiments, the first direction D1 and the second direction D2 may also be perpendicular.

The thin film transistor 12 includes an active layer 121 and a gate electrode 122. The active layer 121 includes a conductor region 1211 and a channel region 1212 connected. The conductor region 1211 is electrically connected to the data line DL. The channel region 1212 is electrically connected to the pixel electrode PX. The gate electrode 122 is electrically connected to the scan line GL and disposed corresponding to the channel region 1212. Gate 122 serves as a switch to open and close channel region 1212. The conductor region 1211 conducts the channel region 1212 and the data line DL. The channel region 1212 turns on and off the electrical connection of the conductor region 1211 and the pixel electrode PX under the control of the gate electrode 122.

The active layer 121 has a first side 121a and a second side 121b opposite to the first side 121 a. The data line DL is positioned at the first side 121a of the active layer 121. The pixel electrode PX is positioned at the second side 121b of the active layer 121. In the present embodiment, the first side 121a is a lower side of the active layer 121, and the second side 121b is an upper side of the active layer 121. In other embodiments, the positions of the first side 121a and the second side 121b may be interchanged.

In one embodiment, thin film transistor 12 is a top gate thin film transistor. The gate electrode 122 is positioned on the second side 121b of the active layer 121. The pixel electrode PX is located between the active layer 121 and the gate electrode 122. The gate electrode 122 is located at the same layer as the scan line GL and is made of the same metal layer. The gate electrode 122 may be a protrusion protruding from the scan line GL. The shape of the gate 122 is not limited in this application. It may be a semi-elliptical shape as shown in fig. 1, or may be a rectangular, triangular, polygonal, or other irregular shape.

A first insulating layer 13 is disposed between the conductor region 1211 and the data line DL. A first via hole 13a is opened in the first insulating layer 13. The conductor region 1211 is electrically connected to the data line DL via the first via hole 13 a. Specifically, the conductor region 1211 may extend into the first via hole 13a to be electrically connected to the data line DL. A second insulating layer 14 is disposed between the channel region 1212 and the pixel electrode PX. The second insulating layer 14 has a second via 14a formed therein. The pixel electrode PX is electrically connected to the channel region 1212 via the second via hole 14 a. Specifically, the pixel electrode PX may extend into the second via hole 14a to be electrically connected with the channel region 1212. Further, a third insulating layer 15 is provided between the pixel electrode PX and the gate electrode 122.

It is to be understood that the present application does not limit the type of thin film transistor. Referring to fig. 3, in another embodiment, the thin film transistor 12 is a bottom gate thin film transistor 12.

The gate electrode 122 is positioned at the first side 121a of the active layer 121. The data line DL is located between the active layer 121 and the gate electrode 122. The gate electrode 122 is located at the same layer as the scan line GL and is made of the same metal layer. The pixel electrode PX is positioned at the second side 121b of the active layer 121.

A first insulating layer 13 is disposed between the conductor region 1211 and the data line DL. A first via hole 13a is opened in the first insulating layer 13. The conductor region 1211 is electrically connected to the data line DL via the first via hole 13 a. The conductor region 1211 extends into the first via hole 13a to be electrically connected to the data line DL. A second insulating layer 14 is disposed between the channel region 1212 and the pixel electrode PX. A second via 14a is opened in the second insulating layer 14. The pixel electrode PX is electrically connected to the channel region 1212 via the second via hole 14 a. Specifically, the pixel electrode PX extends into the second via hole 14a to be electrically connected to the channel region 1212. In addition, a third insulating layer 15 is disposed between the data line DL and the gate electrode 122.

It is understood that the array substrate 10 may further include a driving chip. The driving chip is electrically connected to the data lines DL and the scan lines GL and provides driving signals to the data lines DL and the scan lines GL. The working principle of the array substrate 10 is as follows: the driving chip supplies a data signal to the data line DL. The driving chip supplies a scan signal to the scan line GL. The gate electrode 122 is driven by the scan signal to make the channel region 1212 conduct the conductor region 1211 and the pixel electrode PX, so that the data signal is transmitted to the pixel electrode PX through the data line DL, the conductor region 1211 and the channel region 1212, thereby controlling the display.

With continued reference to fig. 1 and 2, in one embodiment, an orthogonal projection T1 of the channel region 1212 on the plane a of the gate 122 completely covers the gate 122. Thus, the pixel structure can be reduced while maintaining a better switching effect. Specifically, the gate 122 can be turned off tightly, thereby preventing light leakage. Specifically, the orthographic projection T1 of the channel region 1212 on the plane a of the gate 122 may be slightly larger than the gate 122. Further, the orthographic projection T1 of the channel region 1212 on the plane a of the scan line GL covers a segment of the scan line GL in the second direction D2. The "coverage" here may be either complete coverage or partial coverage. Thereby, the switching effect of the channel region 1212 may be enhanced.

In one embodiment, the gate 122 has a semi-elliptical shape and the channel region 1212 has a substantially triangular shape. Specifically, the bottom side of the channel region 1212 may be substantially parallel to the scan line GL. By substantially triangular is meant an approximate, non-standard triangle, which may also be polygonal, but with a triangular appearance.

The orthographic projection T2 of the conductor region 1211 on the plane B on which the data line DL is located covers a section of the data line DL in the first direction D1. Thereby, the electrical connection of the data line DL to the conductor region 1211 is facilitated.

Conductor region 1211 may have a generally triangular shape. So that the entire active layer 121 appears substantially triangular in plan view. By substantially triangular is meant an approximate, non-standard triangle, which may also be polygonal, but with a triangular appearance. With such an arrangement, the area of the active layer 121 can be reduced, and the light transmittance can be improved. In addition, the bottom side of the conductor region 1211 may be substantially parallel to the data line DL.

Referring to fig. 4, fig. 4 is a schematic top view of the active layer 121 and the pixel electrode PX of the array substrate 10. Specifically, the channel region 1212 and the conductor region 1211 have one common side L. The orthogonal projection of the common side L on the pixel electrode PX divides one top angle α of the pixel electrode PX into two parts.

The material of the channel region 1212 may comprise intrinsic semiconductor material and may also comprise doped semiconductor material. The intrinsic semiconductor material is, for example, amorphous silicon or polycrystalline silicon. The polysilicon may be low temperature polysilicon. Doped semiconductor materials, such as amorphous silicon or polysilicon, are doped with phosphorus or boron, etc. The doped semiconductor material has a higher conductivity. The material of the conductor region 1211 includes a conductor material. The conductor material may be a conductible semiconductor material, such as amorphous silicon or polysilicon. The polysilicon may be low temperature polysilicon. The method of conductimerization may be ion doping. The doping ions may be, for example, phosphorus or boron. It is to be understood that the materials of the channel region 1212 and the conductor region 1211 are not limited in this application as long as the conductor region 1211 comprises a conductor material and the channel region 1211 comprises a semiconductor material. In one embodiment, the material of the channel region 1212 may also include a lightly doped semiconductor material, and the material of the conductor region 1211 includes a conductor material formed of a heavily doped semiconductor material. Specifically, the channel region 1212 has a first doping concentration and the conductor region 1211 has a second doping concentration. The first doping concentration is less than the second doping concentration.

The gate electrode 122, the data line DL, and the scan line GL may be made of, for example, tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), a copper niobium (CuNb) alloy, or a laminate of copper (Cu) and molybdenum (Mo), a laminate of copper (Cu) and molybdenum titanium (MoTi), a laminate of copper (Cu) and titanium (Ti), a laminate of aluminum (Al) and molybdenum (Mo), a laminate of molybdenum (Mo) and tantalum (Ta), a laminate of molybdenum (Mo) and tungsten (W), or a laminate of molybdenum (Mo) -aluminum (Al) -molybdenum (Mo).

The material of the first insulating layer 13, the second insulating layer 14, and the third insulating layer 15 may be selected from silicon dioxide, nitrogen dioxide, silicon oxynitride, and a stack thereof.

The application also provides a manufacturing method of the array substrate, which can be used for manufacturing the array substrate.

Referring to fig. 1, fig. 2 and fig. 5 together, in one embodiment, a method for manufacturing an array substrate of the present application includes:

s1: a substrate 11 is provided, and a data line DL extending in a first direction D1 is formed on the substrate 11.

The data line DL may be formed by depositing a gate metal layer GM on the substrate 11, and patterning the gate metal layer GM by exposure, development, and etching to form the data line DL. It is understood that the data lines DL are a plurality of data lines DL disposed at intervals.

S2: a semiconductor layer SML is formed over the data line DL to electrically connect the semiconductor layer SML and the data line DL.

A step of forming a first insulating layer 13 over the data line DL is further included between steps S1 and S2. Step S2 includes opening a first via hole 13a in the first insulating layer 13, forming a semiconductor layer SML over the first insulating layer 13, and patterning the semiconductor layer SML. The semiconductor layer SML is electrically connected to the data line DL via the first via hole 13 a. Specifically, the semiconductor layer SML may extend into the first via hole 13a to be electrically connected to the data line DL.

S3: a pixel electrode PX is formed over the semiconductor layer SML, electrically connecting the pixel electrode PX and the semiconductor layer SML.

A step of forming the second insulating layer 14 over the semiconductor layer SML is further included between steps S2 and S3. Step S3 includes opening a second via hole 14a in the second insulating layer 14, and forming a pixel electrode PX over the second insulating layer 14, the pixel electrode PX being electrically connected to the data line DL via the second via hole 14 a. Specifically, the pixel electrode PX may extend into the second via hole 14a to be electrically connected to the semiconductor layer SML.

S4: a gate electrode 122 and a scan line GL electrically connected to the gate electrode 122 are formed over the pixel electrode PX. Here, the scan line GL extends in a second direction D2 intersecting the first direction D1, the pixel electrode PX is located in a region surrounded by the scan line GL and the data line DL, and the gate electrode 122 is disposed corresponding to the semiconductor layer SML. The first direction D1 intersects the second direction D2. In some embodiments, the first direction D1 and the second direction D2 may also be perpendicular.

A step of forming a third insulating layer 15 over the semiconductor layer SML is further included between steps S3 and S4. The method of forming the gate electrode 122 and the scan line GL may be to deposit a source and drain metal layer SDM on the third insulating layer 15, and form the gate electrode 122 and the scan line GL by patterning the source and drain metal layer SDM through exposure, development, and etching. It is understood that the scanning lines GL are a plurality of scanning lines GL arranged at intervals.

S5: the semiconductor layer SML is doped with the gate electrode 122 as a blocking layer, so that the channel region 1212 is formed in the semiconductor layer SML blocked by the gate electrode 122, and the conductor region 1211 is formed in the semiconductor layer SML not blocked by the gate electrode 122.

The semiconductor material comprises an intrinsic semiconductor material, such as amorphous silicon or polycrystalline silicon. The polysilicon may be low temperature polysilicon.

In another embodiment, after forming the second insulating layer 14 over the semiconductor layer SML between steps S02 and S03, the method may further include: the semiconductor is primarily doped through the second insulating layer 14 to increase the conductivity of the active layer 12. The preliminary doping is lightly doped, so that the material of the channel region 1212 may also include lightly doped semiconductor material, and the material of the conductor region 1211 includes conductor material formed of heavily doped semiconductor material. The doping ions may be, for example, phosphorus or boron. Specifically, the channel region 1212 has a first doping concentration and the conductor region 1211 has a second doping concentration. The first doping concentration is less than the second doping concentration.

Referring to fig. 1, 3 and 6 together, in another embodiment, a method for manufacturing an array substrate includes:

s21: a substrate 11 is provided, and a gate electrode 122 and a scan line GL electrically connected to the gate electrode 122 are formed on the substrate 11. Wherein the scanning line GL extends along the second direction D2.

The scan line GL may be formed by depositing a gate metal layer GM on the substrate 11, and patterning the gate metal layer GM by exposure, development and etching. It is understood that the scanning lines GL are a plurality of scanning lines GL arranged at intervals.

S22: the data line DL extending in the first direction D1 is formed above the scan line GL.

A step of forming the third insulating layer 15 over the scan line GL is further included between steps S21 and S22. The method of forming the data lines DL may be to deposit a source/drain metal layer SDM on the third insulating layer 15, and form the data lines DL by patterning the source/drain metal layer SDM through exposure, development, and etching. It is understood that the data lines DL are a plurality of data lines DL disposed at intervals.

S23: a semiconductor layer SML is formed over the data line DL to electrically connect the semiconductor layer SML and the data line DL.

A step of forming a first insulating layer 13 over the data line DL is further included between steps S22 and S23. Step S23 includes opening a first via hole 13a in the first insulating layer 13, forming a semiconductor layer SML over the first insulating layer 13, and patterning the semiconductor layer SML. The semiconductor layer SML is electrically connected to the data line DL via the first via hole 13 a. Specifically, the semiconductor layer SML may extend into the first via hole 13a to be electrically connected to the data line DL.

S24: a pixel electrode PX is formed over the semiconductor layer SML, electrically connecting the pixel electrode PX and the semiconductor layer SML.

A step of forming the second insulating layer 14 over the semiconductor layer SML is further included between steps S23 and S24. Step S003 includes opening a second via hole 14a in the second insulating layer 14, and forming a pixel electrode PX over the second insulating layer 14, the pixel electrode PX being electrically connected to the data line DL via the second via hole 14 a. Specifically, the pixel electrode PX may extend into the second via hole 14a to be electrically connected to the semiconductor layer SML.

S25: the semiconductor layer SML is doped with a shielding layer, so that the channel region 1212 is formed in the semiconductor layer SML corresponding to the gate electrode 122, and the conductor region 1211 is formed in the remaining semiconductor layer SML.

Further, the shape and material of the thin film transistor are described in detail in the foregoing embodiments, and the description thereof is omitted here.

It is to be understood that the above-described order for the steps of the method is for illustration only, and the steps of the method of the present invention are not limited to the order specifically described above unless specifically stated otherwise.

Referring to fig. 7, the present application further provides a display device 100. The electronic device according to various embodiments of the present invention may be at least one of a smart phone (smartphone), a tablet personal computer (tablet personal computer), a mobile phone (mobile phone), a video phone, an electronic book reader (e-book reader), a desktop computer (desktop PC), a laptop computer (laptop PC), a netbook computer (netbook computer), a workstation (workstation), a server, a personal digital assistant (personal digital assistant), a portable media player (portable multimedia player), an MP3 player, a mobile medical machine, a camera, a game machine, a digital camera, a car navigation device, an electronic billboard, an automatic teller machine, or a wearable device (wearable device).

In one embodiment, the display device 100 includes a liquid crystal display panel 1 and a laser backlight 2 for supplying a laser beam to the liquid crystal display panel 1.

The liquid crystal display panel 1 is not limited In the present application, and may be a Vertical electric Field type liquid crystal display panel, such as a Twisted Nematic (TN) type liquid crystal display panel, a Multi-domain Vertical Alignment (MVA) type liquid crystal display panel, or a horizontal electric Field type liquid crystal display panel, such as a Fringe Field Switching (FFS) type liquid crystal display panel or an In-Plane Switching (IPS) type liquid crystal display panel. .

The liquid crystal display panel 1 includes an array substrate 10 and a color filter substrate 20 which are oppositely disposed, and a liquid crystal layer 30 disposed between the array substrate 10 and the color filter substrate 20.

The operating principle of the display device 100 is as follows: the data line DL supplies a data signal to the conductor region 1211. The driving chip provides a scan signal to the scan line GL. The gate electrode 122 is driven by a scan signal to make the channel region 1212 electrically connect the conductor region 1211 and the pixel electrode PX. Thereby allowing the data signal to be transmitted to the pixel electrode PX through the conductor region 1211 and the channel region 1212. The data signal including high and low potentials is transmitted to the pixel electrode PX and a common electrode (not shown) to form a strong and weak electric field for deflecting the liquid crystal.

The size of the pixel unit of the liquid crystal display panel 1 can be 10 μm or less, and a high-resolution display device 100 can be obtained by incorporating a laser backlight.

By using the array substrate of the present application, the pixel unit size can be reduced, and a high-resolution display device 100 can be obtained.

The foregoing provides a detailed description of embodiments of the present application, and the principles and embodiments of the present application have been described herein using specific examples, which are presented solely to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. An array substrate, comprising:

a data line extending in a first direction;

a scan line extending in a second direction intersecting the first direction;

an active layer including a conductor region and a channel region connected, the conductor region being electrically connected to the data line, the channel region being electrically connected to the pixel electrode, the conductor region having a substantially triangular shape, the channel region and the conductor region having a common side, an orthographic projection of the common side on the pixel electrode dividing a vertex of the pixel electrode into two parts; and

2. The array substrate of claim 1, wherein an orthographic projection of the channel region on a plane of the gate completely covers the gate.

3. The array substrate of claim 2, wherein the channel region is substantially triangular.

4. The array substrate of claim 1, wherein the thin film transistor is a top gate type thin film transistor, the active layer has a first side and a second side opposite to the first side, the data line is located at the first side, the pixel electrode is located at the second side, and the pixel electrode is located between the active layer and the gate electrode.

5. The array substrate according to claim 1, wherein a first insulating layer is disposed between the conductor region and the data line, a first via hole is formed in the first insulating layer, the conductor region is electrically connected to the data line via the first via hole, a second insulating layer is disposed between the channel region and the pixel electrode, a second via hole is formed in the second insulating layer, and the pixel electrode is electrically connected to the channel region via the second via hole.

6. The array substrate of claim 1, wherein the thin film transistor is a bottom gate type thin film transistor, the active layer has a first side and a second side opposite to the first side, the gate electrode is located at the first side, the data line is located between the active layer and the gate electrode, and the pixel electrode is located at the second side.

7. The array substrate according to claim 6, wherein the first insulating layer is disposed between the conductor region and the data line, a first via hole is formed in the first insulating layer, the conductor region is electrically connected to the data line via the first via hole, a second insulating layer is disposed between the channel region and the pixel electrode, the second via hole is formed in the second insulating layer, and the pixel electrode is electrically connected to the channel region via the second via hole.

8. A manufacturing method of an array substrate comprises the following steps:

providing a substrate;

doping the semiconductor layer to form a conductor region and a channel region which are connected, wherein the conductor region is electrically connected with the data line, the channel region is electrically connected with the pixel electrode, the conductor region is in a roughly triangular shape, the channel region and the conductor region are provided with a common edge, and an orthographic projection of the common edge on the pixel electrode divides a vertex angle of the pixel electrode into two parts;

9. The method for manufacturing an array substrate according to claim 8, wherein:

the doping the semiconductor layer to form a conductor region and a channel region which are connected, wherein the conductor region is electrically connected with the data line, and the channel region is electrically connected with the pixel electrode, and the doping the semiconductor layer to form the conductor region and the channel region which are connected with the pixel electrode comprises the following steps:

10. A display device comprising the array substrate according to any one of claims 1 to 7.

11. The display device according to claim 10, wherein the display device comprises a liquid crystal display panel and a laser backlight source for providing a laser beam to the liquid crystal display panel, and the liquid crystal display panel comprises the array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the color filter substrate and the array substrate.