CN112365843B

CN112365843B - Pixel driving circuit and driving method thereof, display panel and device

Info

Publication number: CN112365843B
Application number: CN202011449289.7A
Authority: CN
Inventors: 曾冉冉; 张蒙蒙; 高娅娜; 周星耀
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2020-12-09
Filing date: 2020-12-09
Publication date: 2022-02-08
Anticipated expiration: 2040-12-09
Also published as: CN112365843A

Abstract

Embodiments of the present invention provide a pixel driving circuit and a driving method thereof, a display panel and a device, which relate to the field of display technology and are used to improve the screen shaking problem of the display panel. In the pixel driving circuit, the control terminal of the driving transistor is electrically connected to the first node, the first terminal is electrically connected to the second node; the second terminal is electrically connected to the third node, and the third node is electrically connected to the light-emitting element; the data writing module The control terminal is electrically connected to the first scanning signal terminal, the first terminal is electrically connected to the data signal terminal, and the second terminal is electrically connected to the second node; the first terminal of the voltage regulator module is electrically connected to the variable voltage terminal, and the second terminal is electrically connected to the variable voltage terminal. It is electrically connected to the first node; when the data voltage input at the data signal terminal is greater than the first preset voltage, the signal at the variable voltage terminal increases from the first reference voltage V ₀₁ to the first voltage V ₁ ; When the data voltage is lower than the first preset voltage, the signal at the variable voltage terminal decreases from the second reference voltage V ₀₂ to the second voltage V ₂ .

Description

Pixel driving circuit and driving method thereof, display panel and device

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of display, in particular to a pixel driving circuit, a driving method thereof, a display panel and a device.

[ background of the invention ]

An Organic Light Emitting Diode (OLED) display panel is becoming the mainstream display technology of displays such as mobile phones, televisions, computers, etc. because of its characteristics of self-luminescence, fast response, wide color gamut, large viewing angle, high brightness, etc.

Since the OLED belongs to a current driving device, when it emits light, it is necessary to control a driving transistor in a pixel driving circuit to supply a driving current to the OLED device to cause it to emit light. In the existing pixel driving circuit, the grid voltage of the driving transistor is unstable, so that the brightness of the OLED controlled by the driving transistor is unstable, and the OLED display panel has the screen shaking problem during display.

[ summary of the invention ]

In view of the above, embodiments of the present invention provide a pixel driving circuit, a driving method thereof, a display panel and a device, so as to improve the problem of screen shaking of an OLED display panel during displaying.

In one aspect, an embodiment of the present invention provides a pixel driving circuit, including:

the control end of the driving transistor is electrically connected with a first node, and the first end of the driving transistor is electrically connected with a second node; the second end of the driving transistor is electrically connected with a third node which is electrically connected with the light-emitting element;

the control end of the data writing module is electrically connected with the first scanning signal end, the first end of the data writing module is electrically connected with the data signal end, and the second end of the data writing module is electrically connected with the second node;

a first end of the voltage stabilizing module is electrically connected with the variable voltage end, and a second end of the voltage stabilizing module is electrically connected with the first node;

when the data voltage input by the data signal end is greater than a first preset voltage, the signal of the variable voltage end is from a first reference voltage V₀₁Increased to a first voltage V₁；

When the data voltage input by the data signal end is less than the first preset voltage, the signal of the variable voltage end is from a second reference voltage V₀₂Reduced to a second voltage V₂。

In another aspect, an embodiment of the present invention provides a driving method for a pixel driving circuit, where the pixel driving circuit includes:

the control end of the driving transistor is electrically connected with a first node, and the first end of the driving transistor is electrically connected with a second node; the second end of the driving transistor is electrically connected with a third node, the third node is electrically connected with the light-emitting element, and the driving transistor is used for generating light-emitting driving current;

the driving period of the pixel driving circuit comprises a data writing phase;

the driving method includes: in the data writing stage, the data writing module supplies the signal of the data signal terminal to the second node under the control of the signal of the first scanning signal terminal; when the data voltage input by the data signal end is greater than a first preset voltage, the signal of the variable voltage end is from a first reference voltage V₀₁Increased to a first voltage V₁(ii) a When the data voltage input by the data signal end is less than the first preset voltage, the signal of the variable voltage end is from a second reference voltage V₀₂Reduced to a second voltage V₂。

In another aspect, an embodiment of the present invention provides a display panel, including a light emitting element and the pixel driving circuit, where the light emitting element is electrically connected to the pixel driving circuit;

the display panel further comprises a voltage adjusting unit electrically connected with the variable voltage terminal, the voltage adjusting unit is used for outputting corresponding voltage to the variable voltage terminal according to the gray scale to be displayed of the light emitting element, wherein,

when the gray scale to be displayed is smaller than a first preset gray scale, the signal output by the voltage regulating unit is converted into a first reference voltage V₀₁Increased to a first voltage V₁；

When the gray scale to be displayed is larger than a first preset gray scale, the signal output by the voltage regulating unit is converted into a second reference voltage V₀₂Reduced to a second voltage V₂。

In another aspect, an embodiment of the present invention provides a driving method for a display panel, which is applied to the display panel, where the driving method includes:

receiving a gray scale to be displayed of the light-emitting element;

outputting a voltage to the variable voltage terminal according to a gray scale to be displayed of the light emitting element,

In another aspect, an embodiment of the present invention provides a display device, including the display panel described above.

According to the pixel driving circuit, the driving method thereof, the display panel and the device provided by the embodiment of the invention, the variable voltage end electrically connected with the first node is arranged in the pixel driving circuit, and the signal of the variable voltage end can be adjusted according to different data voltages input by the data signal end, so that the influence of film layer leakage current on the potential of the first node can be compensated and even eliminated. When the light-emitting element emits light, the potential of the first node can be kept stable, so that the light-emitting current of the light-emitting element is stable, and the change of the brightness of the light-emitting element is avoided. When the pixel driving circuit and the light-emitting element are applied to the display panel, the problem of screen shaking of the display panel can be avoided, and the display effect of the display panel is improved.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram illustrating brightness variation of a display panel displaying at 255 gray scales in the related art;

fig. 2 is a schematic diagram of a pixel driving circuit according to an embodiment of the invention;

FIG. 3 is a schematic diagram of another pixel driving circuit according to an embodiment of the present invention;

FIG. 4 is a diagram of a pixel driving circuit according to another embodiment of the present invention;

FIG. 5 is a diagram illustrating a pixel driving circuit according to another embodiment of the present invention;

FIG. 6 is a diagram of a pixel driving circuit according to another embodiment of the present invention;

FIG. 7 is a timing diagram illustrating the operation of the pixel driving circuit shown in FIG. 6;

FIG. 8 is a timing diagram illustrating another operation of the pixel driving circuit shown in FIG. 6;

FIG. 9 is a diagram of a pixel driving circuit according to another embodiment of the present invention;

FIG. 10 is a timing diagram illustrating the operation of the pixel driving circuit shown in FIG. 9;

FIG. 11 is a timing diagram illustrating another operation of the pixel driving circuit shown in FIG. 9;

fig. 12 is a schematic diagram of a display panel according to an embodiment of the invention;

FIG. 13 is a timing diagram illustrating operation of the display panel shown in FIG. 12;

FIG. 14 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 15 is a timing diagram illustrating an operation of the display panel shown in FIG. 14;

fig. 16 is a schematic diagram illustrating a driving method of a display panel according to an embodiment of the invention;

fig. 17 is a schematic diagram of a display device according to an embodiment of the present invention.

[ detailed description ] embodiments

For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that although the terms first, second, etc. may be used to describe the light emission control modules in the embodiments of the present invention, the light emission control modules should not be limited to these terms. These terms are only used to distinguish the light emission control modules from each other. For example, the first lighting control module may also be referred to as a second lighting control module, and similarly, the second lighting control module may also be referred to as a first lighting control module without departing from the scope of the embodiments of the present invention.

As described in the background section, the OLED has a problem of unstable luminance when emitting light in the related art. In the process of implementing the embodiment of the present invention, the inventors have studied and found that, in the working process of the pixel driving circuit, a Dielectric Layer (Inter Metal Dielectric, hereinafter abbreviated as IMD) and a Dielectric Layer (Inter Layer Dielectric, hereinafter abbreviated as ILD) near the gate of the driving transistor have a leakage problem, and the gate potential of the driving transistor is changed under the influence of the leakage at a stage when a stable gate potential needs to be maintained.

For example, when the display panel displays in a high gray scale, as shown in fig. 1, fig. 1 is a schematic diagram illustrating a luminance change of the display panel in a 255 gray scale in the related art, and it can be seen that the luminance of the display panel gradually decreases with time during a display time of one frame. Between two adjacent frames, the brightness jumps obviously, so that the screen shaking phenomenon is easily observed by human eyes. The inventors have found that the reason for this is that, during the display time of one frame, some high potential signals in the circuit, such as the power supply voltage signal PVDD, leak to the gate of the driving transistor, causing the gate potential of the driving transistor to become high, and thus the luminance to fade.

When the display panel displays in a low gray scale, there is a problem that the luminance of the display panel gradually becomes brighter. In this process, this occurs because some low potential signals in the circuit, such as the reference voltage signal Vref, leak to the gate of the driving transistor, causing the gate potential of the driving transistor to become low.

In view of the above, an embodiment of the present invention provides a pixel driving circuit, as shown in fig. 2, fig. 2 is a schematic diagram of a pixel driving circuit according to an embodiment of the present invention, and the pixel driving circuit 100 includes a driving transistor M0, a data writing module 10 and a voltage stabilizing module 20.

A control terminal of the driving transistor M0 is electrically connected to the first node N1, a first terminal of the driving transistor M0 is electrically connected to the second node N2, and a second terminal of the driving transistor M0 is electrically connected to the third node N3. The third node N3 is electrically connected to the light emitting element 200. In the embodiments of the present invention, the "electrical connection" may refer to a direct electrical connection, or may refer to an electrical connection through another component, such as a transistor.

In the embodiment of the present invention, the light Emitting element 200 may be an OLED, or may also be another current driving device such as a Quantum Light Emitting Diode (QLED).

The third node N3 may be electrically connected to the anode of the light emitting element 200. The cathode of the light emitting element 200 is electrically connected to the low power supply voltage terminal PVEE. The signal provided by the low voltage supply terminal PVEE is a constant low voltage signal, for example, the low voltage supply terminal PVEE can be a ground terminal.

The driving transistor M0 may control the magnitude of the current flowing through the light emitting element 200 such that the current flowing through the light emitting element 200 is related to the magnitude of the voltage applied to the first node N1.

The control terminal of the data writing module 10 is electrically connected to the first scan signal terminal S1, the first terminal of the data writing module 10 is electrically connected to the data signal terminal Vdata, and the second terminal of the data writing module 10 is electrically connected to the second node N2. The data writing module 10 is used for providing a data signal to the driving transistor M0.

A first terminal of the regulator module 20 is electrically connected to the variable voltage terminal Vnew, and a second terminal of the regulator module 20 is electrically connected to the first node N1. When the data voltage inputted from the data signal end Vdata is larger than the first preset voltage, the signal of the variable voltage end Vnew is from the first reference voltage V₀₁Increased to a first voltage V₁(ii) a When the data voltage inputted from the data signal end Vdata is less than the first preset voltage, the signal of the variable voltage end Vnew is from the second reference voltage V₀₂Reduced to a second voltage V₂。

The drive period of the pixel drive circuit includes a data write phase t 1. In operation of the pixel driving circuit, the above-mentioned operation of inputting the data voltage to the data signal terminal Vdata occurs in the data writing phase t1, in which the data writing module 10 supplies the signal of the data signal terminal Vdata to the second node N2 under the control of the signal of the first scan signal terminal S1. Meanwhile, it is determined whether the data voltage inputted from the data signal terminal Vdata is greater than a first predetermined voltage, and when the data voltage is greater than the first predetermined voltage, the light emitting element 200 electrically connected to the pixel driving circuit needs to display at a relatively low gray scale, and at this time, the signal of the variable voltage terminal Vnew is driven from the first reference voltage V₀₁Increased to a first voltage V₁。

In the embodiment of the invention, the first preset voltage can be adjusted according to different design requirements. For example, taking an 8-bit display as an example, each light emitting element in the display can represent 256 luminance levels, i.e., can display 256 gray levels of 0 to 255, and at this time, the first preset voltage can be a data voltage corresponding to a gray level value of 100. The light emitting element 200 electrically connected to the pixel driving circuit needs to display a relatively low gray scale, so that the signal of the variable voltage terminal Vnew changes from low to high. In this process, even if IMD or ILD leakage occurs, a low voltage signal in the circuit, such as the reference voltage signal Vref, leaks to the first node N1, resulting in a decrease in the potential of the first node N1. The signal setting of the variable voltage terminal Vnew can raise the potential of the first node N1 through the film leakage, compensate or even cancel the above-mentioned influence of the low voltage signal in the circuit on the potential of the first node N1, and maintain the potential of the first node N1 at the target potential when the light emitting element 200 displays in low gray scale, so that the light emitting element 200 can stably display in preset low gray scale.

When the data voltage inputted from the data signal terminal Vdata is smaller than the first predetermined voltage, i.e. the light emitting device 200 electrically connected to the pixel driving circuit 100 is required to display with relatively high gray scale, the signal of the variable voltage terminal Vnew is driven from the second reference voltage V₀₂Reduced to a second voltage V₂. That is, the signal at the variable voltage terminal Vnew is changed from low to high. In this process, even if IMD or ILD leakage occurs, high voltage signals in the circuit, such as the high power supply voltage PVDD, leak to the first node N1, resulting in an increase in the potential of the first node N1. The signal setting of the variable voltage terminal Vnew can pull down the potential of the first node N1 through the film leakage, compensate or even cancel the above-mentioned influence of the high voltage signal in the circuit on the potential of the first node N1, so that the potential of the first node N1 is maintained at the target potential when the light emitting device 200 displays at the high gray scale, and the light emitting device 200 can stably display at the preset high gray scale.

The pixel driving circuit 100 according to the embodiment of the invention can compensate or even eliminate the influence of the film leakage on the potential of the first node N1 by providing the variable voltage terminal Vnew electrically connected to the first node N1 therein and adjusting the signal of the variable voltage terminal Vnew according to the difference of the data voltage input from the data signal terminal Vdata. When the light emitting element 200 emits light, the potential of the first node N1 can be kept stable, and thus the light emitting current of the light emitting element 200 can be stabilized, thereby preventing the luminance from changing. When the pixel driving circuit 100 and the light emitting element 200 are applied to a display panel, the problem of screen shaking of the display panel can be avoided, and the display effect of the display panel can be improved.

Illustratively, the first reference voltage V is₀₁And a second reference voltage V₀₂The values of (A) may or may not be equal. A first reference voltage V₀₁And a first voltage V₁The absolute value of the difference between, and a second reference voltage V₀₂And a second voltage V₂The absolute values of the differences may be equal to or different from each other, which is not limited in the embodiment of the present invention.

Optionally, the pixel driving circuit according to the embodiment of the present invention further includes a first node reset module, where the first node reset module is configured to provide a reset signal to the first node N1.

The driving period of the pixel driving circuit further includes a reset period t0 before the data writing period t1, and the potential of the first node N1 is reset in the reset period t0 to eliminate the influence of the data signal written to the first node N1 in the previous driving period on the potential of the first node N1 in the current driving period.

When the first node reset block is disposed, for example, as shown in fig. 3, fig. 3 is a schematic diagram of another pixel driving circuit provided in the embodiment of the present invention, the control terminal of the first node reset block 30 may be electrically connected to the second scan signal terminal S2, the first terminal of the first node reset block 30 may be electrically connected to the reference voltage terminal Vref, and the second terminal of the first node reset block 30 may be electrically connected to the first node N1, where the reference voltage terminal Vref is used for providing the reset signal.

In the operation of the pixel driving circuit, during the reset period t0, the second scan signal terminal S2 is provided with a signal for turning on the first node reset module 30, so that the first node reset module 30 provides the signal of the reference voltage terminal Vref to the first node N1.

Illustratively, during the reset period t0, the voltage of the variable voltage terminal Vnew remains unchanged. For example, the voltage of the variable voltage terminal Vnew may be maintained at the first reference voltage V₀₁Or a second reference voltage V₀₂To avoid the influence on the reset of the first node N1, the potential of the first node N1 is kept stable during the reset phase.

Optionally, as shown in fig. 4, fig. 4 is a schematic diagram of another pixel driving circuit provided in the embodiment of the present invention, and in the embodiment of the present invention, a threshold capture module 40, a light emitting element resetting module 50, a first light emitting control module 61, and a second light emitting control module 62 may be further disposed in the pixel driving circuit 100.

The control terminal of the threshold capture module 40 is electrically connected to the third scan signal terminal S3, the first terminal of the threshold capture module 40 is electrically connected to the third node N3, and the second terminal of the threshold capture module 40 is electrically connected to the first node N1. The threshold grabbing module 40 is used to detect and self-compensate the threshold voltage of the driving transistor M0. The threshold grasping module 40 is configured to make the light emitting current of the light emitting element 200 independent of the threshold voltage of the driving transistor M0. When a plurality of pixel driving circuits are used for forming a plurality of sub-pixels in a display panel, the threshold capture module 40 is arranged, so that the problems of display unevenness caused by the difference of the threshold voltage of the driving transistor M0 due to the manufacturing process, the threshold voltage drift caused by the aging of the driving transistor M0 and the like can be solved.

The control terminal of the light emitting element resetting module 50 is electrically connected to the fourth scan signal terminal S4, the first terminal of the light emitting element resetting module 50 is electrically connected to the reference voltage terminal Vref, and the second terminal of the light emitting element resetting module 50 is electrically connected to the light emitting element 200.

A control end of the first light emitting control module 61 and a control end of the second light emitting control module 62 are electrically connected to the light emitting signal end E, a first end of the first light emitting control module 61 is electrically connected to the first power voltage end PVDD, and a second end of the first light emitting control module 61 is electrically connected to the second node N2; a first terminal of the second light emission control module 62 is electrically connected to the third node N3, and a second terminal of the second light emission control module 62 is electrically connected to the light emitting element 200. The first and second light

emission control modules

61 and 62 are used to control whether a driving current flows through the light emitting element 200.

In the reset phase t0, the light emitting device reset module 50 provides the light emitting device 200 with the signal of the reference voltage Vref under the control of the signal of the fourth scan signal terminal S4, so as to eliminate the influence of the voltage written into the light emitting device 200 in the previous driving period on the potential of the light emitting device 200 in the current driving period, and ensure that the light emitting device 200 can emit light with the preset current.

In the data write phase t1, the threshold capture module 40 provides the signal of the third node N3 to the first node N1 under the control of the signal of the third scan signal terminal S3.

The drive period of the pixel drive circuit further includes a light emission period t2 following the data writing period t 1.

In the lighting period t2, the first lighting control module 61 provides the signal of the first power voltage terminal PVDD to the second node N2 under the control of the signal of the lighting signal terminal E; the second light emission control module 62 supplies the signal of the third node N3 to the light emitting element 200 under the control of the signal of the light emission signal terminal E.

For example, as shown in fig. 5, fig. 5 is a schematic diagram of a pixel driving circuit according to another embodiment of the present invention, where the light-emitting signal terminal E includes a first light-emitting signal terminal E1 and a second light-emitting signal terminal E2; the control terminal of the first light-emitting control module 61 is electrically connected to the first light-emitting signal terminal E1, and the control terminal of the second light-emitting control module 62 is electrically connected to the second light-emitting signal terminal E2. In an embodiment of the present invention, the threshold grabbing module 40, the second light emitting control module 62 and the light emitting element resetting module 50 may be multiplexed as the first node resetting module 30.

Specifically, in the reset phase t0, the light emitting element resetting module 50 provides the signal of the reference voltage terminal Vref to the second terminal of the second light emitting control module 62 under the control of the signal of the fourth scan signal terminal S4; the second light emission control module 62 provides the signal of the second terminal of the second light emission control module E2 to the first terminal of the threshold grasping module 40 under the control of the signal of the second light emission control signal terminal E2; the threshold grabbing module 40 provides the signal of the first terminal of the threshold grabbing module 40 to the first node N1 to reset the first node N1 under the control of the signal of the third scan signal terminal S3.

With such an arrangement, on the basis of the normal reset of the first node N1, the path through which the reference signal terminal Vref leaks to the first node N1 can be reduced, which is more favorable for maintaining the potential stability of the first node N1 and ensuring the stability of the light emitting brightness of the light emitting device 200.

Illustratively, as shown in fig. 6, fig. 6 is a schematic diagram of another pixel driving circuit according to an embodiment of the present invention, and the first node reset module 30 includes a first transistor M1. The threshold grabbing module 40 comprises a second transistor M2. The first light emission control module 61 includes a third transistor M3; the second light emission control module 62 includes a fourth transistor M4; the data write module 10 includes a fifth transistor M5; the light emitting element resetting module 50 includes a sixth transistor M6.

Alternatively, the first transistor M1 and the second transistor M2 may be N-type transistors. When the signal at the second scan signal terminal S2 is at a high level, the first transistor M1 is turned on; when the signal of the second scan signal terminal S2 is at a low level, the first transistor M1 is turned off. When the signal at the third scan signal terminal S3 is at a high level, the second transistor M2 is turned on; when the signal of the third scan signal terminal S3 is at a low level, the second transistor M2 is turned off. The embodiment of the invention forms the first transistor M1 and the second transistor M2 by selecting N-type transistors, so that the first transistor M1 and the second transistor M2 have smaller leakage current, and the stability of the potential of a first node N1 electrically connected with the first transistor M1 and the second transistor M2 is more favorably maintained.

For example, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 may select P-type transistors. When the light emitting signal terminal E is at a low level, the third transistor M3 and the fourth transistor M4 are turned on; when the light emission signal terminal E is at a high level, the third transistor M3 and the fourth transistor M4 are turned off. When the signal at the first scan signal terminal S1 is at a low level, the fifth transistor M5 is turned on; when the signal of the first scan signal terminal S1 is at a high level, the fifth transistor M5 is turned off. When the signal at the fourth scan signal terminal S4 is at a low level, the sixth transistor M6 is turned on; when the signal of the fourth scan signal terminal S4 is at a low level, the sixth transistor M6 is turned off. In the embodiment of the invention, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are formed by selecting the P-type transistors, so that the turn-on speed of the transistors can be increased, and the transmission of corresponding signals is facilitated.

Optionally, as shown in fig. 6, the voltage regulator module 20 includes a capacitor Cst, where the capacitor Cst includes a first plate and a second plate, the first plate is electrically connected to the variable voltage terminal Vnew, and the second plate is electrically connected to the first node N1. Based on the characteristic of the capacitor Cst, when the voltage of the first plate of the capacitor Cst, which is connected to the variable voltage terminal Vnew, changes, the voltage of the second plate connected to the first node N1 also changes accordingly, and further, the influence of the leakage current on the potential of the first node N1 can be compensated by the change of the signal of the variable voltage terminal Vnew, so that the potential of the first node N1 is kept stable when the light emitting device 200 emits light.

The operation of the pixel driving circuit shown in fig. 6 is described below with reference to the timing diagram shown in fig. 7:

in the reset stage t0, a signal for turning on the first transistor M1 is supplied to the second scan signal terminal S2, a signal for turning on the sixth transistor M6 is supplied to the fourth scan signal terminal S4, a signal for turning off the fifth transistor M5 is supplied to the first scan signal terminal S1, a signal for turning off the second transistor M2 is supplied to the third scan signal terminal S3, and a signal for turning off the third transistor M3 and the fourth transistor M4 is supplied to the emission signal terminal E. The signal of the reference voltage terminal Vref is transmitted to the first node N1 and the anode of the light emitting element 200 through the turned-on first transistor M1 and sixth transistor M6, respectively. At this time, the potential of the first node N1 is the potential provided by the reference voltage terminal Vref, and is represented by N1 equal to Vref.

In the data writing phase t1, a signal for turning on the fifth transistor M5 is supplied to the first scan signal terminal S1, a signal for turning on the second transistor M2 is supplied to the third scan signal terminal S3, a signal for turning off the first transistor M1 is supplied to the second scan signal terminal S2, a signal for turning off the sixth transistor M6 is supplied to the fourth scan signal terminal S4, and a signal for turning off the third transistor M3 and the fourth transistor M4 is supplied to the light emission signal terminal E. The signal of the data signal terminal Vdata is transmitted to the second node N2 through the fifth transistor M5, and N2 is Vdata. In this process, the driving transistor M0 is turned on. When the potential of the first node N1 reaches Vdata- | Vth |, the driving transistor M0 is turned off, completing the threshold capture. Where Vth is the threshold voltage of the drive transistor. At this time, N1 ═ N3 ═ Vdata | Vth |.

In addition, in the data writing stage t1, the signal of the data signal terminal Vdata is determined, and when the data voltage inputted from the data signal terminal Vdata is greater than the first preset voltage, the signal of the variable voltage terminal Vnew is driven from the first reference voltage V₀₁Increased to a first voltage V₁(ii) a When the data voltage inputted from the data signal end Vdata is less than the first preset voltage, the signal of the variable voltage end Vnew is from the second reference voltage V₀₂Reduced to a second voltage V₂。

In the light-emitting period t2, a signal for turning on the third transistor M3 and the fourth transistor M4 is supplied to the light-emitting signal terminal E, a signal for turning off the fifth transistor M5 is supplied to the first scan signal terminal S1, a signal for turning off the first transistor M1 is supplied to the second scan signal terminal S2, a signal for turning off the second transistor M2 is supplied to the third scan signal terminal S3, a signal for turning off the sixth transistor M6 is supplied to the fourth scan signal terminal S4, and a current is supplied to the light-emitting element 200, so that the light-emitting element 200 emits light. At this time, N1 ═ Vdata | Vth |, and N2 ═ PVDD.

The current flowing through the light emitting element 200 is expressed as follows:

I＝kⅹ(Vsg-Vth)²＝kⅹ[PVDD-(Vdata-|Vth|)-Vth)]²＝kⅹ(PVDD-Vdata)²

where k is a proportionality constant determined by the structure and physical characteristics of the driving transistor M0.

It can be seen that the current flowing through the light emitting element 200 is independent of the threshold voltage of the driving transistor M0 at the time of light emission.

In the embodiment of the present invention, when the plurality of pixel driving circuits and the plurality of light emitting elements are used to form the display panel, the display panel can be operated in the low frequency display mode and the high frequency display mode in order to meet the display requirements of users for displaying different application scenarios of the product.

For example, when displaying a dynamic picture, the display panel may operate in a high frequency display mode with a refresh frequency greater than or equal to 60Hz, so as to improve the display effect of the display panel. When displaying a static picture, the display panel can be operated in a low-frequency display mode with a refresh frequency of 15Hz or 30Hz, and at this time, the power consumption of the display panel can be reduced. In particular, low frequency driving is generally used when the Display panel is used in an Always On Display (AOD) mode or an idle mode.

Illustratively, when the display panel is switched between the high-frequency display mode and the low-frequency display mode, the embodiment of the invention can provide an intermediate-frequency picture with a refreshing frequency between the high frequency and the low frequency as a transition to avoid the problem of visually observing flicker.

Fig. 7 is a timing diagram of a case where the refresh frequency of the display panel is 60Hz, in this case, the light-emitting period t2 of the pixel driving circuit is relatively short, the time required for the potential of the first node N1 to be maintained is also short, the influence of the leakage current on the stabilization of the potential of the first node N1 is weak, and the luminance change of the light-emitting element is not easily observed by human eyes. Therefore, in one driving period T of the pixel driving circuit_jIn addition, as shown in fig. 7, in the lighting period t2, the embodiment of the invention can make the voltage of the variable voltage terminal Vnew keep the first reference voltage V₀₁Or a second reference voltage V₀₂Is not changed until the next driving period T is entered_j+1Until phase t 1. With the arrangement, on the basis of ensuring the display effect, the voltage of the variable voltage end Vnew does not need to be adjusted frequently, and the power consumption of the pixel driving circuit can be reduced.

In FIG. 7, Vnew-1 denotes the light emitting element in the drive period T_jDisplay with relatively high gray scale in the driving period T_j+1Displaying with relatively low gray scale; vnew-2 denotes the light emitting element in the driving period T_jWith relatively low gray scale thereinDisplay, using T in the drive period_j+1Displaying with relatively high gray scale; vnew-3 denotes the light emitting element in the driving period T_jAnd a driving period T_j+1All displayed with relatively high gray scale; vnew-4 indicates that the light emitting element is in the driving period T_jAnd a driving period T_j+1All displayed at a relatively low gray level. Unless otherwise specified, like reference numerals are understood in the above description.

When the pixel driving circuit operates at a lower refresh frequency in the low frequency display mode, the potential of the first node N1 needs to be maintained for a longer time than in the high frequency display mode. Therefore, in the related art, in the low frequency mode, the degree of potential leakage of the first node N1 is also greater, and accordingly, the resulting luminance variation is more easily observed by human eyes, and the screen-shaking problem is more obvious.

Specifically, in the low-frequency display mode, the operation of the pixel driving circuit includes writing the sub-frame and holding the sub-frame in one driving period of the pixel driving circuit. In the write sub-frame, the pixel drive circuit is caused to sequentially perform the operations of the reset phase, the data write phase, and the light emission phase shown in fig. 7. In the retention sub-frame, the supply of the data signal to the pixel drive circuit is stopped. That is, in the process of keeping the sub-frame without data writing, the potential of the first node N1 is maintained, and thus the light emitting element is continuously turned on.

For example, one or more holding sub-frames may be set within one driving period of the pixel driving circuit, and the time for one holding sub-frame may be made the same as the time for one writing sub-frame. In the holding sub-frame, the signal timing of the emission control signal terminal E may be controlled to be the same as the timing at the time of writing the sub-frame, so that the corresponding light emitting element continues to emit light.

As shown in FIG. 8, FIG. 8 is another timing diagram of the pixel driving circuit shown in FIG. 6, wherein the refresh frequency of the pixel driving circuit is 15Hz, and the driving period T of the pixel driving circuit is one driving period T_jIn the pixel driving circuit, the working process comprises one writing sub-frame Z1 and three keeping sub-frames, namely Z2, Z3 and Z4.

In the write sub-frame Z1, the embodiment of the present invention may change the voltage of the variable voltage terminal Vnew in the data write phase t1 according to the rule shown in fig. 7, and in the hold sub-frame, the embodiment of the present invention may also change the voltage of the variable voltage terminal Vnew, and the switching frequency and the switching amplitude in the hold sub-frame are the same as those in the write sub-frame Z1.

When the display is driven at low frequency, the electric potential of the first node N1 can be compensated for many times by adopting the mode of the embodiment of the invention, so that the flicker phenomenon during the low-frequency driving can be improved, and the display effect is improved.

Illustratively, as shown in fig. 9, fig. 9 is a schematic diagram of another pixel driving circuit according to an embodiment of the present invention, and the threshold grabbing block 40 includes a second transistor M2. The first light emission control module 61 includes a third transistor M3; the second light emission control module 62 includes a fourth transistor M4; the data write module 10 includes a fifth transistor M5; the light emitting element resetting module 50 includes a sixth transistor M6.

The second transistor M2 may be an N-type transistor. The third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 may select P-type transistors. The voltage stabilizing module 20 includes a capacitor Cst including a first plate electrically connected to the variable voltage terminal Vnew and a second plate electrically connected to the first node N1.

The operation of the pixel driving circuit shown in fig. 9 is described below with reference to the timing chart shown in fig. 10:

in the reset stage t0, a signal for turning on the fourth transistor M4 is supplied to the second light-emitting signal terminal E2, a signal for turning on the third transistor M3 is supplied to the third scan signal terminal S3, a signal for turning on the sixth transistor M6 is supplied to the fourth scan signal terminal S4, a signal for turning off the third transistor M3 is supplied to the first light-emitting signal terminal E1, and a signal for turning off the fifth transistor M5 is supplied to the first scan signal terminal S1. The signal of the reference voltage terminal Vref is transmitted to the anode of the light emitting device 200 through the turned-on sixth transistor M6, and the middle first node N1 is transmitted through the turned-on fourth transistor M4 and the turned-on second transistor M2, where N1 is equal to N3 equal to Vref.

In the data write phase t1, a signal for turning on the fifth transistor M5 is supplied to the first scan signal terminal S1, a signal for turning on the second transistor M2 is supplied to the third scan signal terminal S3, a signal for turning off the sixth transistor M6 is supplied to the fourth scan signal terminal S4, a signal for turning off the third transistor M3 is supplied to the first light-emitting signal terminal E1, and a signal for turning off the fourth transistor M4 is supplied to the second light-emitting signal terminal E2. The signal of the data signal terminal Vdata is transmitted to the second node N2 through the fifth transistor M5, and N2 is Vdata. In this process, the driving transistor M0 is turned on. When the potential of the first node N1 reaches Vdata- | Vth |, the driving transistor M0 is turned off, completing the threshold capture. At this time, N1 ═ N3 ═ Vdata | Vth |.

In addition, in the data writing stage t1, the signal of the data signal terminal Vdata is determined, and when the data voltage inputted from the data signal terminal Vdata is greater than the first preset voltage, the signal of the variable voltage terminal Vnew is driven from the first reference voltage V₀₁Increased to a first voltage V₁(ii) a When the data voltage input from the data signal end Vdata is less than the first preset voltage, the signal Vnew of the variable voltage end Vnew is from the second reference voltage V₀₂Reduced to a second voltage V₂。

In the light-emitting period t2, a signal for turning on the third transistor M3 is supplied to the first light-emitting signal terminal E1, a signal for turning on the fourth transistor M4 is supplied to the second light-emitting signal terminal E2, a signal for turning off the fifth transistor M5 is supplied to the first scan signal terminal S1, a signal for turning off the second transistor M2 is supplied to the third scan signal terminal S3, a signal for turning off the sixth transistor M6 is supplied to the fourth scan signal terminal S4, and a current is supplied to the light-emitting element 200, so that the light-emitting element 200 emits light. At this time, N1 ═ Vdata | Vth |, and N2 ═ PVDD. The current flowing through the light emitting element 200 is represented as: i-kxx (PVDD-Vdata)²

It can be seen that, at the time of light emission, the current flowing through the light emitting element 200 is also independent of the threshold voltage of the driving transistor M0 based on the circuit shown in fig. 9.

Illustratively, as shown in fig. 10, a holding phase t11 and a pre-lighting phase t12 are further provided between the data writing phase t1 and the lighting phase t 2.

In the holding period t11, a signal for turning on the fifth transistor M5 is supplied to the first scan signal terminal S1, a signal for turning off the third transistor M3 is supplied to the first light-emitting signal terminal E1, a signal for turning off the fourth transistor M4 is supplied to the second light-emitting signal terminal E2, a signal for turning off the second transistor M2 is supplied to the third scan signal terminal S3, and a signal for turning off the sixth transistor M6 is supplied to the fourth scan signal terminal S4. The potential of the first node N1 is kept at Vdata-Vth |; n2 ═ Vdata.

In the pre-emission period t12, a signal for turning on the third transistor M3 is supplied to the first emission signal terminal E1, a signal for turning off the fourth transistor M4 is supplied to the second emission signal terminal E2, a signal for turning off the fifth transistor M5 is supplied to the first scan signal terminal S1, a signal for turning off the second transistor M2 is supplied to the third scan signal terminal S3, and a signal for turning off the sixth transistor M6 is supplied to the fourth scan signal terminal S4. N2 ═ PVDD.

Fig. 10 is a timing diagram of a refresh frequency of 60Hz, in which the time of the light-emitting period t2 of the pixel driving circuit is relatively short, the time required for the potential of the first node N1 to be maintained is also short, the influence of the leakage current on the stabilization of the potential of the first node N1 is weak, and the luminance change of the light-emitting element is not easily observed by human eyes. Therefore, in one driving period T_jAs shown in fig. 10, the embodiment of the invention can make the voltage of the variable voltage terminal Vnew remain unchanged in the lighting period T2 until entering the next driving period T_j+1Until the data write phase in (1). With the arrangement, on the basis of ensuring the display effect, the voltage of the variable voltage end Vnew does not need to be adjusted frequently, and the power consumption of the pixel driving circuit can be reduced.

FIG. 11 is a schematic diagram of another operation timing sequence of the pixel driving circuit shown in FIG. 9, wherein the refresh frequency of the pixel driving circuit is 15Hz, and the refresh frequency is within one driving period T of the pixel driving circuit_jIn this embodiment, the operation of the pixel driving circuit includes one write sub-frame Z1 and three hold sub-frames Z2, Z3, and Z4.

In the write sub-frame Z1, the voltage of the variable voltage terminal Vnew may be changed according to the rule shown in fig. 10 in the data write phase t1, and in the hold sub-frame, the voltage of the variable voltage terminal Vnew may also be changed, and the switching frequency and the switching amplitude in the hold sub-frame are the same as those in the data write phase.

An embodiment of the present invention further provides a driving method for the pixel driving circuit, where the specific structure of the pixel driving circuit can be referred to the foregoing description, and is not repeated herein.

The drive period T of the pixel drive circuit includes a data write phase T1. The driving method comprises the following steps:

in the data writing phase t1, the data writing module 10 provides the signal of the data signal terminal Vdata to the second node N2 under the control of the signal of the first scan signal terminal S1; when the data voltage inputted from the data signal end Vdata is larger than the first preset voltage, the signal of the variable voltage end Vnew is from the first reference voltage V₀₁Increased to a first voltage V₁(ii) a When the data voltage inputted from the data signal end Vdata is less than the first preset voltage, the signal of the variable voltage end Vnew is from the second reference voltage V₀₂Reduced to a second voltage V₂。

According to the driving method of the pixel driving circuit provided by the embodiment of the invention, the variable voltage end Vnew electrically connected with the first node N1 is arranged in the pixel driving circuit, and the signal of the variable voltage end Vnew can be adjusted according to the difference of the data voltage input by the data signal end Vdata, so that the influence of film layer leakage current on the potential of the first node N1 can be compensated and even eliminated. When the light emitting element 200 emits light, the potential of the first node N1 can be kept stable, and thus the light emitting current of the light emitting element 200 can be stabilized, thereby preventing the luminance from changing. When the pixel driving circuit and the light-emitting element are applied to the display panel, the problem of screen shaking of the display panel can be avoided, and the display effect of the display panel is improved.

Illustratively, the pixel driving circuit 100 further includes a first node reset module. The drive cycle of the pixel drive circuit further includes a reset phase t0 preceding the data write phase t 1.

The driving method provided by the embodiment of the invention further comprises the following steps: in the reset phase t0, the first node reset module provides a signal of the reference voltage terminal Vref to the first node N1.

And, during the reset period t0, the voltage of the variable voltage terminal Vnew maintains the first reference voltage V₀₁Or a second reference voltage V₀₂And is not changed.

For example, as shown in fig. 3, the embodiment of the invention may electrically connect the control terminal of the first node reset module 30 to the second scan signal terminal S2, the first terminal of the first node reset module 30 to the reference voltage terminal Vref, and the second terminal of the first node reset module 30 to the first node N1.

Based on the structure shown in fig. 3, the driving method provided by the embodiment of the invention includes: during the reset period t0, the first node reset module 30 provides the signal of the reference voltage terminal Vref to the first node N1 under the control of the signal of the second scan signal terminal S2.

Optionally, as shown in fig. 4, in the embodiment of the present invention, a threshold grabbing module 40, a light emitting element resetting module 50, a first light emitting control module 61, and a second light emitting control module 62 may be further disposed in the pixel driving circuit.

Based on the structure shown in fig. 4, the driving method provided by the embodiment of the invention includes:

in the reset phase t0, the light emitting device reset module 50 provides the light emitting device 200 with the signal of the reference voltage terminal Vref under the control of the signal of the fourth scan signal terminal S4.

The driving method provided by the embodiment of the invention further comprises the following steps:

Illustratively, as shown in fig. 5, the light-emitting signal terminal E includes a first light-emitting signal terminal E1 and a second light-emitting signal terminal E2; the control terminal of the first light-emitting control module 61 is electrically connected to the first light-emitting signal terminal E1, and the control terminal of the second light-emitting control module 62 is electrically connected to the second light-emitting signal terminal E2. In an embodiment of the present invention, the threshold grabbing module 40, the second light emitting control module 62 and the light emitting element resetting module 50 may be multiplexed as the first node resetting module 30.

Based on the structure shown in fig. 5, the driving method provided by the embodiment of the present invention further includes: in the reset phase t0, the light emitting element reset module 50 provides a signal of the reference voltage terminal Vref to the second terminal of the second light emitting control module 62 under the control of the signal of the fourth scan signal terminal S4; the second light emission control module 62 provides the signal of the second terminal of the second light emission control module E2 to the first terminal of the threshold grasping module 40 under the control of the signal of the second light emission control signal terminal E2; the threshold grabbing module 40 provides the signal of the first terminal of the threshold grabbing module 40 to the first node N1 to reset the first node N1 under the control of the signal of the third scan signal terminal S3.

As shown in fig. 12, fig. 12 is a schematic view of a display panel provided in an embodiment of the present invention, and the display panel 1000 includes a plurality of sub-pixels 1. The sub-pixel 1 includes a light emitting element (not shown in fig. 9) and a pixel driving circuit (not shown in fig. 9) as described above, and the light emitting element is electrically connected to the pixel driving circuit.

The display panel 1000 further includes a voltage adjusting unit 52, and the voltage adjusting unit 52 is electrically connected to the variable voltage terminal Vnew of the corresponding sub-pixel 1. The voltage adjusting unit 52 is configured to output a corresponding voltage to the variable voltage terminal Vnew according to a gray scale to be displayed of the light emitting element.

When the display panel operates, the voltage adjusting unit 52 receives a gray scale to be displayed of the light emitting element, and outputs a voltage to the variable voltage terminal according to the gray scale to be displayed of the light emitting element.

Specifically, when the gray scale to be displayed is smaller than a first preset valueIn the case of gray scale, i.e., in the case where the sub-pixel 1 is displayed in low gray scale, the signal output from the voltage adjusting unit 52 is derived from the first reference voltage V₀₁Increased to a first voltage V₁。

When the gray scale to be displayed is larger than the first predetermined gray scale, i.e. when the sub-pixel 1 is displayed at a high gray scale, the signal outputted from the voltage adjusting unit 52 is outputted from the second reference voltage V₀₂Reduced to a second voltage V₂。

The display panel 1000 according to the embodiment of the present invention can compensate or even eliminate the effect of the film leakage current on the potential of the first node N1 in the pixel driving circuit of the sub-pixel by arranging the voltage adjusting unit 52 therein and making the signal output by the voltage adjusting unit 52 vary according to the gray scale to be displayed of the sub-pixel 1. When the light-emitting element emits light, the potential of the first node N1 can be kept stable, so that the light-emitting current of the light-emitting element is stable, the change of the brightness of the light-emitting element is avoided, the screen shaking problem of the display panel can be avoided, and the display effect of the display panel is favorably improved.

For example, as shown in fig. 12, when designing the display panel 1000, a plurality of sub-pixels 1 therein may be arranged in an array along a first direction x and a second direction y. The plurality of sub-pixels 1 are arranged in a sub-pixel row along a first direction x, and the plurality of sub-pixel rows are arranged along a second direction y. The plurality of sub-pixels 1 are arranged in a sub-pixel column along the second direction y, and the plurality of sub-pixel columns are arranged along the first direction x.

For example, in the display panel 1000 shown in fig. 12, the pixel driving circuit therein may be arranged with reference to the circuit structure shown in fig. 6. In order to drive the pixel driving circuit to operate, the display panel 1000 further includes a plurality of data lines 21, a plurality of first scanning signal lines 311, a plurality of second scanning signal lines 312, a plurality of third scanning signal lines 313, a plurality of fourth scanning signal lines 314, and a plurality of light emission control signal lines 41.

One of the data lines 21 is electrically connected to the data signal terminal Vdata in the same sub-pixel column. One first scanning signal line 311 is electrically connected to the first scanning signal terminal S1 in the same sub-pixel row, one second scanning signal line 312 is electrically connected to the second scanning signal terminal S2 in the same sub-pixel row, one third scanning signal line 313 is electrically connected to the third scanning signal terminal S3 in the same sub-pixel row, one fourth scanning signal line 314 is electrically connected to the fourth scanning signal terminal S4 in the same sub-pixel row, and one emission control signal line 41 is electrically connected to the emission control signal terminal E in the same sub-pixel row.

As shown in fig. 12, the display panel 1000 further includes a data driving circuit 22, a first scanning circuit 310, a second scanning circuit 320, a third scanning circuit 330, a fourth scanning circuit 340, and a light emission control circuit 42.

The data driving circuit 22 is electrically connected to the data lines 21. The first scanning circuit 310 is electrically connected to a plurality of first scanning signal lines 311. The second scan circuit 320 is electrically connected to the plurality of second scan signal lines 312. The third scan circuit 330 is electrically connected to the plurality of third scan signal lines 313. The fourth scan circuit 340 is electrically connected to the plurality of fourth scan signal lines 314. The light emission control circuit 42 is electrically connected to the plurality of light emission control signal lines 41.

When the display panel is operated, as shown in fig. 13, fig. 13 is a schematic diagram of an operation timing sequence of the display panel shown in fig. 12, and the driving chip drives the display panel to display frame by frame. And sequentially providing effective scanning signals to the plurality of sub-pixel rows within the display time of one frame of picture, and sequentially writing data into the corresponding sub-pixel rows under the control of the effective scanning signals so that the display panel normally displays each frame of picture. The order of providing the scan signals to the plurality of sub-pixel rows may be, for example, from top to bottom in fig. 12.

For example, the display process of each sub-pixel 1 in the display panel 1000 shown in fig. 12 in one frame of picture may sequentially perform the actions in the reset phase, the data writing phase and the light emitting phase shown in fig. 8. The effective scan signals may include a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a light emission control signal. In this process, the first scanning circuit 310 sequentially outputs a plurality of effective pulse signals to the plurality of first scanning signal lines 311; the second scanning circuit 320 sequentially outputs a plurality of effective pulse signals to a plurality of second scanning signal lines 321; the third scanning circuit 330 sequentially outputs a plurality of effective pulse signals to the plurality of third scanning signal lines 323; the fourth scanning circuit 340 sequentially outputs a plurality of effective pulse signals to the plurality of fourth scanning signal lines 324; the light emission control circuit 40 sequentially outputs a plurality of effective pulse signals to a plurality of light emission control signal lines 41.

In fig. 13, the signal output from the first scanning circuit 310 to the first scanning signal line 311 connected to the i-1 th sub-pixel row is S1_i-1Represents; the first scanning circuit 310 outputs a signal to the first scanning signal line 311 connected to the ith sub-pixel row at S1_iRepresents; the usage of the rest labels is similar, and is not repeated here.

For a plurality of sub-pixels in a display panel, the embodiment of the invention can independently control the voltage of the variable voltage terminal in different sub-pixels. That is, in the data writing stage of each sub-pixel, a signal is independently supplied to the variable voltage terminal connected to each sub-pixel according to the data voltage written to the corresponding sub-pixel.

Or, when the display panel operates in the pure gray scale display mode, the pure gray scale display mode refers to a mode in which all the sub-pixels in the display panel display in the same gray scale within the display time of one frame of picture. As shown in fig. 12, the embodiment of the present invention may connect the variable signal terminals of the plurality of sub-pixels in the display panel to the voltage adjusting unit 52 through the same variable voltage line 51, so as to reduce the number of the variable voltage lines.

Specifically, in the pure gray scale display mode, as shown in fig. 13, in the display time of one frame of picture, the embodiment of the present invention may enable the working process of the voltage adjusting unit 52 to include a plurality of stages, and enable each stage to include a voltage switching sub-stage and a voltage holding sub-stage. In the voltage switching sub-phase, the signal output by the voltage adjusting unit 52 is changed, and in the voltage maintaining sub-phase, the voltage output by the voltage adjusting unit 52 is kept unchanged. Wherein the duration of the voltage switching sub-phase may be much smaller than the duration of the voltage holding sub-phase.

Specifically, when the display panel operates in the pure gray scale display mode, the receiving of the to-be-displayed gray scale of the light emitting element includes: and receiving the gray scales to be displayed of the light-emitting elements in the first sub-pixel row according to the scanning sequence of the sub-pixel rows within the display time of one frame of picture. With this arrangement, only the relative magnitude relationship between the to-be-displayed gray scale of the light emitting element in the first sub-pixel row and the first preset gray scale needs to be determined, so that the voltage adjusting unit 52 can output signals to the variable voltage terminals of the plurality of sub-pixel rows in the display panel according to the to-be-displayed gray scale of the light emitting element in the first sub-pixel row, thereby simplifying the working process of the display panel.

When the gray scale to be displayed of the light emitting elements in the first sub-pixel row is smaller than the first predetermined gray scale, as shown in fig. 13, in the ith voltage switching sub-stage, the signal output by the voltage adjusting unit 52 is from V_i-1Increase to V_i(ii) a In the ith voltage holding sub-phase, the signal output from the voltage regulating unit 52 is held at V_i。

When the gray scale to be displayed of the light emitting elements in the first sub-pixel row is larger than the first preset gray scale, the signal output by the voltage adjusting unit 52 is switched from V to V in the ith voltage switching sub-stage_i-1Is reduced to V_i(ii) a In the ith voltage holding sub-phase, the signal output from the voltage regulating unit 52 is held at V_i；

Wherein, V_i-1For the voltage regulating unit 52 in the i-1 st phase A_iVoltage holding sub-phase in_iThe output voltage of (1); in the display time of a frame of picture, the data writing of the ith sub-pixel row and the ith voltage switching sub-stage are carried out simultaneously; the reset phase of the (i + 1) th sub-pixel row and the ith voltage holding sub-phase are carried out simultaneously; wherein i is a positive integer.

Taking the ith sub-pixel row and the (i + 1) th sub-pixel row in the display panel as examples, in the data writing stage of the ith sub-pixel row, when displaying in high gray scale, the signal output by the voltage regulating unit 52 is made to be V_i-1Is reduced to V_iThen, the signal outputted from the voltage adjusting unit 52 is held at V_iThe data writing phase to the (i + 1) th sub-pixel row comes. At the i +1 st sonIn the data writing phase of the pixel row, the signal output by the voltage regulating unit 52 is enabled to be from V_iIs reduced to V_i+1. This change will cause the voltage at the first node N1 in the ith subpixel row and the first node N1 in the (i + 1) th subpixel row to both be pulled low. For each sub-pixel row, as the light-emitting time is prolonged, the high-voltage signal in the circuit continuously leaks to the first node N1, so that by making the signal of the variable voltage terminal connected to one sub-pixel row include a plurality of variation phases, the potential of the first node N1 of each sub-pixel row can be compensated for a plurality of times, which is more beneficial to maintaining the potential of the first node N1 in the light-emitting phase to be stable.

Furthermore, when the potential of the first node N1 of each sub-pixel row is compensated for a plurality of times, the embodiment of the present invention can shorten the compensation time by performing the ith voltage switching sub-phase simultaneously with the data writing of the ith sub-pixel row.

In addition, in the embodiment of the present invention, the ith voltage holding sub-phase and the reset phase of the (i + 1) th sub-pixel row are performed simultaneously, so that the potential of the first node N1 of each sub-pixel row can be kept stable in the reset phase.

For example, as shown in fig. 13, in order to shorten the display time of one frame of picture, the embodiment of the invention may enable the data writing phase of the ith sub-pixel row and the resetting phase of the (i + 1) th sub-pixel row to be performed simultaneously.

In FIG. 13, Vnew-1 indicates that the j frame of the display panel is a high gray scale frame, and the j +1 frame of the display panel is a low gray scale frame; vnew-2 indicates that the j frame picture of the display panel is a low gray scale picture, and the j +1 frame picture is a high gray scale picture; vnew-3 indicates that the j frame picture and the j +1 frame picture of the display panel are both high gray scale pictures; vnew-4 indicates that the j frame picture and the j +1 frame picture of the display panel are low gray scale pictures.

The operation timing chart of the display panel shown in fig. 13 can be regarded as that the display panel is driven at a high frequency. When the display panel 1000 shown in fig. 12 is driven at a low frequency, the operation of each sub-pixel row can be performed with reference to fig. 8, and only the data writing periods of different sub-pixel rows need to be staggered. The embodiments of the present invention are not described herein.

Exemplarily, as shown in fig. 14, fig. 14 is a schematic diagram of another display panel provided in the embodiment of the present invention, wherein the pixel driving circuit can be configured with reference to the circuit structure shown in fig. 9. In comparison with fig. 12, the display panel shown in fig. 14 includes a first light emission control circuit 411 and a second light emission control circuit 412. The second light emission control circuit 402, the third scan circuit 330, and the fourth scan circuit 340 therein may be multiplexed as a second scan circuit.

When the display panel operates, as shown in fig. 15, fig. 15 is a schematic diagram of an operation timing sequence of the display panel shown in fig. 14, and the driving chip drives the display panel to display frame by frame. And sequentially providing effective scanning signals to the plurality of sub-pixel rows within the display time of one frame of picture, and sequentially writing data into the corresponding sub-pixel rows under the control of the effective scanning signals so that the display panel normally displays each frame of picture. The order of providing the scan signals to the plurality of sub-pixel rows may be, for example, from top to bottom in fig. 14.

For example, the display process of each sub-pixel 1 in the display panel 1000 shown in fig. 14 in one frame of picture may sequentially perform the actions in the reset phase, the data writing phase and the light emitting phase shown in fig. 10. The effective scan signal may include a first scan signal, a third scan signal, a fourth scan signal, and a light emission control signal.

When the display panel operates in the pure gray scale display mode, as shown in fig. 14, the embodiment of the invention can connect the variable signal terminals of the plurality of sub-pixels in the display panel to the voltage adjusting unit 52 through the same variable voltage line 51, so as to reduce the number of the variable voltage lines. In the pure gray scale display mode, as shown in fig. 15, during the display time of one frame of picture, the embodiment of the invention may make the working process of the voltage adjusting unit 52 include a plurality of stages, and make each stage include a voltage switching sub-stage and a voltage holding sub-stage. In the voltage switching sub-phase, the signal output by the voltage adjusting unit 52 is changed, and in the voltage maintaining sub-phase, the voltage output by the voltage adjusting unit 52 is kept unchanged. Wherein the duration of the voltage switching sub-phase may be much smaller than the duration of the voltage holding sub-phase.

Specifically, when the display panel operates in the pure gray scale display mode, the receiving of the to-be-displayed gray scale of the light emitting element includes: and receiving the gray scales to be displayed of the light-emitting elements in the first sub-pixel row according to the scanning sequence of the sub-pixel rows within the display time of one frame of picture.

When the gray scale to be displayed of the light emitting elements in the first sub-pixel row is smaller than the first predetermined gray scale, as shown in fig. 15, in the ith voltage switching sub-stage, the signal output by the voltage adjusting unit 52 is from V_i-1Increase to V_i(ii) a In the ith voltage holding sub-phase, the signal output by the voltage regulating unit is held at V_i。

In the display time of a frame of picture, the data writing of the ith sub-pixel row and the ith voltage switching sub-stage are carried out simultaneously; the reset phase of the (i + 1) th sub-pixel row is performed simultaneously with the ith voltage holding sub-phase.

In FIG. 15, Vnew-1 indicates that the j frame of the display panel is a high gray scale frame, and the j +1 frame of the display panel is a low gray scale frame; vnew-2 indicates that the j frame picture of the display panel is a low gray scale picture, and the j +1 frame picture is a high gray scale picture; vnew-3 indicates that the j frame picture and the j +1 frame picture of the display panel are both high gray scale pictures; vnew-4 indicates that the j frame picture and the j +1 frame picture of the display panel are low gray scale pictures.

The operation timing chart of the display panel shown in fig. 15 can be regarded as that the display panel is driven at a high frequency. When the display panel 1000 shown in fig. 14 is driven at a low frequency, the operation of each sub-pixel row can be performed with reference to fig. 11, and only the data writing periods of different sub-pixel rows need to be shifted from each other. The embodiments of the present invention are not described herein.

An embodiment of the present invention further provides a driving method of a display panel, as shown in fig. 16, fig. 16 is a schematic diagram of the driving method of the display panel provided in the embodiment of the present invention, the driving method is applied to the display panel, and the driving method includes:

step S1: receiving the gray scale to be displayed of the light-emitting element.

Step S2: outputting a voltage to a variable voltage end Vnew according to the gray scale to be displayed of the light emitting element, wherein when the gray scale to be displayed is smaller than a first preset gray scale, the signal output by the voltage regulating unit is from a first reference voltage V₀₁Increased to a first voltage V₁(ii) a When the gray scale to be displayed is larger than the first preset gray scale, the signal output by the voltage regulating unit is converted into a second reference voltage V₀₂Reduced to a second voltage V₂。

Illustratively, as shown in fig. 12 and 14, the display panel 1000 includes a plurality of sub-pixel rows, the sub-pixel rows including a plurality of sub-pixels 1 arranged along a first direction x, and the sub-pixel rows arranged along a second direction y.

As shown in fig. 12 and 14, the display panel 1000 further includes a variable voltage line 51, and the voltage adjusting unit 52 is electrically connected to the plurality of sub-pixel rows through the variable voltage line 51.

The display modes of the display panel comprise a pure gray scale display mode; in the pure gray scale display mode, the driving method comprises the following steps:

and sequentially providing effective scanning signals to a plurality of sub-pixel rows within the display time of one frame of picture, and sequentially writing data into the corresponding sub-pixel rows under the control of the effective scanning signals.

The receiving of the to-be-displayed gray scale of the light emitting element in the step S1 includes:

receiving the gray scale to be displayed of the light-emitting elements in the first sub-pixel row according to the scanning sequence of the sub-pixel rows within the display time of a frame of picture;

as shown in fig. 13 and 15, in the pure gray scale display mode, the operation process of the voltage adjusting unit 52 includes a plurality of stages each including a voltage switching sub-stage and a voltage holding sub-stage within the display time of one frame of picture.

When the gray scale to be displayed of the light-emitting elements in the first sub-pixel row is smaller than the first preset gray scale, the signal output by the voltage regulating unit is switched from V to V in the ith voltage switching sub-stage_i-1Increase to V_i(ii) a In the ith voltage holding sub-phase, the signal output by the voltage regulating unit is held at V_i。

When the gray scale to be displayed of the light-emitting elements in the first sub-pixel row is larger than the first preset gray scale, in the ith voltage switching sub-stage, the signal output by the voltage regulating unit is from V_i-1Is reduced to V_i(ii) a In the ith voltage holding sub-phase, the signal output by the voltage regulating unit is held at V_i；

Wherein, V_i-1Maintaining the output voltage of the sub-stage for the voltage of the voltage regulating unit in the i-1 th stage;

in the display time of a frame of picture, the data writing of the ith sub-pixel row and the ith voltage switching sub-stage are carried out simultaneously; wherein i is a positive integer.

Illustratively, the display panel includes a low frequency display mode, as shown in fig. 8 and 11, in which the display process of one frame of picture includes writing the sub-frame Z1 and maintaining the sub-frames Z2, Z3, Z4.

The driving method comprises the following steps:

in write sub-frame Z1, sequentially providing effective scanning signals to a plurality of sub-pixel rows; each sub-pixel row is charged in turn.

In the holding subframes Z2, Z3, Z4, supply of the effective scanning signal to the sub pixel row is stopped.

In the embodiment of the present invention, as shown in fig. 8 and 11, the switching frequency and the switching amplitude of the signal output by the voltage adjusting unit are the same in the writing sub-frame and the holding sub-frame.

Fig. 17 is a schematic view of a display device according to an embodiment of the present invention, and the display device includes the display panel 1000 as described above. The specific structure of the display panel 1000 has been described in detail in the above embodiments, and is not described herein again. Of course, the display device shown in fig. 17 is only a schematic illustration, and the display device may be any electronic device having a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a television, and a smart wearable device such as a watch or a bracelet.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. The driving method of the display panel is characterized by being applied to the display panel, wherein the display panel comprises a plurality of sub-pixel rows, the sub-pixel rows comprise a plurality of sub-pixels arranged along a first direction, and the sub-pixel rows are arranged along a second direction; the sub-pixel comprises a light emitting element and a pixel driving circuit which are electrically connected; the pixel driving circuit comprises a driving transistor, a data writing module and a voltage stabilizing module, wherein the control end of the driving transistor is electrically connected with a first node, and the first end of the driving transistor is electrically connected with a second node; the second end of the driving transistor is electrically connected with a third node which is electrically connected with the light-emitting element; the control end of the data writing module is electrically connected with the first scanning signal end, the first end of the data writing module is electrically connected with the data signal end, and the second end of the data writing module is electrically connected with the second node; the first end of the voltage stabilizing module is electrically connected with the variable voltage end, and the second end of the voltage stabilizing module is electrically connected with the first node; the display panel further comprises a voltage regulating unit, and the voltage regulating unit is electrically connected with the variable voltage end; the display panel further includes a variable voltage line through which the voltage adjusting unit is electrically connected to the plurality of sub-pixel rows;

the driving method includes:

receiving a gray scale to be displayed of the light-emitting element;

When the gray scale to be displayed is larger than a first preset gray scale, the signal output by the voltage regulating unit is converted into a second reference voltage V₀₂Reduced to a second voltage V₂；

The display modes of the display panel comprise a pure gray scale display mode;

the driving method includes: sequentially providing effective scanning signals to a plurality of sub-pixel rows within the display time of one frame of picture, and sequentially writing data into the corresponding sub-pixel rows under the control of the effective scanning signals;

the receiving of the gray scale to be displayed of the light emitting element includes: receiving the gray scale to be displayed of the light-emitting elements in the first sub-pixel row according to the scanning sequence of the sub-pixel rows within the display time of a frame of picture;

in the pure gray scale display mode, within the display time of a frame of picture, the working process of the voltage regulating unit comprises a plurality of stages, and each stage comprises a voltage switching sub-stage and a voltage holding sub-stage;

when the gray scale to be displayed of the light-emitting elements in the first sub-pixel row is smaller than a first preset gray scale, in the ith voltage switching sub-stage, the signal output by the voltage regulating unit is from V_i-1Is reduced to V_i(ii) a In the ith voltage holding sub-phase, the signal output by the voltage regulating unit is held at V_i；

When the gray scale to be displayed of the light-emitting elements in the first sub-pixel row is larger than a first preset gray scale, in the ith voltage switching sub-stage, the signal output by the voltage regulating unit is from V_i-1Increase to V_i(ii) a In the ith voltage holding sub-phase, the signal output by the voltage regulating unit is held at V_i；

Wherein, V_i-1Maintaining an output voltage of the sub-phase for the voltage of the voltage regulating unit in the i-1 th phase;

and, in the display time of a frame of picture, the data writing of the ith sub-pixel row and the ith voltage switching sub-stage are carried out simultaneously;

wherein i is a positive integer.

2. The driving method according to claim 1, wherein when the refresh frequency of the display panel is less than a preset frequency, the display process of one frame of picture comprises writing a sub-frame and maintaining the sub-frame;

sequentially providing effective scanning signals to a plurality of sub-pixel rows in the writing sub-frame;

stopping supplying effective scanning signals to the sub-pixel rows in the holding sub-frame;

the switching frequency and the switching amplitude of the signals output by the voltage regulating unit in the writing sub-frame and the maintaining sub-frame are the same.

3. A display panel for performing the driving method according to claim 1 or 2, the display panel comprising a plurality of sub-pixel rows, the sub-pixel rows comprising a plurality of sub-pixels arranged in a first direction, the plurality of sub-pixel rows being arranged in a second direction; the sub-pixel comprises a light emitting element and a pixel driving circuit which are electrically connected;

the pixel driving circuit comprises a driving transistor, a data writing module and a voltage stabilizing module, wherein the control end of the driving transistor is electrically connected with a first node, and the first end of the driving transistor is electrically connected with a second node; the second end of the driving transistor is electrically connected with a third node which is electrically connected with the light-emitting element; the control end of the data writing module is electrically connected with the first scanning signal end, the first end of the data writing module is electrically connected with the data signal end, and the second end of the data writing module is electrically connected with the second node;

the first end of the voltage stabilizing module is electrically connected with the variable voltage end, and the second end of the voltage stabilizing module is electrically connected with the first node; the display panel further comprises a voltage regulating unit, and the voltage regulating unit is electrically connected with the variable voltage end;

the display panel further includes a variable voltage line, and the voltage adjusting unit is electrically connected to the plurality of sub-pixel rows through the variable voltage line.

4. The display panel of claim 3, further comprising a first node reset module to provide a reset signal to the first node.

5. The display panel according to claim 4, wherein the control terminal of the first node reset module is electrically connected to the second scan signal terminal, the first terminal of the first node reset module is electrically connected to a reference voltage terminal, the second terminal of the first node reset module is electrically connected to the first node, and the reference voltage terminal is configured to provide a reset signal.

6. The display panel according to claim 5,

the first node reset module comprises a first transistor, and the first transistor is an N-type transistor.

7. The display panel according to claim 4, further comprising:

a control end of the threshold capturing module is electrically connected with a third scanning signal end, a first end of the threshold capturing module is electrically connected with the third node, and a second end of the threshold capturing module is electrically connected with the first node;

the control end of the light-emitting element resetting module is electrically connected with the fourth scanning signal end, the first end of the light-emitting element resetting module is electrically connected with the reference voltage end, and the second end of the light-emitting element resetting module is electrically connected with the light-emitting element;

the lighting control device comprises a first lighting control module and a second lighting control module; the control end of the first light-emitting control module and the control end of the second light-emitting control module are electrically connected with a light-emitting signal end, the first end of the first light-emitting control module is electrically connected with a first power voltage end, and the second end of the first light-emitting control module is electrically connected with the second node; the first end of the second light-emitting control module is electrically connected with the third node, and the second end of the second light-emitting control module is electrically connected with the light-emitting element.

8. The display panel according to claim 7, wherein the light-emitting signal terminal comprises a first light-emitting signal terminal and a second light-emitting signal terminal; the control end of the first light-emitting control module is electrically connected with the first light-emitting signal end, and the control end of the second light-emitting control module is electrically connected with the second light-emitting signal end.

9. The display panel according to claim 8,

the threshold grabbing module, the second light emitting control module and the light emitting element resetting module are multiplexed into the first node resetting module.

10. The display panel according to claim 7,

the threshold grabbing module comprises a second transistor which is an N-type transistor.

11. The display panel according to claim 3,

the voltage stabilizing module comprises a capacitor, the capacitor comprises a first polar plate and a second polar plate, the first polar plate is electrically connected with the variable voltage end, and the second polar plate is electrically connected with the first node.

12. A display device characterized by comprising the display panel according to any one of claims 3 to 11.