CN112397382B - Method for processing polycrystalline silicon thin film - Google Patents
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Abstract
本发明涉及一种多晶硅薄膜的处理方法和薄膜晶体管的制作方法,该多晶硅薄膜的处理方法包括:在所述多晶硅薄膜表面沉积无机膜层,使用刻蚀粒子对所述无机膜层远离所述多晶硅薄膜一侧表面进行刻蚀,能够减小多晶硅薄膜的表面粗糙度并能够避免刻蚀粒子对多晶硅薄膜造成损伤,从而能够减小使用该多晶硅薄膜作为有源层的薄膜晶体管的漏电流,进而使得将该薄膜晶体管应用于显示装置中时,能够有效提高显示装置的显示效果。
The invention relates to a method for processing a polysilicon film and a method for manufacturing a thin film transistor. The method for processing the polysilicon film includes: depositing an inorganic film on the surface of the polysilicon film, and using etching particles to keep the inorganic film away from the polysilicon Etching the surface of one side of the film can reduce the surface roughness of the polysilicon film and prevent the etching particles from causing damage to the polysilicon film, thereby reducing the leakage current of the thin film transistor using the polysilicon film as the active layer. When the thin film transistor is applied to a display device, the display effect of the display device can be effectively improved.
Description
技术领域technical field
本发明涉及显示领域,尤其涉及一种多晶硅薄膜的处理方法和薄膜晶体管的制作方法。The invention relates to the display field, in particular to a method for processing a polysilicon film and a method for manufacturing a thin film transistor.
背景技术Background technique
显示装置包括阵列基板,阵列基板上设置有薄膜晶体管,薄膜晶体管包括栅极、栅绝缘层、有源层、源极和漏极。由于多晶硅具有较高的电子迁移率,目前,薄膜晶体管的有源层的材质主要为多晶硅,以使薄膜晶体管具有较快的响应速度。The display device includes an array substrate on which a thin film transistor is arranged, and the thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain. Due to the high electron mobility of polysilicon, at present, the material of the active layer of the thin film transistor is mainly polysilicon, so that the thin film transistor has a faster response speed.
现有技术中,主要通过ELA(Excimer Laser Anneal,准分子激光退火)技术制备多晶硅薄膜,即先在衬底上形成非晶硅薄膜,然后再对非晶硅薄膜进行激光退火处理,使非晶硅薄膜转变为多晶硅薄膜。但是通过此种方式得到的薄膜晶体管的漏电流增大,最终影响显示装置的显示效果。In the prior art, the polycrystalline silicon thin film is mainly prepared by ELA (Excimer Laser Anneal, excimer laser annealing) technology, that is, an amorphous silicon thin film is first formed on the substrate, and then the amorphous silicon thin film is subjected to laser annealing treatment to make the amorphous silicon thin film The silicon film is transformed into a polysilicon film. However, the leakage current of the thin film transistor obtained in this way increases, which ultimately affects the display effect of the display device.
发明内容Contents of the invention
本发明的目的在于提供一种多晶硅薄膜的处理方法,能够有效减小薄膜晶体管的漏电流。The purpose of the present invention is to provide a method for processing polysilicon thin films, which can effectively reduce the leakage current of thin film transistors.
为达到上述目的,本发明提供一种多晶硅薄膜的处理方法,采用如下技术方案。In order to achieve the above purpose, the present invention provides a method for processing polysilicon thin films, which adopts the following technical solutions.
本发明实施例提供一种多晶硅薄膜的处理方法,包括:在所述多晶硅薄膜表面沉积无机膜层,使用刻蚀粒子对所述无机膜层远离所述多晶硅薄膜一侧表面进行刻蚀以去除所述无机膜层。An embodiment of the present invention provides a method for processing a polysilicon film, comprising: depositing an inorganic film layer on the surface of the polysilicon film, and using etching particles to etch the surface of the inorganic film layer away from the polysilicon film to remove the The inorganic film layer.
根据本发明实施例的一个方面,所述使用刻蚀粒子对所述无机膜层远离所述多晶硅薄膜一侧表面进行刻蚀的步骤包括:在解离设备中通入惰性气体和/或三氟化氮气体,解离所述惰性气体和/或所述三氟化氮气体形成等离子体;使用所述等离子体对所述无机膜层远离所述多晶硅薄膜一侧表面进行刻蚀。According to an aspect of an embodiment of the present invention, the step of using etching particles to etch the surface of the inorganic film layer away from the polysilicon film comprises: passing inert gas and/or trifluorine into the dissociation device Nitrogen gas, dissociating the inert gas and/or the nitrogen trifluoride gas to form plasma; using the plasma to etch the surface of the inorganic film layer away from the polysilicon film.
根据本发明实施例的一个方面,所述惰性气体为氩气;优选地,所述氩气的流量为15000sccm~25000sccm,和/或,所述三氟化氮气体的流量为20000sccm~25000sccm;优选地,所述氩气和所述三氟化氮气体的通入时间均为2s~12s。According to an aspect of the embodiment of the present invention, the inert gas is argon; preferably, the flow rate of the argon gas is 15000 sccm-25000 sccm, and/or the flow rate of the nitrogen trifluoride gas is 20000 sccm-25000 sccm; preferably Specifically, the feeding times of the argon gas and the nitrogen trifluoride gas are both 2s˜12s.
根据本发明实施例的一个方面,所述刻蚀的温度为230℃~430℃;优选地,所述刻蚀的时间为2s~12s。According to an aspect of the embodiments of the present invention, the etching temperature is 230°C-430°C; preferably, the etching time is 2s-12s.
根据本发明实施例的一个方面,所述使用刻蚀粒子对所述无机膜层远离所述多晶硅薄膜一侧表面进行刻蚀的步骤还包括:测量沉积所述无机膜层前所述多晶硅薄膜的最大表面粗糙度,所述最大表面粗糙度包括最大高度特征参数a和所述最大高度所对应的最大间距特征参数b;测量沉积所述无机膜层前所述多晶硅薄膜表面的平均表面粗糙度的平均高度特征参数c;测量所述多晶硅薄膜的多晶硅晶粒尺寸d;所述刻蚀粒子的运动轨迹和所述无机膜层远离所述多晶硅薄膜一侧表面的角度为θ且满足以下关系:arctan(c/d)≤θ≤arctan(a/b)。According to an aspect of an embodiment of the present invention, the step of using etching particles to etch the surface of the inorganic film layer away from the polysilicon film further includes: measuring the thickness of the polysilicon film before depositing the inorganic film layer. The maximum surface roughness, the maximum surface roughness includes the maximum height characteristic parameter a and the maximum distance characteristic parameter b corresponding to the maximum height; measure the average surface roughness of the polysilicon film surface before depositing the inorganic film layer The average height characteristic parameter c; measure the polysilicon grain size d of the polysilicon film; the trajectory of the etching particles and the angle of the surface of the inorganic film layer away from the polysilicon film side are θ and satisfy the following relationship: arctan (c/d)≤θ≤arctan(a/b).
根据本发明实施例的一个方面,在所述刻蚀结束后,使用氢氟酸溶液对所述无机膜层表面进行一次清洗。According to an aspect of the embodiments of the present invention, after the etching, the surface of the inorganic film layer is cleaned once with a hydrofluoric acid solution.
根据本发明实施例的一个方面,在所述一次清洗后,使用纯水对所述无机膜层表面进行二次清洗。According to an aspect of the embodiments of the present invention, after the primary cleaning, the surface of the inorganic film layer is cleaned a second time with pure water.
根据本发明实施例的一个方面,所述无机膜层的厚度为10~80nm。According to an aspect of the embodiments of the present invention, the thickness of the inorganic film layer is 10-80 nm.
根据本发明实施例的一个方面,所述无机膜层的材料为氧化硅、氮化硅中的至少一种。According to an aspect of the embodiments of the present invention, the material of the inorganic film layer is at least one of silicon oxide and silicon nitride.
进一步地,本发明还提供了一种薄膜晶体管的制作方法,该薄膜晶体管的制作方法包括:Further, the present invention also provides a method for manufacturing a thin film transistor, and the method for manufacturing a thin film transistor includes:
提供一基板;在所述基板上形成栅极、栅绝缘层、有源层、源极和漏极;其中,在所述基板上形成有源层的步骤包括:在所述基板上形成非晶硅薄膜;使用激光退火技术使所述非晶硅薄膜转变为多晶硅薄膜;使用以上所述的多晶硅薄膜处理方法对所述多晶硅薄膜进行处理;对处理后的所述多晶硅薄膜进行构图,形成包括所述有源层的图形。A substrate is provided; a gate, a gate insulating layer, an active layer, a source and a drain are formed on the substrate; wherein, the step of forming the active layer on the substrate includes: forming an amorphous Silicon film; using laser annealing technology to convert the amorphous silicon film into a polysilicon film; using the polysilicon film processing method described above to process the polysilicon film; patterning the processed polysilicon film to form a polysilicon film comprising the The pattern of the active layer described above.
由于在本发明提供的多晶硅薄膜的处理方法中,使用无机膜层覆盖多晶硅薄膜层后再利用刻蚀粒子对多晶硅薄膜进行刻蚀,能够减小多晶硅薄膜的表面粗糙度并能够避免刻蚀粒子对多晶硅薄膜造成损伤,从而能够减小使用该多晶硅薄膜作为有源层的薄膜晶体管的漏电流,进而使得将该薄膜晶体管应用于显示装置中时,能够有效提高显示装置的显示效果。Because in the processing method of the polysilicon thin film provided by the present invention, use etching particles to etch the polysilicon thin film after using the inorganic film layer to cover the polysilicon thin film layer, can reduce the surface roughness of the polysilicon thin film and can avoid the etching particle The polysilicon film causes damage, so that the leakage current of the thin film transistor using the polysilicon film as an active layer can be reduced, and the display effect of the display device can be effectively improved when the thin film transistor is applied to a display device.
附图说明Description of drawings
通过阅读以下参照附图对非限制性实施例所作的详细描述,本发明的其它特征、目的和优点将会变得更明显,其中,相同或相似的附图标记表示相同或相似的特征,附图并未按照实际的比例绘制。Other characteristics, objects and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, wherein the same or similar reference numerals represent the same or similar features, appended Figures are not drawn to scale.
图1示出根据本发明一种实施例提供的多晶硅薄膜处理方法示意图;1 shows a schematic diagram of a polysilicon film processing method provided according to an embodiment of the present invention;
图2示出根据本发明一种实施例提供的多晶硅薄膜处理方法流程图。Fig. 2 shows a flowchart of a method for processing a polysilicon thin film according to an embodiment of the present invention.
具体实施方式Detailed ways
下面将详细描述本发明的各个方面的特征和示例性实施例,为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及具体实施例,对本发明进行进一步详细描述。应理解,此处所描述的具体实施例仅被配置为解释本发明,并不被配置为限定本发明。对于本领域技术人员来说,本发明可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本发明的示例来提供对本发明更好的理解。The characteristics and exemplary embodiments of various aspects of the present invention will be described in detail below. In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only configured to explain the present invention, not to limit the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by showing examples of the present invention.
需要说明的是,在本文中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括……”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. any such actual relationship or order exists between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the statement "comprising..." does not exclude the presence of additional same elements in the process, method, article or device comprising said element.
应当理解,在描述部件的结构时,当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时,可以指直接位于另一层、另一个区域上面,或者在其与另一层、另一个区域之间还包含其它的层或区域。并且,如果将部件翻转,该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the part is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.
本申请的发明人发现,采用ELA技术制备多晶硅薄膜时,由于在非晶硅薄膜转变为多晶硅薄膜的过程中,形核中心最先固化,晶界处最后固化,且熔融硅与固态硅的密度具有差异,进而使得形成的多晶硅薄膜具有凸出的晶界,导致形成的多晶硅薄膜的表面粗糙度高。发明人进一步发现多晶硅薄膜的表面粗糙度越高,使用该多晶硅薄膜作为有源层的薄膜晶体管的漏电流越大,其中,表面粗糙度增加一倍,漏电流便会增加两个数量级。因此,当将通过GLA技术制备的多晶硅薄膜作为薄膜晶体管的有源层时,薄膜晶体管的漏电流大,显示装置的显示效果不佳。而现有技术中通过粒子刻蚀来降低多晶硅薄膜的表面粗糙度时容易损伤多晶硅晶粒,从而影响该多晶硅薄膜制成的晶体管的性能。The inventors of the present application have found that when using ELA technology to prepare polysilicon films, the nucleation centers solidify first and the grain boundaries solidify last during the process of transforming amorphous silicon films into polysilicon films, and the density of molten silicon and solid silicon There are differences, so that the formed polysilicon film has protruding grain boundaries, resulting in a high surface roughness of the formed polysilicon film. The inventors further found that the higher the surface roughness of the polysilicon film, the greater the leakage current of the thin film transistor using the polysilicon film as the active layer, wherein the leakage current increases by two orders of magnitude when the surface roughness is doubled. Therefore, when the polysilicon thin film prepared by GLA technology is used as the active layer of the thin film transistor, the leakage current of the thin film transistor is large, and the display effect of the display device is not good. However, in the prior art, when the surface roughness of the polysilicon film is reduced by particle etching, the polysilicon grains are easily damaged, thereby affecting the performance of the transistor made of the polysilicon film.
为了解决以上问题,本发明实施例提供了一种多晶硅薄膜的处理方法,以下将结合附图对各实施例进行说明。In order to solve the above problems, an embodiment of the present invention provides a method for processing a polysilicon thin film. The embodiments will be described below with reference to the accompanying drawings.
图1示出了本发明一种实施例提供的一种多晶硅薄膜的处理过程的示意图。如图1所示,本发明实施例提供的一种多晶硅薄膜的处理方法,该方法包括:在多晶硅薄膜1的表面沉积有无机膜层2。在未经过任何处理的情况下,晶硅薄膜1的表面具有凸出的晶界,导致多晶硅薄膜1的表面粗糙度较高,在多晶硅薄膜1表面沉积无机膜层2后,无机膜层2对应多晶硅表面凸起的部分厚度较小。在多晶硅薄膜1表面沉积无机膜层2后,通过刻蚀粒子对无机膜层2远离多晶硅薄膜1一侧的表面进行刻蚀以去除无机膜层2,蚀刻粒子首先刻蚀掉无机膜层2较薄的部分即对应多晶硅薄膜2表面凸起的部分后蚀刻粒子再刻蚀多晶硅薄膜1表面的凸起,随着刻蚀的进行,多晶硅薄膜表面的凸起和无机膜层2均被刻蚀掉,从而能够降低多晶硅薄膜1表面的粗糙度,同时由于无机膜层2的存在,蚀刻粒子首先对无机膜层2进行刻蚀,无法直接接触多晶硅薄膜1,能够避免蚀刻粒子对多晶硅晶体的损伤。FIG. 1 shows a schematic diagram of a polysilicon film processing process provided by an embodiment of the present invention. As shown in FIG. 1 , an embodiment of the present invention provides a method for processing a polysilicon thin film. The method includes: depositing an
具体地,无机膜层2的材料可以为氧化硅、氮化硅中的至少一种,在多晶硅薄膜1表面沉积无机材料时,氧化硅和/或氮化硅与多晶硅薄膜1的结合力较高,且密封性好,蚀刻粒子刻蚀时不易穿透氧化硅膜层和/或氮化硅膜层,从而能够避免多晶硅晶粒被蚀刻粒子损伤。Specifically, the material of the
可选地,无机膜层2的厚度为10nm-80nm。多晶硅晶粒的尺寸往往是在几百纳米到几微米之间,因此多晶硅薄膜1表面的凸起的尺寸往往在纳米级别或微米级别,因此无机膜层2的厚度在10nm-80nm时,其厚度不会超过多晶硅薄膜1表面凸起的高度,沉积无机膜层2后,多晶硅薄膜1表面的凸起高于无机膜层2的厚度,在蚀刻粒子进行刻蚀时,能够先刻蚀无机膜层2表面的凸起再刻蚀多晶硅薄膜层1表面的凸起,最终将无机膜层2和多晶硅薄膜1表面的凸起刻蚀完,从而降低多晶硅薄膜2的表面粗糙度,同时能够节约刻蚀的时间。Optionally, the thickness of the
附图2为本发明实施例处理多晶硅薄膜的流程图,步骤具体包括:Accompanying drawing 2 is the flow chart of the embodiment of the present invention processing polysilicon thin film, and step specifically comprises:
步骤S201:在多晶硅薄膜表面沉积无机膜层。可选地,通过化学气相沉积方式在多晶硅薄膜1表面沉积厚度在10nm-80nm的无机膜层2,无机膜层的材料可以为氧化硅和/或氮化硅。Step S201: Depositing an inorganic film layer on the surface of the polysilicon film. Optionally, an
步骤S202:在解离设备中通入惰性气体和/或三氟化氮气体。在本申请的一些实施例中,可在解离设备中单独通入惰性气体,该惰性气体可以为较为常用的氩气,以降低该多晶硅薄膜1的处理方法的成本,其中,通入的氩气的流量越大,对多晶硅薄膜1的刻蚀速度也越大,本发明实施例在综合考虑刻蚀速度和刻蚀均匀性后,优选氩气的流量为15000sccm~25000sccm,通气时间为2s~12s;在本申请的另一些实施例中,也可以在解离设备中单独通入三氟化氮气体,其中,通入的三氟化氮气体的流量越大,对多晶硅薄膜1的刻蚀速度也越大,在综合考虑刻蚀速度和刻蚀均匀性后,优选三氟化氮气体的流量为20000sccm~25000sccm,通气时间为2s~12s;在本申请的另一些实施例中,可在解离设备中同时通入惰性气体和三氟化氮气,惰性气体可以为氩气,优选氩气的流量为15000sccm~25000sccm,通气时间为2s~12s,三氟化氮气体的流量为20000sccm~25000sccm,通气时间为2s~12s。可选地,解离设备可以时化学气相沉积设备,也可以是电磁谐振腔,可以根据实际情况选择。Step S202: Inert gas and/or nitrogen trifluoride gas is introduced into the dissociation device. In some embodiments of the present application, an inert gas may be introduced into the dissociation device separately, and the inert gas may be the more commonly used argon gas, so as to reduce the cost of the processing method of the
步骤S203:解离惰性气体和/或三氟化氮气体,形成等离子体。可选地,解离惰性气体和/或三氟化氮气体的温度在230℃~430℃。其中惰性气体为氩气时,解离形成氩等离子体,使用氩等离子体对上述多晶硅薄膜进行轰击,通过物理轰击的形式将上述无机膜层2和多晶硅薄膜1表面的凸起击碎,从而降低多晶硅薄膜1的表面粗糙度;当使用三氟化氮气体作为解离时的气体时,能够解离形成氟等离子体,使用氟等离子体对上述多晶硅薄膜进行轰击时,氟等离子体能够与无机膜层2发生化学反应露出多晶硅薄膜表面的凸起,同时氟等离子体能够刻蚀多晶硅薄膜1表面上的凸起,从而降低多晶硅薄膜1表面的粗糙度。优选地,当被解离气体中同时包括氩气和三氟化氮气体时,能够同时产生氟等离子体和氩等离子体,对无机膜层2和多晶硅薄膜表面的凸起的蚀刻效果更好。Step S203: dissociate the inert gas and/or nitrogen trifluoride gas to form plasma. Optionally, the temperature for dissociating the inert gas and/or nitrogen trifluoride gas is between 230°C and 430°C. Wherein when the inert gas is argon, it dissociates to form argon plasma, and uses argon plasma to bombard the above-mentioned polysilicon film, and smashes the protrusions on the surface of the above-mentioned
步骤S204:使用等离子体对无机膜层远离多晶硅薄膜一侧表面进行刻蚀。可选地,在使用等离子体对无机膜层进行刻蚀时,刻蚀的温度为230℃~430℃,刻蚀的时间为2s~12s,在保证刻蚀程度的前提下避免因为过度刻蚀损伤多晶硅薄膜1。Step S204: using plasma to etch the surface of the inorganic film layer away from the polysilicon film. Optionally, when using plasma to etch the inorganic film layer, the etching temperature is 230°C-430°C, and the etching time is 2s-12s. Under the premise of ensuring the degree of etching, avoid excessive etching The polysilicon
具体地,在沉积无机膜层2前,测量多晶硅薄膜1的最大表面粗糙度、平均表面粗糙度和多晶硅薄膜1多晶硅晶粒尺寸d。表面粗糙度指加工表面具有的较小间距和微小峰谷的不平度,其包括高度特征参数、间距特征参数和形状特征参数三个评定参数。测量的得到的最大表面粗糙度包括最大高度特征参数a和所述最大高度所对应的最大间距特征参数b,平均表面粗糙度的平均高度特征参数c。在使用等离子体刻蚀时,等离子体中蚀刻粒子的运动轨迹和无机膜层2表面的夹角为θ(即等离子体中蚀刻粒子的运动轨迹和无机膜层2表面之间形成的锐角夹角),且满足arctan(c/d)≤θ≤arctan(a/b),从而能够避免蚀刻粒子轰击在无机膜层2表面不存在凸起的部分,避免无机膜层2平整的部分先被刻蚀从而过早暴露多晶硅薄膜1的表面,防止多晶硅薄膜1被蚀刻粒子损伤。Specifically, before depositing the
进一步地,在刻蚀结束后,使用氢氟酸溶液对多晶硅薄膜1沉积有所述无机膜层2的一侧表面进行一次清洗,除去蚀刻后残留的无机膜层2,得到平整的多晶硅薄膜1。Further, after the etching is finished, the surface of the
更进一步地,在使用氢氟酸溶液对进行一次清洗后,使用纯水再对多晶硅薄膜1沉积有无机膜层2的一侧表面进行清洗,去除残留的氢氟酸和残渣。Furthermore, after the hydrofluoric acid solution is used to clean the
此外,本发明实施例还提供了一种薄膜晶体管的制作方法,该薄膜晶体管的制作方法包括:提供一基板;在基板上形成栅极、栅绝缘层、有源层、源极和漏极的步骤。其中,在基板上形成有源层的步骤包括:在基板上形成非晶硅薄膜;使用激光退火技术使非晶硅薄膜转变为多晶硅薄膜;使用以上所述的多晶硅薄膜处理技术对多晶硅薄膜进行处理;对处理后的多晶硅薄膜进行构图,形成包括有源层的图形。该基板可以为玻璃基板或者适应基板。In addition, an embodiment of the present invention also provides a method for manufacturing a thin film transistor. The method for manufacturing a thin film transistor includes: providing a substrate; forming a gate, a gate insulating layer, an active layer, a source, and a drain on the substrate; step. Wherein, the step of forming the active layer on the substrate includes: forming an amorphous silicon film on the substrate; using laser annealing technology to convert the amorphous silicon film into a polysilicon film; using the above-mentioned polysilicon film processing technology to process the polysilicon film and patterning the processed polysilicon film to form a pattern including an active layer. The substrate can be a glass substrate or a conformable substrate.
示例性地,当制作底栅型薄膜晶体管时,在基板上形成栅极、栅绝缘层、有源层、源极和漏极的步骤具体包括:首先,在基板上形成栅极金属层,经过构图工艺形成包括栅极的图形;然后,在基板上形成栅绝缘层;接着,在基板上形成有源层;最后,在基板上形成源漏极金属层,经过构图工艺形成包括源极和漏极的图形。Exemplarily, when fabricating a bottom-gate thin film transistor, the steps of forming a gate, a gate insulating layer, an active layer, a source, and a drain on a substrate specifically include: first, forming a gate metal layer on a substrate, and after The patterning process forms a pattern including the gate; then, a gate insulating layer is formed on the substrate; then, an active layer is formed on the substrate; finally, a source-drain metal layer is formed on the substrate, and the patterning process is used to form a gate insulating layer including the source and drain. Extreme graphics.
需要说明的是,制作底栅型薄膜晶体管时,在基板上形成栅极、栅绝缘层、有源层、源极和漏极的步骤不局限于此,本发明实施例对此不进行限定。另外,制作顶栅型薄膜晶体管时,在基板上形成栅极、栅绝缘层、有源层、源极和漏极的步骤的具体实现方式本领域技术人员可以参照上述内容,并结合实际需要进行选择,此处不再一一赘述。It should be noted that when fabricating a bottom-gate TFT, the steps of forming a gate, a gate insulating layer, an active layer, a source, and a drain on a substrate are not limited thereto, and are not limited in this embodiment of the present invention. In addition, when making a top-gate thin film transistor, those skilled in the art can refer to the above-mentioned content and carry out the specific implementation of the steps of forming a gate, a gate insulating layer, an active layer, a source electrode and a drain electrode on a substrate, and in combination with actual needs. selection, which will not be repeated here.
由于在本发明实施例提供的薄膜晶体管的制作方法中,在形成有源层的过程中,对多晶硅薄膜进行了如上处理,减小了多晶硅薄膜的表面粗糙度,同时避免了多晶硅薄膜的损伤,即减小了有源层的表面粗糙度,避免了有源层的损伤,减小了薄膜晶体管的漏电流,进而使得将该薄膜晶体管应用于显示装置中时,能够有效提高显示装置的显示效果。In the thin film transistor manufacturing method provided in the embodiment of the present invention, in the process of forming the active layer, the polysilicon film is treated as above, which reduces the surface roughness of the polysilicon film and avoids damage to the polysilicon film at the same time, That is, the surface roughness of the active layer is reduced, damage to the active layer is avoided, and the leakage current of the thin film transistor is reduced, so that when the thin film transistor is applied to a display device, the display effect of the display device can be effectively improved .
依照本发明如上文所述的实施例,这些实施例并没有详尽叙述所有的细节,也不限制该发明仅为所述的具体实施例。显然,根据以上描述,可作很多的修改和变化。本说明书选取并具体描述这些实施例,是为了更好地解释本发明的原理和实际应用,从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。According to the embodiments of the present invention described above, these embodiments do not describe all details in detail, nor do they limit the invention to only the specific embodiments described. Obviously many modifications and variations are possible in light of the above description. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modification on the basis of the present invention. The invention is to be limited only by the claims, along with their full scope and equivalents.
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| JP2007294994A (en) * | 2007-06-25 | 2007-11-08 | Renesas Technology Corp | Method of manufacturing semiconductor device |
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Denomination of invention: A processing method for polycrystalline silicon thin films Granted publication date: 20230120 Pledgee: China Construction Bank Co.,Ltd. Gu'an Sub branch Pledgor: YUNGU (GU'AN) TECHNOLOGY Co.,Ltd. Registration number: Y2025110000103 |
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