CN112420747B - A kind of array substrate and preparation method thereof - Google Patents

Abstract

The application provides an array substrate and a preparation method thereof, wherein the preparation method of the array substrate comprises the following steps: sequentially preparing a grid electrode, a grid insulating layer and an active layer on a substrate, wherein the active layer comprises a channel region and a source electrode contact region and a drain electrode contact region which are respectively positioned at two sides of the channel region; preparing a crystallization inducing film on the active layer, and patterning the crystallization inducing film to form a crystallization inducing line at least positioned in the source contact region and the drain contact region, wherein the crystallization inducing line is perpendicular to a connection line direction between the source contact region and the drain contact region; and applying a horizontal electric field between two adjacent crystallization inducing lines, and simultaneously performing an annealing process on the active layer to induce the crystallization of the active layer so as to convert the active layer from an amorphous oxide semiconductor layer to a crystalline oxide semiconductor layer. The method and the device can solve the problem that the uniformity of laser annealing crystallization of the oxide semiconductor on a large generation line is poor, and the performance of an oxide semiconductor device is influenced.

Description

A kind of array substrate and preparation method thereof

technical field

The present application relates to the field of display technology, in particular to an array substrate and a preparation method thereof.

Background technique

Oxide thin-film transistor technology is considered to have the potential to replace amorphous silicon thin-film transistor technology and become the mainstream technology for next-generation display drive backplanes. Compared with amorphous silicon TFT technology, existing oxide TFT technology is characterized by higher mobility, better large-area uniformity, and lower production costs. However, the mobility of oxide thin film transistor technology is still insufficient compared with low temperature polysilicon thin film transistor technology. Therefore, high-mobility oxide thin film transistor technology has become the direction of everyone's attention. In addition, the stability of oxide thin film transistors has always been a major problem plaguing its wide application. The number of deep-gap oxygen vacancies in oxide thin film transistors is large, which easily leads to poor light stability of the device.

Crystallization of oxide semiconductors can improve the light stability and mobility of devices. The generation line algebra of the display screen is defined according to the size of the glass substrate used in the production of the display screen. The larger the size of the glass substrate, the higher the generation line algebra number. At present, the crystallization method using laser annealing can support the production of the 6th generation line at most, but there are problems such as poor crystallization uniformity on the large generation line (such as 8.5th generation, 10th generation, 10.5th generation, etc.), which affects the performance of oxide semiconductor devices .

Therefore, there are defects in the prior art, which urgently need to be solved.

Contents of the invention

The present application provides an array substrate and a preparation method thereof, which can solve the problem of poor uniformity of laser annealing crystallization of an oxide semiconductor on a large-generation line and affect the performance of an oxide semiconductor device.

In order to solve the above problems, the technical scheme provided by the application is as follows:

The application provides an array substrate, including:

Substrate;

a grid, disposed on the substrate;

a gate insulating layer disposed on the gate;

an active layer, disposed on the gate insulating layer corresponding to the gate, the active layer includes a channel region and a source contact region and a drain contact region respectively located on both sides of the channel region;

a crystallization inducing layer disposed on the active layer, the crystallization inducing layer at least including crystallization inducing lines located in the source contact region and the drain contact region;

Wherein, the crystallization inducing line is arranged perpendicular to the wiring direction between the source contact region and the drain contact region, and the active layer is a crystalline oxide semiconductor layer.

In the array substrate of the present application, the crystallization induction layer further includes at least one crystallization induction line located in the channel region, at least one crystallization induction line located in the channel area and the source contact area and The crystallization induction lines of the drain contact region are arranged in parallel.

In the array substrate of the present application, the material of the crystallization inducing layer is one or more alloys of nickel, tantalum, and tungsten metal materials.

In the array substrate of the present application, the crystal orientation direction of the active layer corresponding to the portion between two adjacent crystallization inducing lines is parallel to the connection line between the source contact region and the drain contact region direction.

In the array substrate of the present application, the array substrate further includes a source and a drain disposed on the active layer, the source is in contact with the source contact region, and the drain is in contact with the The drain contact region is in contact, wherein the part of the source/drain electrode corresponding to the crystallization induction line is in contact with the source/drain contact region through the crystallization induction line.

The present application also provides a method for preparing an array substrate, comprising the following steps:

Step S1, sequentially preparing a gate, a gate insulating layer and an active layer on the substrate, the active layer including a channel region and source contact regions and drain contact regions respectively located on both sides of the channel region;

Step S2, preparing a crystallization-inducing film on the active layer, and patterning the crystallization-inducing film to form crystallization-inducing lines at least in the source contact region and the drain contact region, wherein the The crystallization induction line is perpendicular to the connection direction between the source contact region and the drain contact region;

Step S3, applying a horizontal electric field between two adjacent crystallization inducing lines, and performing an annealing process on the active layer at the same time, so as to induce the crystallization of the active layer, so that the active layer is made of amorphous oxide The semiconductor layer is transformed into a crystalline oxide semiconductor layer.

In the preparation method of the present application, the strength of the horizontal electric field applied between two adjacent crystallization induction lines is 1V/m-10V/m.

In the preparation method of the present application, patterning the crystallization-inducing film in step S2 further includes the following steps:

forming at least one crystallization induction line located in the channel region; wherein, the at least one crystallization induction line located in the channel area and the crystallization induction lines of the source contact region and the drain contact region Parallel setting.

In the preparation method of the present application, the electric field direction of the horizontal electric field is parallel to the connection line direction between the source contact region and the drain contact region.

In the preparation method of the present application, the crystal orientation direction of the active layer corresponding to the portion between two adjacent crystallization inducing lines is parallel to the connection line between the source contact region and the drain contact region direction.

The beneficial effect of the present application is: the array substrate and the preparation method thereof provided by the present application form parallel crystallization induction lines in the source contact area and the drain contact area of the active layer, and between two adjacent crystallization induction lines Apply a horizontal electric field between them, and the direction of the electric field of the horizontal electric field is parallel to the connection direction between the source contact region and the drain contact region. At the same time, an annealing process is performed on the active layer to induce the active layer to carry out lateral crystallization and vertical crystallization, thereby The uniformity of crystallization is improved so that the active layer changes from an amorphous oxide semiconductor layer to a crystalline oxide semiconductor layer. Furthermore, the problem that the uniformity of laser annealing crystallization of the oxide semiconductor on the large-generation line is poor and affects the performance of the oxide semiconductor device is solved.

Description of drawings

The technical solutions and other beneficial effects of the present application will be apparent through the detailed description of the specific embodiments of the present application below in conjunction with the accompanying drawings.

FIG. 1 is a flowchart of a method for preparing an array substrate provided in an embodiment of the present application;

2-7 are schematic diagrams of the preparation process of an array substrate provided in the embodiment of the present application;

FIG. 8 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

FIG. 9 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application.

In the description of the present application, it should be understood that the terms "longitudinal", "transverse", "length", "width", "upper", "lower", "front", "rear", "left", " The orientation or positional relationship indicated by "right", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the application and simplifying the description, rather than indicating or implying the referred device Or elements must have a certain orientation, be constructed and operate in a certain orientation, and thus should not be construed as limiting the application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of said features. In the description of the present application, "plurality" means two or more, unless otherwise specifically defined. In this application, "/" means "or".

The present application may repeat reference numerals and/or reference letters in various instances, such repetition is for the purposes of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed.

At present, with the application of large-size display panels in various fields, the display requirements for large-size display panels are also getting higher and higher. Among them, oxide thin film transistor technology is used in display panels due to its high mobility and other characteristics. However, for large-generation production lines, the crystallization method using laser annealing has problems such as poor crystallization uniformity, which affects oxide semiconductor devices. performance.

Embodiments of the present application provide an array substrate and a manufacturing method thereof, which can improve the uniformity of the crystallization of the oxide semiconductor layer, thereby solving the problem of poor uniformity of the crystallization of the oxide semiconductor layer by laser annealing on the large-generation line, which affects the crystallization of the oxide semiconductor layer. device performance issues.

As shown in FIG. 1 , it is a flow chart of a method for preparing an array substrate provided in an embodiment of the present application. Referring to FIG. 2-FIG. 7, it is a schematic diagram of the preparation process of the array substrate provided by the embodiment of the present application. The preparation method comprises the following steps:

Step S1 , sequentially preparing a gate, a gate insulating layer and an active layer on the substrate, the active layer including a channel region and source contact regions and drain contact regions respectively located on both sides of the channel region.

As shown in FIG. 2 , a gate metal layer is deposited on the substrate 100 , specifically, a gate metal layer with a thickness of about 500 angstroms-4000 angstroms may be deposited on the substrate 100 by sputtering or thermal evaporation. And the gate metal layer is patterned to form a patterned gate 200 .

Then, a gate insulating layer 300 and an oxide semiconductor layer are sequentially prepared on the gate 200 , and the oxide semiconductor layer is patterned to form an active layer 400 corresponding to the gate 200 . Wherein, the active layer 400 includes a channel region 401 and a source contact region 402 and a drain contact region 403 respectively located on two sides of the channel region 401 .

Wherein, the gate 200 may be made of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd) , Iridium (Ir), Chromium (Cr), Lithium (Li), Calcium (Ca), Molybdenum (Mo), Titanium (Ti), Tungsten (W) and Copper (Cu) layer or layers.

The gate insulating layer 300 can be selected from oxide, nitride or oxynitride.

Specifically, the material of the oxide semiconductor film layer includes but is not limited to amorphous ITO, IGO, IGZO, HIZO, IZO, a-InZnO, ZnO, CdO, TiO ₂ , Al ₂ O ₃ , SnO, Cu ₂ At least one of O, NiO, CoO, FeO, Cr ₂ O ₃ , SnO ₂ , Fe ₂ O ₃ , ZrO ₂ , WO ₃ , In ₂ O ₃ , Fe ₃ O ₄ is formed.

Step S2, preparing a crystallization-inducing film on the active layer, and patterning the crystallization-inducing film to form crystallization-inducing lines at least in the source contact region and the drain contact region, wherein the The crystallization induction line is perpendicular to the connection direction between the source contact region and the drain contact region.

As shown in Figures 3 and 4, specifically, a layer of crystallization inducing film 500 is prepared on the active layer 400, the thickness of the crystallization inducing film 500 is 20-500 angstroms, and the The crystallization induction film 500 is patterned to form crystallization induction lines 501 located in the source contact region 402 and the drain contact region 403 . Wherein, the crystallization inducing line 500 is perpendicular to the connection direction between the source contact region 402 and the drain contact region 403, wherein, between the source contact region 402 and the drain contact region 403 The direction of the connecting lines is shown by the arrow in the figure.

Specifically, the crystallization induction wire 501 is made of one or more alloys of nickel, tantalum, and tungsten metal materials, but not limited thereto.

Wherein, the crystallization induction line 501 covers a part of the source contact region 402 and the drain contact region 403, for example, covers one-half of the source contact region 402/the drain contact region 403 area, One-third, one-quarter, or one-fifth, etc.

In this embodiment, the crystallization induction line 501 is located at a side of the source contact region 402 /the drain contact region 403 away from the channel region 401 .

Step S3 , applying a horizontal electric field between two adjacent crystallization inducing lines, and performing an annealing process on the active layer at the same time, so as to induce crystallization of the active layer to form an active layer of polycrystalline material.

Specifically, under the heat treatment conditions of the annealing process in this application, the crystallization induction line 501 can induce the crystallization of the active layer; due to the poor uniformity of laser annealing crystallization of oxide semiconductors on the large-generation production line; therefore, this application At the same time, a horizontal electric field is applied between the two adjacent crystallization induction lines 501, since the electric field greatly increases the mobility of the diffuser, and thus can increase the rate of metal-induced lateral crystallization.

Further, the strength of the horizontal electric field applied between two adjacent crystallization induction lines 501 is 1V/m-10V/m. When the strength of the horizontal electric field is within this range, the mobility of the diffuser is higher, and the rate of lateral crystallization is faster.

The annealing temperature in the traditional annealing and crystallization process is relatively high, such as 600 degrees Celsius, and it is easy to cause damage to other film layers and devices of the array substrate at such a high temperature. However, in the present application, under the assisted action of the electric field, the temperature of the annealing process can be reduced, and the crystallization time can be shortened.

In this embodiment, the temperature of the annealing process can be reduced by 200-400 degrees Celsius, which greatly reduces the process temperature compared with the traditional laser annealing crystallization process.

Further, the direction of the electric field of the horizontal electric field in this application is parallel to the direction of the connection line between the source contact region 402 and the drain contact region 403 .

Crystal grains are formed after the active layer 400 is crystallized, wherein the crystal orientation direction of the active layer 400 corresponding to the part between two adjacent crystallization inducing lines 501 is parallel to the source contact region 402 and the The wiring direction between the drain contact regions 403 . Therefore, the mechanical properties of the active layer 400 parallel to the crystallographic direction are excellent.

In the present application, the active layer 400 undergoes longitudinal crystallization at the position corresponding to the crystallization induction line 501, and the active layer 400 undergoes lateral crystallization at the part between two adjacent crystallization induction lines 501, so that The uniformity of the crystallization of the active layer 400 of the oxide semiconductor material is improved, thereby avoiding the problem of poor crystallization uniformity of the oxide semiconductor by laser annealing on the large-generation production line. In addition, the lateral crystallization of the present application can introduce less metal residue into the channel region 401 , thereby avoiding the possibility of the source contact region 402 and the drain contact region 403 penetrating through. In addition, applying a horizontal electric field between two adjacent crystallization inducing lines 501 can move the crystallization front out of the channel region 401, thereby avoiding the gate electrode caused by more crystallization fronts in the channel region 401. Leakage increases and other problems, thereby improving the reliability of the device.

In one embodiment, the preparation method of the present application may also include the following steps:

Step S4 , as shown in FIG. 5 , forming a source 600 and a drain 700 on the active layer 400 .

The source 600 is in contact with the source contact region 402, and the drain 700 is in contact with the drain contact region 403, wherein the source 600/drain 700 corresponds to the part of the crystallization induction line 501 Contact with the source contact region 402 /drain contact region 403 through the crystallization induction line 501 .

The material of the source electrode 600/drain electrode 700 may be metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and alloys of these metals. The source 600/drain 700 may be a single-layer structure or a multi-layer structure, such as Cu/Mo, Ti/Cu/Ti, Mo/Al/Mo and the like.

In step S5 , as shown in FIG. 6 , a passivation layer 800 is formed on the source electrode 600 and the drain electrode 700 .

Wherein, the passivation layer 800 includes a single-layer or multi-layer structure of one or more of silicon oxide and silicon nitride.

In one embodiment, patterning the crystallization-inducing film in step S2 further includes the following steps:

forming at least one crystallization induction line located in the channel region; wherein, the at least one crystallization induction line located in the channel area and the crystallization induction lines of the source contact region and the drain contact region Parallel setting.

As shown in FIG. 7 , only one crystallization induction line 501 is shown in the channel region 401 , which is of course not limited thereto, and may also include two, three, etc. in other embodiments. Since the crystallization induction lines 501 are correspondingly arranged in the channel region 401, the crystallization induction lines 501 located in the channel region 401 can be formed separately from the crystallization induction lines 501 on both sides when an electric field is applied. electric field. In this way, the crystallization uniformity of the active layer 400 of the oxide semiconductor material can be further ensured.

The present application also provides an array substrate prepared by the above preparation method. As shown in FIG. 8 , the array substrate includes: a substrate 100; a gate 200 disposed on the substrate 100; on the gate 200; the active layer 400 is disposed on the gate insulating layer 300 corresponding to the gate 200, and the active layer 400 includes a channel region 401 and two sides respectively located on the two sides of the channel region 401. A source contact region 402 and a drain contact region 403; a crystallization inducing layer, disposed on the active layer 400, the crystallization inducing layer at least includes A crystallization induction line 501; wherein, the crystallization induction line 501 is arranged perpendicular to the wiring direction between the source contact region 402 and the drain contact region 403, and the active layer 400 is a polycrystalline oxide semiconductor Floor.

In this embodiment, the crystallization inducing layer is made of one or more alloys of nickel, tantalum, and tungsten metal materials.

Wherein, the grain orientation direction of the active layer corresponding to the portion between two adjacent crystallization inducing lines is parallel to the direction of the connecting line between the source contact region and the drain contact region.

Wherein, the array substrate further includes a source and a drain disposed on the active layer, the source is in contact with the source contact region, and the drain is in contact with the drain contact region, Wherein, the part of the source/drain corresponding to the crystallization induction line is in contact with the source contact region/drain contact region through the crystallization induction line.

In one embodiment, as shown in FIG. 9 , the crystallization inducing layer further includes at least one crystallization inducing line 502 located in the channel region 401, and the at least one crystallization inducing line 502 in the channel region is connected to The crystallization inducing lines of the source contact region and the drain contact region are arranged in parallel.

In the array substrate and its preparation method provided by this application, parallel crystallization inducing lines are formed in the source contact region and drain contact area of the active layer, and a horizontal electric field is applied between two adjacent crystallization inducing lines. The direction of the electric field is parallel to the connection direction between the source contact region and the drain contact region. At the same time, an annealing process is performed on the active layer to induce lateral crystallization and vertical crystallization of the active layer, thereby improving the uniformity of crystallization, making The active layer is changed from an amorphous oxide semiconductor layer to a crystalline oxide semiconductor layer. Furthermore, the problem that the uniformity of laser annealing crystallization of the oxide semiconductor on the large-generation line is poor and affects the performance of the oxide semiconductor device is solved.

In summary, although the present application has disclosed the above with preferred embodiments, the above preferred embodiments are not intended to limit the present application, and those of ordinary skill in the art can make various modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is subject to the scope defined in the claims.

Claims (8)

1. An array substrate, characterized in that, comprising: Substrate; a grid, disposed on the substrate; a gate insulating layer disposed on the gate; an active layer, disposed on the gate insulating layer corresponding to the gate, the active layer includes a channel region and a source contact region and a drain contact region respectively located on both sides of the channel region; a crystallization inducing layer disposed on the active layer, the crystallization inducing layer at least including crystallization inducing lines located in the source contact region and the drain contact region; Wherein, the crystallization induction lines are arranged perpendicular to the wiring direction between the source contact region and the drain contact region, and a horizontal electric field is applied between two adjacent crystallization induction lines; The active layer is a crystalline oxide semiconductor layer, and the crystal orientation direction of the active layer corresponding to the part between two adjacent crystallization inducing lines is parallel to that between the source contact region and the drain contact region The direction of the connection line of the active layer corresponding to the position of the crystallization induction line is perpendicular to the direction of the connection line between the source contact region and the drain contact region. 2. The array substrate according to claim 1, wherein the crystallization inducing layer further comprises at least one crystallization inducing line located in the channel region, at least one of the crystallization inducing lines in the channel area The crystallization inducing lines of the source contact region and the drain contact region are arranged in parallel. 3 . The array substrate according to claim 1 , wherein the material of the crystallization inducing layer is one or more alloys of nickel, tantalum and tungsten metal materials. 4. The array substrate according to claim 1, wherein the array substrate further comprises a source and a drain disposed on the active layer, the source is in contact with the source contact region , the drain is in contact with the drain contact region, wherein the part of the source/drain corresponding to the crystallization inducing line is in contact with the source/drain contact region through the crystallization inducing line . 5. A method for preparing an array substrate, comprising the following steps: Step S1, sequentially preparing a gate, a gate insulating layer and an active layer on the substrate, the active layer including a channel region and source contact regions and drain contact regions respectively located on both sides of the channel region; Step S2, preparing a crystallization-inducing film on the active layer, and patterning the crystallization-inducing film to form crystallization-inducing lines at least in the source contact region and the drain contact region, wherein the The crystallization induction line is perpendicular to the connection direction between the source contact region and the drain contact region; Step S3, applying a horizontal electric field between two adjacent crystallization inducing lines, and performing an annealing process on the active layer at the same time, so as to induce the crystallization of the active layer, so that the active layer is made of amorphous oxide the semiconductor layer is converted into a crystalline oxide semiconductor layer; Wherein, the crystal orientation direction of the active layer corresponding to the portion between two adjacent crystallization inducing lines is parallel to the connection line direction between the source contact region and the drain contact region, and the active layer The crystal orientation direction of the layer corresponding to the position of the crystallization induction line is perpendicular to the connection line direction between the source contact region and the drain contact region. 6. The preparation method according to claim 5, characterized in that the strength of the horizontal electric field applied between two adjacent crystallization induction lines is 1V/m-10V/m. 7. The preparation method according to claim 5, characterized in that, patterning the crystallization-inducing film in step S2 further comprises the following steps: forming at least one crystallization induction line located in the channel region; wherein, the at least one crystallization induction line located in the channel area and the crystallization induction lines of the source contact region and the drain contact region Parallel setting. 8 . The manufacturing method according to claim 5 , wherein the direction of the electric field of the horizontal electric field is parallel to the direction of the connection line between the source contact region and the drain contact region.

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