CN112422859B - Image sensor - Google Patents
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- CN112422859B CN112422859B CN202011157513.5A CN202011157513A CN112422859B CN 112422859 B CN112422859 B CN 112422859B CN 202011157513 A CN202011157513 A CN 202011157513A CN 112422859 B CN112422859 B CN 112422859B
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- 239000011159 matrix material Substances 0.000 claims abstract description 38
- 238000003491 array Methods 0.000 claims abstract description 31
- 230000006870 function Effects 0.000 claims abstract description 4
- 230000003287 optical effect Effects 0.000 claims description 27
- 239000003990 capacitor Substances 0.000 claims description 23
- 230000002093 peripheral effect Effects 0.000 claims description 21
- 238000002955 isolation Methods 0.000 claims description 20
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000003384 imaging method Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
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- Solid State Image Pick-Up Elements (AREA)
Abstract
An image sensor, comprising: a pixel cell array divided into a plurality of pixel cell sub-arrays, wherein the pixel cell sub-arrays are divided into a pixel matrix area having effective pixels and a redundant area; wherein each redundant area has one or more functional circuit units for implementing one or more electronic circuit functions and comprising at least a portion of the circuit module and/or the electronics. The invention can effectively improve the space utilization rate of the chip and is beneficial to reducing the cost.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to an image sensor.
Background
Image sensors have been applied in various fields such as machine vision, robotics, satellite-based instrumentation, traffic, navigation and guidance. Typically, an image sensor has pixels that make up a two-dimensional array of image frames.
Wherein the pixel includes a photoelectric conversion element capable of accumulating electric charges corresponding to the amount of absorbed light. In other words, when photons collide with the surface of the photoelectric conversion element formed on the semiconductor substrate, free carriers are generated and collected in the photoelectric conversion element. The collected carriers are read out and then transferred to an output circuit through various processes, thereby reproducing an image.
In an existing image sensor, a pixel array (pixel array) and a peripheral circuit are included, wherein the peripheral circuit may include a row driving circuit, a column readout circuit, a digital processing circuit, other peripheral circuits, and the like.
Further, a semiconductor manufacturing process is adopted to obtain a Micro Lens (Micro Lens) array corresponding to the pixel array, for example, one Micro Lens can correspond to one or a plurality of pixel units, and light irradiates the pixel array through the Micro Lens and is converted into an electric signal. In general, a pixel array is composed of simple photoelectric conversion and signal transmission units, and the circuit structure of each unit is identical.
However, in the conventional partial image sensor, in order to avoid imaging blur caused by the problem that crosstalk of optical paths is easy to occur when one microlens corresponds to a plurality of Pixel units, redundant regions are added to form redundant (Pixel cells), which results in reduced space utilization of the chip and increased cost. This is more common in image sensors that employ microlenses, without solid optical lenses (Lens), such as ultra-thin fingerprint image sensors.
Disclosure of Invention
The invention solves the technical problem of providing an image sensor which can effectively improve the space utilization rate of a chip and is beneficial to reducing the cost.
To solve the above technical problem, an embodiment of the present invention provides an image sensor, including: a pixel cell array divided into a plurality of pixel cell sub-arrays, wherein the pixel cell sub-arrays are divided into a pixel matrix area with effective pixels and a redundant area peripheral circuit, and the peripheral circuit surrounds or partially surrounds the pixel cell array; wherein each redundant area has one or more functional circuit units for implementing one or more electronic circuit functions and comprising at least a portion of the circuit module and/or the electronics.
Optionally, the circuit module is selected from: column readout circuitry, row drive circuitry, and circuit connection lines; the electronic device is selected from: SRAM and capacitor.
Optionally, the functional circuit unit is the column readout circuit, and the column readout circuit is divided into m column readout sub-circuits; in the m pixel unit sub-arrays belonging to the same column, each redundant area respectively comprises a column readout sub-circuit, the column readout sub-circuits contained in different redundant areas are different, and the m column readout sub-circuits are connected by adopting the circuit connection line.
Optionally, the number of column readout sub-circuits belonging to the same column is determined by the area occupied by the column readout circuits and the area of the redundant area; the larger the area occupied by the column readout circuit, the smaller the area of the redundant area, and the larger the number m of the column readout sub-circuits belonging to the same column.
Optionally, the functional circuit unit is the row driving circuit, and the row driving circuit is divided into n row driving sub-circuits; in the n pixel unit sub-arrays belonging to the same row, each redundant area respectively comprises a row driving sub-circuit, the row driving sub-circuits contained in different redundant areas are different, and the n row driving sub-circuits are connected by adopting the circuit connecting lines.
Optionally, the number of the plurality of row driving sub-circuits belonging to the same row is determined by the area occupied by the row driving circuit and the area of the redundant area; the larger the area occupied by the row driving circuit is, the smaller the area of the redundant area is, and the larger the number n of the row driving sub-circuits belonging to the same row is.
Optionally, the functional circuit unit is the SRAM; each redundant area contains one or more of the SRAMs, with or without a space between adjacent SRAMs.
Optionally, the functional circuit unit is the capacitor; each redundant area contains one or more of the capacitances with or without a gap between adjacent capacitances.
Optionally, the redundant area partially surrounds or encloses the pixel matrix area, and a space area is provided between the area where the functional circuit unit is located and the pixel matrix area.
Optionally, the spacer region has one or more of the following: redundant pixels, shallow trench isolation, and well isolation.
Optionally, the image sensor further includes a plurality of optical units, and the sub-arrays of pixel units are in one-to-one correspondence with the optical units; each optical element covers a corresponding sub-array of pixel elements.
Optionally, the optical unit is selected from: optical microlenses and pinholes.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, by arranging one or more functional circuit units in each redundant area, wherein the functional circuit units are selected from at least one part of circuit modules and/or electronic devices, the circuit modules or the electronic devices can be placed in the redundant area between the pixel matrix area and the peripheral circuit, so that the space utilization rate of the chip is effectively improved, and the cost is reduced.
Further, when the functional circuit unit is the column readout circuit and the column readout circuit is large and is difficult to place in a single pixel unit sub-array, the characteristic that the column readout circuit reads out charges in the pixel unit sub-array of the same column can be utilized, and a part of the column readout circuit is placed in a plurality of pixel unit sub-arrays belonging to the same column, so that a plurality of redundant areas are effectively utilized to place larger circuit modules, and the space utilization of the chip is further improved.
Further, when the functional circuit unit is the row driving circuit and the row driving circuit is large and is difficult to be placed in a single sub-array of pixel units, the characteristic that the row driving circuit is used for inputting driving voltages to the sub-arrays of pixel units in the same row can be utilized, and a part of the row driving circuit is placed in the sub-arrays of pixel units belonging to the same row, so that a plurality of redundant areas are effectively utilized to place larger circuit modules, and the space utilization rate of the chip is further improved.
Further, the functional circuit unit is the SRAM; each redundant area contains one or more of the SRAMs, with or without a space between adjacent SRAMs. Therefore, the characteristic that the SRAM can be placed without interval can be utilized, and when the SRAM is placed, the SRAM layout can be reasonably planned according to the available area and shape in the redundant area, so that the optimal utilization of the area is realized.
Further, the functional circuit unit is the capacitor; each redundant area contains one or more of the capacitances with or without a gap between adjacent capacitances. Therefore, the characteristic that the capacitors can be placed without intervals can be utilized, and when the capacitors are placed, the capacitor layout can be reasonably planned according to the available area and shape in the redundant area, so that the optimal utilization of the area is realized.
Furthermore, a space area is arranged between the area where the functional circuit unit is arranged and the pixel matrix area, so that the pixel matrix can be protected, the electrical interference of the functional circuit unit is avoided, and the influence on the imaging effect is avoided.
Drawings
FIG. 1 is a schematic top view of a cross-sectional structure of a device of an image sensor according to the prior art;
FIG. 2 is a schematic top view showing a cross-sectional structure of a device of a first image sensor according to an embodiment of the present invention;
FIG. 3 is a schematic top view illustrating a cross-sectional structure of a device of a second image sensor according to an embodiment of the present invention;
FIG. 4 is a schematic top view showing a cross-sectional structure of a device of a third image sensor according to an embodiment of the present invention;
FIG. 5 is a schematic top view showing a cross-sectional structure of a device of a fourth image sensor according to an embodiment of the present invention;
fig. 6 is a schematic top view illustrating a cross-sectional structure of a fifth image sensor according to an embodiment of the present invention.
Detailed Description
As described above, in the conventional image sensor, the pixel cell array and the peripheral circuit are included, wherein the peripheral circuit may include a row driving circuit, a column readout circuit, a digital processing circuit, and other peripheral circuits, however, in order to avoid imaging ambiguity caused by the problem that optical path crosstalk is easy to occur when one microlens corresponds to a plurality of pixel cells, a redundant area is added to form a redundant pixel cell, which results in a reduction in space utilization of a chip and an increase in cost.
Referring to fig. 1, fig. 1 is a schematic top view of a cross-sectional structure of a device of an image sensor in the prior art.
As shown in fig. 1, the pixel cell array may be divided into a number of pixel cell sub-arrays, wherein the pixel cell sub-arrays are divided into a pixel matrix area having effective pixels and a redundancy area, wherein the pixel matrix area may have a pixel matrix.
It should be noted that although a 5×5 pixel matrix is used as an example in fig. 1, in the implementation, the specific size of the pixel matrix is not limited.
Peripheral circuitry may also be included in the image sensor, surrounding or partially surrounding the array of pixel cells.
It will be appreciated that for a pixel cell array, the peripheral circuit may directly surround or directly semi-surround the pixel cell array, or may indirectly surround or indirectly semi-surround the pixel cell array, for example, for a pixel cell array including m×n pixel cell sub-arrays, m×n pixel cell sub-arrays may be arranged with the peripheral circuit surrounding the pixel cell sub-arrays, where m and n are positive integers, and m and n may be equal or unequal
Further, the image sensor may further include a plurality of optical units, and the sub-arrays of pixel units are in one-to-one correspondence with the optical units; each optical element may cover a corresponding sub-array of pixel elements.
Still further, the optical unit may be selected from: optical microlenses (Micro-Lens) and pinholes (Pinhole).
In one non-limiting embodiment, a semiconductor fabrication process may be used to obtain a microlens array corresponding to the pixel array, e.g., a microlens may correspond to a sub-array of pixel elements, each sub-array of pixel elements containing one or more pixel elements, where light is directed through the microlens onto the pixel array and converted to an electrical signal. In general, the sub-array of pixel units may be composed of simple photoelectric conversion and signal transmission units, and the circuit structures of each unit are identical.
The inventors of the present invention have found through studies that in the case of employing a redundant region, the chip area increases significantly, which leads to an increase in cost. In the above-mentioned case, in an image sensor (for example, an image sensor with ultra-thin fingerprint) having a plurality of pixel units in each pixel unit sub-array, the problem of the increase of the chip area is more remarkable because the corresponding relationship between the optical unit array and the pixel unit array is more depended on.
In the embodiment of the invention, by arranging one or more functional circuit units in each redundant area, wherein the functional circuit units are selected from at least one part of circuit modules and/or electronic devices, the circuit modules or the electronic devices can be placed in the redundant area between the pixel unit array and the peripheral circuit, so that the space utilization rate of the chip is effectively improved, and the cost is reduced.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2, fig. 2 is a schematic top view illustrating a cross-sectional structure of a device of a first image sensor according to an embodiment of the present invention.
The first image sensor may include a pixel cell array and peripheral circuits (not shown).
The pixel unit array is divided into a plurality of pixel unit subarrays, and the pixel unit subarrays are divided into a pixel matrix area with effective pixels and a redundant area; the peripheral circuit surrounds or partially surrounds the pixel cell array.
Wherein each redundant area has one or more functional circuit units for implementing one or more electronic circuit functions and comprising at least a portion of the circuit module and/or the electronics.
It should be noted that the peripheral circuit may have a space from the pixel cell array.
It will be appreciated that the effective pixels (effective pixels) are pixels for participating in photoimaging, and may be opposed to redundant pixels (dummy pixels), for example.
In the first image sensor shown in fig. 2, the functional circuit units may be separate electronic devices in the pixel cell array.
Further, the electronic device may be selected from: static Random-Access Memory (SRAM) and capacitance.
It should be noted that the electronic device may be one of an SRAM and a capacitor, and may also include both the SRAM and the capacitor.
Further, the functional circuit unit is the SRAM; each redundant area contains one or more of the SRAMs, with or without a space between adjacent SRAMs.
The functional circuit unit shown in fig. 2 may be 4 SRAMs without a space.
In the embodiment of the invention, the functional circuit unit is the SRAM; each redundant area contains one or more of the SRAMs, with or without a space between adjacent SRAMs. Therefore, the characteristic that the SRAM can be placed without interval can be utilized, and when the SRAM is placed, the SRAM layout can be reasonably planned according to the available area and shape in the redundant area, so that the optimal utilization of the area is realized.
It should be noted that when the redundant area is larger and the number of SRAMs is smaller, the redundant area can be set to be an SRAM with an interval, so that when the SRAMs are placed, the interval between the SRAMs can be increased, the layout of the SRAMs is reasonably planned, and the influence possibly existing between the SRAMs is avoided.
Still further, the functional circuit unit may be the capacitor; each redundant area contains one or more of the capacitances with or without a gap between adjacent capacitances.
The functional circuit unit shown in fig. 2 may be 4 capacitors without a space.
In the embodiment of the invention, the functional circuit unit is the capacitor; each redundant area contains one or more of the capacitances with or without a gap between adjacent capacitances. Therefore, the characteristic that the capacitors can be placed without intervals can be utilized, and when the capacitors are placed, the capacitor layout can be reasonably planned according to the available area and shape in the redundant area, so that the optimal utilization of the area is realized.
It should be noted that when the redundant area is larger and the number of the capacitors is smaller, the capacitors can be set to have intervals, so that when the capacitors are placed, the intervals between the capacitors can be increased, the layout of the capacitors is reasonably planned, and the influence possibly existing between the capacitors is avoided.
Further, the redundant area may partially surround or enclose the pixel matrix area, and a space area is provided between the area where the functional circuit unit is located and the pixel matrix area.
The region shown by the broken line in fig. 2 is the spacing region, which is used to separate the functional circuit unit and the pixel matrix in each pixel matrix region.
In the embodiment of the invention, the pixel matrix can be protected by arranging the interval area between the area where the functional circuit unit is positioned and the pixel matrix area, so that the electrical interference of the functional circuit unit is avoided, and the imaging effect is prevented from being influenced.
Further, the spacer region may have one or more of the following: redundant pixels (Dummy pixels), shallow trench Isolation (Shallow Trench Isolation), and Well Isolation (Well Isolation).
It should be noted that the spacer region may be one of a redundant pixel, a shallow trench isolation, and a well isolation, and may further include a plurality of the redundant pixel, the shallow trench isolation, and the well isolation.
In the embodiment of the invention, proper isolation modes can be selected for isolation according to specific conditions, for example, modes such as shallow slot isolation or well isolation can be adopted when the space requirement is smaller and the isolation requirement is larger; when the space requirement is larger and the isolation requirement is smaller, redundant pixel isolation and other modes can be adopted.
In the following description of the embodiments of the present invention, redundant pixel isolation (i.e., the spacing region has redundant pixels) will be described as an example.
In the embodiment of the invention, by arranging one or more functional circuit units in each redundant area, wherein the functional circuit units are selected from at least one part of circuit modules and/or electronic devices, the circuit modules or the electronic devices can be placed in the redundant area between the pixel matrix area and the peripheral circuit, so that the space utilization rate of the chip is effectively improved, and the cost is reduced.
Referring to fig. 3, fig. 3 is a schematic top view illustrating a cross-sectional structure of a device of a second image sensor according to an embodiment of the present invention.
The second image sensor may include a pixel cell array divided into a number of pixel cell sub-arrays divided into a pixel matrix area having effective pixels and a redundancy area; and a peripheral circuit surrounding or partially surrounding the pixel cell array.
In the second type of image sensor shown in fig. 3, in the pixel cell array, the functional circuit unit may include at least a part of a circuit module.
Further, the circuit module may be selected from: column readout circuitry, row drive circuitry, and circuit connection lines.
It should be noted that the circuit module may be one of a column readout circuit, a row driving circuit and a circuit connection line, and may further include a plurality of column readout circuits, row driving circuits and circuit connection lines.
Further, the redundant area partially surrounds or encloses the pixel matrix area, and a space area is arranged between the area where the functional circuit unit is located and the pixel matrix area.
The region shown by the broken line in fig. 3 is the spacing region, which is used to separate the functional circuit unit and the pixel matrix in each pixel matrix region.
In the embodiment of the invention, because the column readout circuit and the row driving circuit are required to keep a certain interval with the pixel matrix, the pixel matrix can be protected by arranging the interval area between the area where the functional circuit unit is arranged and the pixel matrix area, the electric interference of the functional circuit unit is avoided, and the imaging effect is prevented from being influenced.
It should be noted that, in the image sensor shown in fig. 3, one of the length and the width occupied by a single pixel in the pixel matrix is taken as the length or the width of the interval region, which is merely a non-limiting setting value, and in the embodiment of the present invention, the length or the width of the specific interval region may be set according to specific requirements of electrical interference resistance.
It should be noted that in the second image sensor shown in fig. 3, there may be a case where the column readout circuit and the row drive circuit occupy a large area, and are difficult to be placed in a single pixel cell sub-array, and in this case, a plurality of pixel cell sub-arrays may be used for placement.
Further, the functional circuit unit is the column readout circuit, and the column readout circuit is divided into m column readout sub-circuits; in the m pixel unit sub-arrays belonging to the same column, each redundant area respectively comprises a column readout sub-circuit, the column readout sub-circuits contained in different redundant areas are different, and the m column readout sub-circuits are connected by adopting the circuit connection line.
Referring to fig. 4, fig. 4 is a schematic top view illustrating a cross-sectional structure of a device of a third image sensor according to an embodiment of the present invention.
As shown in fig. 4, the functional circuit unit is the column readout circuit, and the m sub-arrays of pixel units belong to the same column and respectively include a 1 st column readout sub-circuit, a 2 nd column readout sub-circuit and an mth column readout sub-circuit.
The column readout circuit is divided into a 1 st column readout sub-circuit, a 2 nd column readout sub-circuit and an mth column readout sub-circuit, and the m column readout sub-circuits are connected by adopting the circuit connection line.
In the embodiment of the invention, when the functional circuit unit is the column readout circuit and the column readout circuit is larger and is difficult to place in a single pixel unit sub-array, the characteristic that the column readout circuit is used for reading out charges in the pixel unit sub-array of the same column can be utilized, and a part of the column readout circuit is respectively placed in a plurality of pixel unit sub-arrays belonging to the same column, so that a plurality of redundant areas are effectively utilized to place larger circuit modules, and the space utilization rate of a chip is further improved.
Further, the number of the plurality of column readout sub-circuits belonging to the same column is determined by the area occupied by the column readout circuit and the area of the redundant area; the larger the area occupied by the column readout circuit, the smaller the area of the redundant area, and the larger the number m of the column readout sub-circuits belonging to the same column.
In the embodiment of the invention, the number is determined by the area, so that the layout can be reasonably planned based on the area for placing the column readout sub-circuit when the column readout sub-circuit is divided and placed, and the utilization rate of the chip is better improved.
Referring to fig. 5, fig. 5 is a schematic top view illustrating a cross-sectional structure of a device of a fourth image sensor according to an embodiment of the present invention.
As shown in fig. 5, the functional circuit unit is the row driving circuit, and the n pixel unit sub-arrays belong to the same row and respectively include a 1 st row driving sub-circuit, a 2 nd row driving sub-circuit and an nth row driving sub-circuit.
The row driving circuit is divided into a 1 st row driving sub-circuit, a 2 nd row driving sub-circuit and an nth row driving sub-circuit, and the n row driving sub-circuits are connected by adopting the circuit connecting wire.
In the embodiment of the invention, when the functional circuit unit is the row driving circuit and the row driving circuit is larger and is difficult to place in a single pixel unit sub-array, the characteristic that the row driving circuit is used for inputting driving voltage to the pixel unit sub-array in the same row can be utilized, and a part of the row driving circuit is respectively placed in a plurality of pixel unit sub-arrays belonging to the same row, so that a plurality of redundant areas are effectively utilized to place larger circuit modules, and the space utilization rate of a chip is further improved.
Further, the number of the plurality of row driving sub-circuits belonging to the same row is determined by the area occupied by the row driving circuit and the area of the redundant area; the larger the area occupied by the row driving circuit is, the smaller the area of the redundant area is, and the larger the number n of the row driving sub-circuits belonging to the same row is.
In the embodiment of the invention, the number is determined by the area, so that the layout is reasonably planned based on the area capable of being used for placing the row driving sub-circuits when the row driving circuits are divided and the row driving sub-circuits are placed, and the utilization rate of chips is better improved.
Referring to fig. 6, fig. 6 is a schematic top view illustrating a cross-sectional structure of a fifth image sensor according to an embodiment of the present invention.
The fifth image sensor may include a pixel cell array divided into a number of pixel cell sub-arrays, wherein the pixel cell sub-arrays are divided into a pixel matrix area having effective pixels and a redundancy area; and a peripheral circuit surrounding or partially surrounding the pixel cell array.
Further, the redundant area may fully enclose the pixel matrix area, and a space area is provided between the area where the functional circuit unit is located and the pixel matrix area.
In the embodiment of the invention, the pixel matrix can be protected by arranging the interval area between the area where the functional circuit unit is positioned and the pixel matrix area, so that the electrical interference of the functional circuit unit is avoided, and the imaging effect is prevented from being influenced.
Wherein the functional circuit unit may be a separate circuit module and/or an electronic device, and may be selected from, for example: SRAM and capacitor.
In the embodiment of the invention, by arranging one or more functional circuit units in each redundant area, wherein the functional circuit units are selected from at least one part of circuit modules and/or electronic devices, the circuit modules or the electronic devices can be placed in the redundant area between the pixel matrix area and the peripheral circuit, so that the space utilization rate of the chip is effectively improved, and the cost is reduced.
Further, the image sensor may further include a plurality of optical units, and the sub-arrays of pixel units are in one-to-one correspondence with the optical units; each optical element covers a corresponding sub-array of pixel elements.
Still further, the optical unit may be selected from: optical microlenses and pinholes.
It should be noted that the optical microlenses may be arranged in an array.
In the embodiment of the invention, by arranging the micro-lens array structure, one optical unit (such as an optical lens or a small hole) can be selected to correspond to one pixel unit sub-array, and the image sensor (such as an image sensor of an ultrathin fingerprint) with a plurality of pixel units in each pixel unit sub-array implements the scheme in the embodiment of the invention.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (11)
1. An image sensor, comprising:
a pixel cell array divided into a plurality of pixel cell sub-arrays, wherein the pixel cell sub-arrays are divided into a pixel matrix area having effective pixels and a redundant area;
a peripheral circuit surrounding or partially surrounding the pixel cell array;
wherein each redundant area has one or more functional circuit units for implementing one or more electronic circuit functions and comprising at least a portion of the circuit module and/or the electronics;
a spacing region is arranged between the region where the functional circuit unit is located and the pixel matrix region;
the circuit module is selected from: a row driving circuit;
the row driving circuit is used for inputting driving voltages to the pixel unit subarrays of the same row, and a part of the row driving circuit is respectively arranged in a plurality of pixel unit subarrays belonging to the same row;
the number of the row driving sub-circuits belonging to the same row is determined by the area occupied by the row driving circuit and the area of the redundant area;
the larger the area occupied by the row driving circuit is, the smaller the area of the redundant area is, and the larger the number n of the row driving sub-circuits belonging to the same row is.
2. The image sensor of claim 1, wherein the image sensor comprises a sensor array,
the circuit module is further selected from: column readout circuitry and circuit connection lines; the electronic device is selected from: SRAM and capacitor.
3. The image sensor according to claim 2, wherein the functional circuit unit is the column readout circuit, and the column readout circuit is divided into m column readout sub-circuits;
in the m pixel unit sub-arrays belonging to the same column, each redundant area respectively comprises a column readout sub-circuit, the column readout sub-circuits contained in different redundant areas are different, and the m column readout sub-circuits are connected by adopting the circuit connection line.
4. The image sensor of claim 3, wherein the number of column readout sub-circuits belonging to the same column is determined by an area occupied by the column readout circuit and an area of the redundant area;
the larger the area occupied by the column readout circuits is, the smaller the area of the redundant area is, and the larger the number m of column readout sub-circuits belonging to the same column is.
5. The image sensor of claim 1, wherein the row drive circuit is partitioned into n row drive sub-circuits;
in the n pixel unit sub-arrays belonging to the same row, each redundant area respectively comprises a row driving sub-circuit, the row driving sub-circuits contained in different redundant areas are different, and the n row driving sub-circuits are connected by adopting circuit connecting wires.
6. The image sensor according to claim 2, wherein the functional circuit unit is the SRAM;
each redundant area contains one or more of the SRAMs, with or without a space between adjacent SRAMs.
7. The image sensor of claim 2, wherein the functional circuit unit is the capacitor;
each redundant area contains one or more of the capacitances with or without a gap between adjacent capacitances.
8. The image sensor of claim 1, wherein the redundant area partially encloses or encloses the pixel matrix area.
9. The image sensor of claim 8, wherein the spacer region has one or more of:
redundant pixels, shallow trench isolation, and well isolation.
10. The image sensor of claim 1, further comprising a plurality of optical elements, the sub-arrays of pixel elements being in one-to-one correspondence with the optical elements;
each optical element covers a corresponding sub-array of pixel elements.
11. The image sensor of claim 10, wherein the sensor further comprises a sensor element,
the optical unit is selected from: optical microlenses and pinholes.
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| JP2005134809A (en) * | 2003-10-31 | 2005-05-26 | Toshiba Matsushita Display Technology Co Ltd | Display device |
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