CN112463539A - Equipment temperature monitoring circuit and server system - Google Patents
Equipment temperature monitoring circuit and server system Download PDFInfo
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- CN112463539A CN112463539A CN202011444886.0A CN202011444886A CN112463539A CN 112463539 A CN112463539 A CN 112463539A CN 202011444886 A CN202011444886 A CN 202011444886A CN 112463539 A CN112463539 A CN 112463539A
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- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
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Abstract
本发明公开了一种设备温度监控电路及服务器系统，包括主温控芯片、温度检测电路及从温控芯片。主温控芯片通过温度读取总线获取设备的第一温度信息，以实现设备的温度监控；温度检测电路检测设备的第二温度信息；从温控芯片基于设备当前对应的散热策略对第二温度信息进行温度补偿，并基于温度补偿后的第二温度信息实现设备的温度监控。可见，系统对设备温度监控既能通过温度读取总线获取设备温度，又能通过温度检测电路获取设备温度，也就是说，即使设备内集成的温度传感器出现问题，也能通过温度检测电路监控设备温度异常；而且，本申请的设备温度监控电路避免了因主温控芯片无法获取设备温度导致的系统无法开机问题及系统监控异常报警问题。
The invention discloses a device temperature monitoring circuit and a server system, comprising a main temperature control chip, a temperature detection circuit and a slave temperature control chip. The main temperature control chip obtains the first temperature information of the device through the temperature reading bus, so as to realize the temperature monitoring of the device; the temperature detection circuit detects the second temperature information of the device; temperature compensation is performed on the information, and temperature monitoring of the device is implemented based on the temperature-compensated second temperature information. It can be seen that the system can monitor the device temperature not only through the temperature reading bus, but also through the temperature detection circuit. The temperature is abnormal; and, the device temperature monitoring circuit of the present application avoids the problem that the system cannot be turned on and the system monitoring abnormal alarm problem caused by the failure of the main temperature control chip to obtain the device temperature.
Description
Technical Field
The invention relates to the field of server safety, in particular to a device temperature monitoring circuit and a server system.
Background
With the generation of new generation of Central Processing Units (CPUs), new standards and new products have come to be matched, including DDR5 (double data rate synchronous dynamic random access memory). Compared with DDR4, the improved DDR5 has data rate up to 4400MT/s, i.e. the frequency is up to 4400MHz, and the data rate is increased by 37.5 percent compared with the fastest DDR4-3200 at present. However, the monolithic chip density of DDR5 exceeds 16Gb, making its temperature monitoring critical.
In the prior art, a design scheme of DDR temperature monitoring is shown in fig. 1, taking a 1-way server as an example, a CPU is used as a main temperature control chip of a DDR, and is used for monitoring temperature information of the DDR in real time so as to avoid overheating of the DDR; the BMC (Baseboard management Controller) is used as a slave temperature control chip of the DDR and used for monitoring temperature information of the DDR in a debug (debugging) process of the system so as to avoid overheating of the DDR, and the BMC read the temperature information from the DDR through a DDR SPD SMBus (temperature reading bus). That is, both the CPU and the BMC can read temperature information of the DDR as a temperature control chip of the DDR, and the CPU and the BMC are switched by a MUX (multiplexer). The channel switching of the MUX chip is directly controlled by a Debug Header, under the normal working condition of the system, a jump cap of the Debug Header is buckled on the Pin1-2, at the moment, a low level signal is input into an S interface of the MUX chip, the MUX chip is gated to one path of the CPU, and the CPU is required to monitor the temperature information of the DDR in real time; in the system Debug process or under the special use condition, a user can switch the jump cap of the Debug Header to Pin2-3, at the moment, an S interface of the MUX chip inputs a high-level signal, the MUX chip is gated to one way of the BMC, and the temperature information of the DDR is monitored by the BMC. It should be noted that the CPU needs to read the temperature information of the DDR in real time, so that the Debug process cannot be too long, and after the Debug process is finished, the jump cap of the Debug Header needs to be switched back to Pin1-2 in time, thereby avoiding the phenomenon that the device cannot be started up in next use.
Based on the above analysis, the existing DDR temperature monitoring design scheme has the following disadvantages: 1) the system can only read the DDR memory bank temperature through the DDR SPD SMBus, if a problem occurs in a temperature sensor integrated in the DDR memory bank, an error exists in the temperature information read through the DDR SPD SMBus, the DDR temperature monitoring is abnormal, and if the DDR memory bank temperature is not found and throttled in time, overheating is easily caused and the memory bank is damaged. 2) In the debug process of the system, the jump cap of the MUX chip needs to be manually switched back and forth, and the problem that the system cannot be started up when being used next time due to forgetting to switch back is easily caused. 3) In the process of system debug, if the control right of the CPU to the DDR SPD SMBus is not recovered for a long time, the system monitoring abnormity alarm is easily triggered.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide an equipment temperature monitoring circuit and a server system, wherein the system can monitor the equipment temperature, not only can acquire the equipment temperature through a temperature reading bus, but also can acquire the equipment temperature through an external temperature detection circuit, namely, even if a temperature sensor integrated in the equipment has a problem, the external temperature detection circuit can also monitor the equipment temperature abnormity; moreover, the equipment temperature monitoring circuit avoids the problem that the system cannot be started and the problem that the system monitoring is abnormal and alarms because the main temperature control chip cannot acquire the equipment temperature.
In order to solve the above technical problem, the present invention provides an apparatus temperature monitoring circuit, including:
the main temperature control chip is connected with a temperature reading bus of the equipment and used for acquiring first temperature information of the equipment through the temperature reading bus so as to realize temperature monitoring of the equipment;
the temperature detection circuit is arranged outside the equipment and used for detecting second temperature information of the equipment;
and the slave temperature control chip is connected with the temperature detection circuit and used for carrying out temperature compensation on the second temperature information based on the current corresponding heat dissipation strategy of the equipment and realizing temperature monitoring of the equipment based on the second temperature information after temperature compensation.
Preferably, when the number of the devices is plural, the temperature detection circuit includes:
a plurality of temperature sensors provided corresponding to the plurality of devices;
the multi-switch circuit is respectively connected with the plurality of temperature sensors and the slave temperature control chip;
correspondingly, the slave temperature control chip is specifically configured to sequentially acquire second temperature information of the multiple devices correspondingly detected by the multiple temperature sensors by controlling the switching channels of the multi-switching circuit to be gated in turn.
Preferably, the device temperature monitoring circuit further comprises:
the first data selector is used for connecting a first movable end with the main temperature control chip and connecting a stationary end with the equipment;
the first movable end is connected with the second movable end of the first data selector, the second movable end is connected with the temperature detection circuit, and the fixed end is connected with the secondary temperature control chip;
the control circuit is respectively connected with the first data selector and the second data selector and is used for controlling the first data selector to gate a data transmission channel of the main temperature control chip and controlling the second data selector to gate a data transmission channel of the temperature detection circuit when the main temperature control chip has a control requirement on the temperature reading bus or the slave temperature control chip carries out equipment temperature control timeout through the temperature reading bus; and when the slave temperature control chip has a control requirement on the temperature reading bus, controlling the first data selector and the second data selector to gate the data transmission channel of the slave temperature control chip.
Preferably, the control circuit comprises a chip selection circuit, an AND gate, a NOT gate and a main control chip; wherein:
the output end of the chip selection circuit is respectively connected with the first input ends of the slave temperature control chip and the AND gate, the slave temperature control chip is connected with the master control chip, the master control chip is connected with the second input end of the AND gate, the output end of the AND gate is connected with the input end of the NOT gate, the common end of the AND gate is connected with the control end of the first data selector, and the output end of the NOT gate is connected with the control end of the second data selector;
the chip selection circuit is used for outputting a low level signal when the main temperature control chip has a control requirement on the temperature reading bus and outputting a high level signal when the slave temperature control chip has a control requirement on the temperature reading bus; the slave temperature control chip is also used for outputting a device temperature control request to the master control chip when receiving the high level signal;
the master control chip is used for judging whether the slave temperature control chip is allowed to carry out equipment temperature control through the temperature reading bus under the current condition after receiving the equipment temperature control request, and if so, outputting a high level signal to the AND gate; and when the main temperature control chip has a control requirement on the temperature reading bus or the slave temperature control chip carries out equipment temperature control timeout through the temperature reading bus, outputting a low level signal to the AND gate.
Preferably, the chip selection circuit comprises a Debug Header, a first resistor and a second resistor; wherein:
a 2Pin of the Debug Header is connected with a first end of the first resistor, a common end of the Debug Header is used as an output end of the chip selection circuit, a second end of the first resistor is grounded, a 3Pin of the Debug Header is connected with a first end of the second resistor, a second end of the second resistor is connected with a direct-current power supply, and a 1Pin of the Debug Header is suspended; when the main temperature control chip has a control requirement on the temperature reading bus, a jump cap of the Debug Header is buckled on the Pin 1-2; when the slave temperature control chip has a control requirement on the temperature reading bus, the jump cap of the Debug Header is buckled on the Pin 2-3.
Preferably, the and gate and the not gate are both integrated in the slave temperature control chip.
Preferably, the control circuit further comprises a switching tube, a third resistor and a light emitting diode; wherein:
the first end of the third resistor is respectively connected with the main control chip, the second input end of the AND gate and the control end of the switch tube, the first end of the switch tube is connected with the cathode of the light-emitting diode, the anode of the light-emitting diode is connected with a direct current power supply, and the second end of the switch tube is grounded; the switch tube is a switch tube with a control end input with a high level for switching on and a low level for switching off.
Preferably, the slave temperature control chip is connected with the master temperature control chip;
the slave temperature control chip is specifically configured to, when a heat dissipation strategy currently corresponding to the device changes, obtain first temperature information of the device from the master temperature control chip, use a difference value between the first temperature information and the second temperature information as a temperature compensation value, and perform temperature compensation on subsequently obtained second temperature information based on the temperature compensation value.
Preferably, the slave temperature control chip is further configured to perform an alarm of abnormal device temperature and control a system to shut down when the temperature detection circuit detects that the device is abnormal in temperature but the system where the device is located does not perform a protection action of abnormal device temperature.
In order to solve the technical problem, the invention also provides a server system which comprises the equipment and any one of the equipment temperature monitoring circuits.
The invention provides an equipment temperature monitoring circuit which comprises a main temperature control chip, a temperature detection circuit and a slave temperature control chip. The main temperature control chip is used for acquiring first temperature information of the equipment through the temperature reading bus so as to realize temperature monitoring of the equipment; the temperature detection circuit is used for detecting second temperature information of the equipment; the slave temperature control chip is used for carrying out temperature compensation on the second temperature information based on a current corresponding heat dissipation strategy of the equipment, and realizing temperature monitoring of the equipment based on the second temperature information after the temperature compensation. Therefore, the system can monitor the temperature of the equipment, and can acquire the temperature of the equipment through the temperature reading bus and the temperature of the equipment through the peripheral temperature detection circuit, namely, even if the temperature sensor integrated in the equipment has a problem, the temperature of the equipment can be monitored to be abnormal through the peripheral temperature detection circuit; moreover, the equipment temperature monitoring circuit avoids the problem that the system cannot be started and the problem that the system monitoring is abnormal and alarms because the main temperature control chip cannot acquire the equipment temperature.
The invention also provides a server system which has the same beneficial effect as the temperature monitoring circuit.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a DDR temperature monitoring scheme in the prior art;
fig. 2 is a schematic structural diagram of a first device temperature monitoring circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first device temperature monitoring circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a second device temperature monitoring circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a control circuit according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a device temperature monitoring circuit and a server system, the system can monitor the device temperature, not only can acquire the device temperature through a temperature reading bus, but also can acquire the device temperature through an external temperature detection circuit, namely, even if a temperature sensor integrated in the device has a problem, the device temperature abnormity can be monitored through the external temperature detection circuit; moreover, the equipment temperature monitoring circuit avoids the problem that the system cannot be started and the problem that the system monitoring is abnormal and alarms because the main temperature control chip cannot acquire the equipment temperature.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a first device temperature monitoring circuit according to an embodiment of the present invention.
The device temperature monitoring circuit includes:
the main temperature control chip 1 is connected with a temperature reading bus of the equipment and is used for acquiring first temperature information of the equipment through the temperature reading bus so as to realize temperature monitoring of the equipment;
the temperature detection circuit 2 is arranged outside the equipment and used for detecting second temperature information of the equipment;
and the slave temperature control chip 3 is connected with the temperature detection circuit 2 and used for performing temperature compensation on the second temperature information based on a current corresponding heat dissipation strategy of the equipment and realizing temperature monitoring of the equipment based on the second temperature information after the temperature compensation.
Specifically, the equipment temperature monitoring circuit of this application includes main temperature control chip 1, temperature-detecting circuit 2 and follows temperature control chip 3, and its theory of operation is:
on one hand, the main temperature control chip 1 can be directly connected with a temperature reading bus of the equipment so as to acquire first temperature information of the equipment through the temperature reading bus in real time, and therefore real-time temperature monitoring of the equipment is achieved. On the other hand, a temperature detection circuit 2 connected with the slave temperature control chip 3 is arranged outside the device, so that the slave temperature control chip 3 acquires second temperature information of the device through the temperature detection circuit 2, and temperature monitoring of the device is achieved.
In addition, considering that the first temperature information of the device is detected by an internal temperature sensor integrated in the device, and the second temperature information of the device is detected by a temperature detection circuit 2 arranged outside the device, since the case of the system where the device is located is designed with a heat dissipation device, the device temperature detected by the internal temperature sensor integrated in the device and the device temperature detected by the temperature detection circuit 2 arranged outside the device are slightly different, after the second temperature information of the device is acquired from the temperature detection circuit 2 by the temperature control chip 3, the second temperature information is temperature compensated based on a heat dissipation strategy currently corresponding to the device, and then the temperature monitoring of the device is realized based on the second temperature information after the temperature compensation.
The invention provides an equipment temperature monitoring circuit which comprises a main temperature control chip, a temperature detection circuit and a slave temperature control chip. The main temperature control chip is used for acquiring first temperature information of the equipment through the temperature reading bus so as to realize temperature monitoring of the equipment; the temperature detection circuit is used for detecting second temperature information of the equipment; the slave temperature control chip is used for carrying out temperature compensation on the second temperature information based on a current corresponding heat dissipation strategy of the equipment, and realizing temperature monitoring of the equipment based on the second temperature information after the temperature compensation. Therefore, the system can monitor the temperature of the equipment, and can acquire the temperature of the equipment through the temperature reading bus and the temperature of the equipment through the peripheral temperature detection circuit, namely, even if the temperature sensor integrated in the equipment has a problem, the temperature of the equipment can be monitored to be abnormal through the peripheral temperature detection circuit; moreover, the equipment temperature monitoring circuit avoids the problem that the system cannot be started and the problem that the system monitoring is abnormal and alarms because the main temperature control chip cannot acquire the equipment temperature.
On the basis of the above-described embodiment:
as an alternative embodiment, when the number of the devices is plural, the temperature detection circuit 2 includes:
a plurality of temperature sensors provided corresponding to the plurality of devices;
a multi-switch circuit connected to the plurality of temperature sensors and the slave temperature control chip 3, respectively;
correspondingly, the slave temperature control chip 3 is specifically configured to sequentially acquire the second temperature information of the multiple devices correspondingly detected by the multiple temperature sensors by controlling the switching channels of the multi-switching circuit to be gated in turn.
Specifically, when the number of the devices is plural, the temperature detection circuit 2 for respectively detecting the second temperature information of the plural devices includes plural temperature sensors and a switch circuit, and its operating principle is:
this application corresponds for a plurality of equipment and sets up a plurality of temperature sensor, and every temperature sensor all is used for detecting the second temperature information of the equipment that corresponds with self. Each temperature sensor occupies one switching channel of the multi-switching circuit, the multi-switching circuit is controlled by the slave temperature control chip 3 to gate only one switching channel at each time, when any switching channel is gated, the temperature sensor connected with the multi-switching circuit can transmit the second temperature information of the corresponding equipment to the slave temperature control chip 3, and therefore the slave temperature control chip 3 is enabled to gate in turn by controlling the switching channels of the multi-switching circuit, and the second temperature information of the multiple equipment correspondingly detected by the multiple temperature sensors is sequentially acquired.
More specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of a first device temperature monitoring circuit according to an embodiment of the present invention. The main temperature control chip 1 is a CPU, the slave temperature control chip 3 is a BMC, the device is a DDR, 16 DDRs are arranged in the system, each DDR is installed in a DIMM (Dual-Inline-Memory-Modules), a high-precision temperature sensor (for example, a temperature sensor of TS5111 model) can be placed beside each DIMM, the multi-SWITCH circuit can include two I3C SWITCH chips, and each I3C SWITCH chip provides 8 SWITCH channels for the access of 8 temperature sensors.
It should be noted that the number of the temperature sensors in the temperature detection circuit 2 is subject to specific requirements, and if the temperature of each DDR needs to be monitored in real time, one temperature sensor needs to be placed beside each DIMM; if the requirement for temperature monitoring is not high, a temperature sensor can be optionally placed between the two DIMMs, and one temperature sensor represents the temperature values of the two DDRs.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a second device temperature monitoring circuit according to an embodiment of the present invention.
As an alternative embodiment, the device temperature monitoring circuit further comprises:
the first data selector MUX _0 is used for connecting the first movable end with the main temperature control chip 1 and connecting the fixed end with the equipment;
the first movable end is connected with the second movable end of the first data selector MUX _0, the second movable end is connected with the temperature detection circuit 2, and the fixed end is connected with the second data selector MUX _1 of the slave temperature control chip 3;
the control circuit is respectively connected with the first data selector MUX _0 and the second data selector MUX _1 and is used for controlling the first data selector MUX _0 to gate the data transmission channel of the main temperature control chip 1 and the second data selector MUX _1 to gate the data transmission channel of the temperature detection circuit 2 when the main temperature control chip 1 has a control requirement on the temperature reading bus or the slave temperature control chip 3 carries out equipment temperature control timeout through the temperature reading bus; when the temperature control chip 3 has a control demand on the temperature reading bus, the first data selector MUX _0 and the second data selector MUX _1 are controlled to gate the data transmission channel of the temperature control chip 3.
Further, the device temperature monitoring circuit of the present application further includes a first data selector MUX _0, a second data selector MUX _1, and a control circuit, and the working principle thereof is as follows:
the first data selector MUX _0 and the second data selector MUX _1 respectively comprise two classified data transmission channels, and the switching of the two classified data transmission channels is controlled by the control circuit. A first classified data transmission channel of the first data selector MUX _0 is connected to the main temperature control chip 1, a second classified data transmission channel is connected to a first classified data transmission channel of the second data selector MUX _1, and a second classified data transmission channel of the second data selector MUX _1 is connected to the temperature detection circuit 2. It can be understood that, when the first sorting data transmission channel of the first data selector MUX _0 is gated, the main temperature control chip 1 may obtain the device temperature information through the temperature reading bus; when the second classified data transmission channel of the second data selector MUX _1 is gated, the slave temperature control chip 3 can acquire equipment temperature information through the temperature detection circuit 2; when the second classified data transmission channel of the first data selector MUX _0 is gated and the first classified data transmission channel of the second data selector MUX _1 is gated, the slave temperature control chip 3 may acquire the device temperature information through the temperature read bus. It can be seen that the master temperature controlling chip 1 has a higher priority for control of the temperature read bus than the slave temperature controlling chip 3.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a control circuit according to an embodiment of the present invention.
As an optional embodiment, the control circuit includes a chip selection circuit, an AND gate AND, a NOT gate NOT, AND a main control chip; wherein:
the output end of the chip selection circuit is respectively connected with the slave temperature control chip 3 AND the first input end of the AND gate AND, the slave temperature control chip 3 is connected with the master control chip, the master control chip is connected with the second input end of the AND gate AND, the output end of the AND gate AND is connected with the input end of the NAND gate NOT, the common end of the output end of the AND gate AND is connected with the control end of the first data selector MUX _0, AND the output end of the NOT gate is connected with the control end of the second data selector MUX _ 1;
the chip selection circuit is used for outputting a low level signal when the main temperature control chip 1 has a control requirement on the temperature reading bus and outputting a high level signal when the slave temperature control chip 3 has a control requirement on the temperature reading bus; the slave temperature control chip 3 is also used for outputting a device temperature control request to the master control chip when receiving the high level signal;
the main control chip is used for judging whether the current condition allows the slave temperature control chip 3 to carry out equipment temperature control through the temperature reading bus after receiving the equipment temperature control request, AND if so, outputting a high-level signal to an AND gate AND; when the main temperature control chip 1 has a control demand on the temperature reading bus or the slave temperature control chip 3 carries out equipment temperature control overtime through the temperature reading bus, a low level signal is output to an AND gate AND.
Specifically, the control circuit of this application includes chip selection circuit, AND gate AND, NOT AND main control chip, AND its theory of operation is:
when the main temperature control chip 1 has a control requirement on the temperature reading bus, the chip selection circuit outputs a low level signal to a first input end (GPIO4) of an AND gate AND, the main control chip outputs a low level signal to a second input end (GPIO1) of the AND gate AND, the AND gate AND outputs a low level signal (GPIO2) to a control end of a first data selector MUX _0, AND at the moment, the first data selector MUX _0 gates a data transmission channel of the main temperature control chip 1; the NOT gate NOT outputs a high level signal (GPIO3) to the control terminal of the second data selector MUX _1, and the second data selector MUX _1 gates the data transmission channel of the temperature detection circuit 2.
When the slave temperature control chip 3 has a control requirement on the temperature reading bus, the chip selection circuit outputs a high level signal to the first input end of the AND gate AND, the chip selection circuit also outputs a high level signal to the slave temperature control chip 3, AND the slave temperature control chip 3 outputs a device temperature control request (IRQ _ SPD) to the master control chip when receiving the high level signal. After receiving the device temperature control request, the main control chip judges whether the current condition allows the slave temperature control chip 3 to perform device temperature control through the temperature reading bus, if the current condition allows the device temperature control, the main control chip outputs a high-level signal to the second input end of the AND gate AND, the AND gate AND outputs the high-level signal to the control end of the first data selector MUX _0, AND at the moment, the first data selector MUX _0 gates the data transmission channel of the slave temperature control chip 3. The NOT gate NOT outputs a low level signal to the control terminal of the second data selector MUX _1, and at this time, the second data selector MUX _1 also gates the data transmission channel of the slave temperature controlled chip 3.
When the slave temperature control chip 3 carries out equipment temperature control timeout through the temperature reading bus (namely, the master temperature control chip 1 does not acquire equipment temperature information for a long time, AND the master temperature control chip 1 can remind the master control chip that the master control chip needs to take back the control right of the temperature reading bus), the master control chip can judge that the system has high risk AND forcibly outputs a low level signal to the second input end of the AND gate AND, AND gate AND outputs the low level signal to the control end of the first data selector MUX _0, AND at the moment, the first data selector MUX _0 gates a data transmission channel of the master temperature control chip 1; the NOT gate NOT outputs a high level signal to the control terminal of the second data selector MUX _1, and at this time, the second data selector MUX _1 gates the data transmission channel of the temperature detection circuit 2.
In addition, the main control chip of the present application may select a PCH (Platform Controller Hub, integrated south bridge).
As an alternative embodiment, the chip selection circuit includes a Debug Header, a first resistor R1 and a second resistor R2; wherein:
the 2Pin of the Debug Header is connected with the first end of a first resistor R1, the common end of the Debug Header is used as the output end of the chip selection circuit, the second end of a first resistor R1 is grounded, the 3Pin of the Debug Header is connected with the first end of a second resistor R2, the second end of the second resistor R2 is connected with a direct-current power supply, and the 1Pin of the Debug Header is suspended; when the main temperature control chip 1 has a control requirement on a temperature reading bus, a jump cap of the Debug Header is buckled on the Pin 1-2; when the temperature reading bus needs to be controlled from the temperature control chip 3, the jump cap of the Debug Header is buckled on the Pin 2-3.
Specifically, the chip selection circuit of the present application includes a Debug Header, a first resistor R1 and a second resistor R2, and its operating principle is:
when the jump cap of the Debug Header is buckled on the Pin1-2, the hardware is pulled down, and the 2 nd Pin Pin of the Debug Header is low level, that is, the GPIO4 is low level. When the jump cap of the Debug Header is buckled on the Pin2-3, the Pin2 of the Debug Header is high, i.e., the GPIO4 goes high.
As an alternative embodiment, the AND gate AND the NOT gate NOT are integrated in the slave temperature control chip 3.
Specifically, as shown in fig. 5, both the AND gate AND the NOT gate of the present application can be integrated in the slave temperature control chip 3, so as to optimize the circuit layout design.
As an optional embodiment, the control circuit further includes a switching tube Q, a third resistor R3, and a light emitting diode LED; wherein:
the first end of the third resistor R3 is respectively connected with the main control chip, the second input end of the AND gate AND AND the control end of the switching tube Q, the first end of the switching tube Q is connected with the cathode of the light emitting diode LED, the anode of the light emitting diode LED is connected with a direct current power supply, AND the second end of the switching tube Q is grounded; the switching tube Q is a switching tube Q with a control end input with a high level on and a low level off.
Specifically, the control circuit of this application still includes switch tube Q, third resistance R3 and emitting diode LED, and its theory of operation is:
when the GPIO5 port of the main control chip outputs low level, the switching tube Q is switched off, and the light emitting diode LED does not emit light; when the GPIO5 port of the main control chip outputs high level, the switch tube Q is conducted, and the light emitting diode LED emits light. That is to say, when the master temperature control chip 1 holds the control right to the temperature reading bus, the light emitting diode LED does not emit light, when the slave temperature control chip 3 holds the control right to the temperature reading bus, the light emitting diode LED emits light, if the master control chip judges that the system has a high risk and forcibly lowers the level of the GPIO5 port, the light emitting diode LED goes out, and the user can be reminded to overtime the device temperature control through the temperature reading bus from the temperature control chip 3, so that the system monitoring has a risk.
As an alternative embodiment, the slave temperature control chip 3 is connected with the master temperature control chip 1;
the slave temperature control chip 3 is specifically configured to, when a heat dissipation strategy currently corresponding to the device changes, obtain first temperature information of the device from the master temperature control chip 1, use a difference value between the first temperature information and the second temperature information as a temperature compensation value, and perform temperature compensation on subsequently obtained second temperature information based on the temperature compensation value.
Specifically, the first temperature information of the equipment is detected by an internal temperature sensor integrated in the equipment, so that the accuracy is high; the second temperature information of the device is detected by the temperature detection circuit 2 disposed outside the device, and is affected by the external heat sink, and is not accurate enough, so the first temperature information of the device can be used as a calibration reference value of the second temperature information of the device. Moreover, the heat dissipation strategies of the external heat dissipation device are different (for example, the fan rotation speeds are different), and the influence values on the second temperature information of the device detected by the temperature detection circuit 2 are also different, so that when the current heat dissipation strategy of the device changes, the temperature compensation value should be updated once again, so that the subsequent temperature compensation is performed on the second temperature information of the device through the second temperature information which is the second temperature information plus the updated temperature compensation value, and the temperature detection accuracy of the temperature detection circuit mode is improved.
More specifically, the slave temperature Control chip 3 may specifically obtain the first temperature information of the device from the master temperature Control chip 1 in an in-band manner through PECI (Platform Environment Control Interface, a one-line bus).
As an optional embodiment, the slave temperature control chip 3 is further configured to perform an alarm of abnormal device temperature and control the system to shut down when the temperature detection circuit 2 detects that the temperature of the device is abnormal, but the system in which the device is located does not perform the protection action of abnormal device temperature.
Further, if the internal temperature sensor integrated in the device has a problem, the device temperature monitoring is abnormal, and the slave temperature control chip 3 monitors the device temperature in real time through the temperature detection circuit 2, so that the device temperature abnormality can be detected in time, if the system where the device is located does not perform a device temperature abnormality protection action, the slave temperature control chip 3 can perform a device temperature abnormality alarm, and the system is controlled to shut down, so as to protect the device and the system.
In addition, the method and the device can display the temperature of the equipment in real time through developing a web interface for a user to check.
The application also provides a server system which comprises the equipment and any one of the equipment temperature monitoring circuits.
For the introduction of the server system provided in the present application, please refer to the above embodiments of the temperature monitoring circuit, which are not described herein again.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A device temperature monitoring circuit, comprising:
the main temperature control chip is connected with a temperature reading bus of the equipment and used for acquiring first temperature information of the equipment through the temperature reading bus so as to realize temperature monitoring of the equipment;
the temperature detection circuit is arranged outside the equipment and used for detecting second temperature information of the equipment;
and the slave temperature control chip is connected with the temperature detection circuit and used for carrying out temperature compensation on the second temperature information based on the current corresponding heat dissipation strategy of the equipment and realizing temperature monitoring of the equipment based on the second temperature information after temperature compensation.
2. The device temperature monitoring circuit according to claim 1, wherein when the number of the devices is plural, the temperature detection circuit includes:
a plurality of temperature sensors provided corresponding to the plurality of devices;
the multi-switch circuit is respectively connected with the plurality of temperature sensors and the slave temperature control chip;
correspondingly, the slave temperature control chip is specifically configured to sequentially acquire second temperature information of the multiple devices correspondingly detected by the multiple temperature sensors by controlling the switching channels of the multi-switching circuit to be gated in turn.
3. The device temperature monitoring circuit of claim 1, further comprising:
the first data selector is used for connecting a first movable end with the main temperature control chip and connecting a stationary end with the equipment;
the first movable end is connected with the second movable end of the first data selector, the second movable end is connected with the temperature detection circuit, and the fixed end is connected with the secondary temperature control chip;
the control circuit is respectively connected with the first data selector and the second data selector and is used for controlling the first data selector to gate a data transmission channel of the main temperature control chip and controlling the second data selector to gate a data transmission channel of the temperature detection circuit when the main temperature control chip has a control requirement on the temperature reading bus or the slave temperature control chip carries out equipment temperature control timeout through the temperature reading bus; and when the slave temperature control chip has a control requirement on the temperature reading bus, controlling the first data selector and the second data selector to gate the data transmission channel of the slave temperature control chip.
4. The device temperature monitoring circuit of claim 3, wherein the control circuit comprises a chip selection circuit, an AND gate, a NOT gate, and a main control chip; wherein:
the output end of the chip selection circuit is respectively connected with the first input ends of the slave temperature control chip and the AND gate, the slave temperature control chip is connected with the master control chip, the master control chip is connected with the second input end of the AND gate, the output end of the AND gate is connected with the input end of the NOT gate, the common end of the AND gate is connected with the control end of the first data selector, and the output end of the NOT gate is connected with the control end of the second data selector;
the chip selection circuit is used for outputting a low level signal when the main temperature control chip has a control requirement on the temperature reading bus and outputting a high level signal when the slave temperature control chip has a control requirement on the temperature reading bus; the slave temperature control chip is also used for outputting a device temperature control request to the master control chip when receiving the high level signal;
the master control chip is used for judging whether the slave temperature control chip is allowed to carry out equipment temperature control through the temperature reading bus under the current condition after receiving the equipment temperature control request, and if so, outputting a high level signal to the AND gate; and when the main temperature control chip has a control requirement on the temperature reading bus or the slave temperature control chip carries out equipment temperature control timeout through the temperature reading bus, outputting a low level signal to the AND gate.
5. The device temperature monitoring circuit of claim 4, wherein the chip select circuit comprises a Debug Header, a first resistor, and a second resistor; wherein:
a 2Pin of the Debug Header is connected with a first end of the first resistor, a common end of the Debug Header is used as an output end of the chip selection circuit, a second end of the first resistor is grounded, a 3Pin of the Debug Header is connected with a first end of the second resistor, a second end of the second resistor is connected with a direct-current power supply, and a 1Pin of the Debug Header is suspended; when the main temperature control chip has a control requirement on the temperature reading bus, a jump cap of the Debug Header is buckled on the Pin 1-2; when the slave temperature control chip has a control requirement on the temperature reading bus, the jump cap of the Debug Header is buckled on the Pin 2-3.
6. The device temperature monitoring circuit of claim 4, wherein the AND gate and the NOT gate are both integrated into the slave temperature control chip.
7. The device temperature monitoring circuit according to claim 4, wherein the control circuit further comprises a switching tube, a third resistor and a light emitting diode; wherein:
the first end of the third resistor is respectively connected with the main control chip, the second input end of the AND gate and the control end of the switch tube, the first end of the switch tube is connected with the cathode of the light-emitting diode, the anode of the light-emitting diode is connected with a direct current power supply, and the second end of the switch tube is grounded; the switch tube is a switch tube with a control end input with a high level for switching on and a low level for switching off.
8. The device temperature monitoring circuit of claim 1, wherein the slave temperature control chip is connected to the master temperature control chip;
the slave temperature control chip is specifically configured to, when a heat dissipation strategy currently corresponding to the device changes, obtain first temperature information of the device from the master temperature control chip, use a difference value between the first temperature information and the second temperature information as a temperature compensation value, and perform temperature compensation on subsequently obtained second temperature information based on the temperature compensation value.
9. The device temperature monitoring circuit according to claim 1, wherein the slave temperature control chip is further configured to perform a device temperature abnormality alarm and control a system shutdown when the temperature detection circuit detects that the temperature of the device is abnormal but the system in which the device is located does not perform a device temperature abnormality protection action.
10. A server system comprising a device and a device temperature monitoring circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011444886.0A CN112463539A (en) | 2020-12-11 | 2020-12-11 | Equipment temperature monitoring circuit and server system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011444886.0A CN112463539A (en) | 2020-12-11 | 2020-12-11 | Equipment temperature monitoring circuit and server system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112463539A true CN112463539A (en) | 2021-03-09 |
Family
ID=74801313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011444886.0A Withdrawn CN112463539A (en) | 2020-12-11 | 2020-12-11 | Equipment temperature monitoring circuit and server system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112463539A (en) |
-
2020
- 2020-12-11 CN CN202011444886.0A patent/CN112463539A/en not_active Withdrawn
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Application publication date: 20210309 |