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CN112490138B - Preparation method of chip structure - Google Patents

Preparation method of chip structure Download PDF

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Publication number
CN112490138B
CN112490138B CN202011487565.9A CN202011487565A CN112490138B CN 112490138 B CN112490138 B CN 112490138B CN 202011487565 A CN202011487565 A CN 202011487565A CN 112490138 B CN112490138 B CN 112490138B
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China
Prior art keywords
carrier
bonding
electrically connected
active element
present application
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CN202011487565.9A
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CN112490138A (en
Inventor
卢建
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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Priority to CN202011487565.9A priority Critical patent/CN112490138B/en
Publication of CN112490138A publication Critical patent/CN112490138A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The embodiment of the application provides a preparation method of a chip structure, which comprises the following steps: the active element is fixed on the surface of the first side of the supporting body, a plurality of first bonding wires are formed on the side, deviating from the supporting body, of the active element, a first packaging layer for packaging the active element and the plurality of first bonding wires is formed on the side, deviating from the supporting body, of the active element, the problem that the active element is embedded into the passive substrate to form an active substrate structure is avoided, the production period is long, the cost is high, the thickness of the first packaging layer is removed from the side, deviating from the supporting body, of the first packaging layer, any one of the plurality of first bonding wires forms two independent second bonding wires, the active element and/or the electric connection end of the supporting body is led out through the second bonding wires, the active element and/or the electric connection end of the supporting body are convenient to be electrically connected with the first element, and the phenomenon that the packaging reliability of a chip structure is poor due to the fact that the active element and the first element are electrically connected and stacked in a punching and metal plating mode is avoided.

Description

Preparation method of chip structure
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a preparation method of a chip structure.
Background
At present, with the continuous development of semiconductor chip packaging technology, the integration level of a chip is higher and the size of the chip is smaller, so that the packaging of the chip is gradually changed from traditional planar packaging (2D packaging) to 2.5D packaging or 3D packaging.
The 2.5D package or the 3D package currently popular in the industry mostly adopts a stacked manner, in the prior art, the 2.5D package or the 3D package is generally embedded, an underlying structure is embedded into a passive substrate to form an active substrate structure, then a via between the underlying structure and an upper structure is formed by a punching manner (such as TSV, TMV), and finally metal is plated in a through hole to electrically connect the underlying structure and the upper structure. However, the packaging reliability of the chip structure formed by the electric connection among different stacking layers realized by the modes of embedding, punching and electroplating metal is poor, the production period is long, and the cost is high.
Disclosure of Invention
Therefore, the embodiment of the application provides a preparation method of a chip structure, which is used for improving the packaging reliability of the chip structure, shortening the production period and reducing the cost.
In order to achieve the above object, the embodiment of the present application provides the following technical solutions:
A method of fabricating a chip structure, comprising:
fixing an active element on the first side surface of the carrier;
forming a plurality of first bonding wires on one side of the active element, which is away from the carrier, wherein two connecting ends of the first bonding wires are electrically connected to any one of the carrier and the active element, and the height of the first bonding wires is higher than the surface of the active element, which is away from the carrier;
Forming a first packaging layer on one side of the active element, which is away from the carrier, wherein the first packaging layer packages the active element and the plurality of first bonding wires;
Removing the thickness of the first packaging layer part and the first bonding wire part from one side of the first packaging layer, which is away from the carrier, until any one of the first bonding wires forms two independent second bonding wires, and exposing one side end surface of the second bonding wire, which is away from the carrier, of the first packaging layer after removing part of the thickness;
forming a plurality of first bonding pads on one side, away from the carrier, of the first packaging layer, wherein the plurality of first bonding pads are in one-to-one correspondence with and are electrically connected with the plurality of second bonding wires;
And fixing a first element on one side of the first bonding pad, which is away from the first packaging layer, wherein the first element is electrically connected with at least one first bonding pad.
Optionally, both connection ends of the first bonding wire are electrically connected with the carrier; or, the two connecting ends of the first bonding wire are electrically connected with the active element; or, one connecting end of the first bonding wire is electrically connected with the carrier, and the other connecting end is electrically connected with the active element.
Optionally, the electrical connection end of the first element faces the active element, and the first element is electrically connected with the first bonding pad through a ball implant.
Optionally, the first element electrical connection end faces away from the active element, and the first element is electrically connected with the first bonding pad through a third bonding wire.
Optionally, the first element is an active element, or the first element is a passive element.
Optionally, the method further comprises:
Before a first element is fixed on the side, away from the first packaging layer, of the first bonding pad, at least one second element is fixed on the side, away from the first packaging layer, of the first bonding pad, and the first element is fixed on the side, away from the active element, of the second element;
the second element is electrically connected with at least one first bonding pad, and the second element is electrically connected with the first bonding pad through a fourth bonding wire.
Optionally, the second element is an active element, or the second element is a passive element.
Optionally, the active element is adhered to the first side surface of the carrier.
Optionally, the supporting body is a substrate, or the supporting body is a metal frame.
Optionally, the method further comprises:
a second encapsulation layer is formed encapsulating at least the first element and the void between the first encapsulation layers.
In the method for manufacturing the chip structure provided by the embodiment of the application, an active element is fixed on the surface of the first side of a carrier, a plurality of first bonding wires are formed on one side of the active element, which is far away from the carrier, two connecting ends of the first bonding wires are electrically connected to at least one of the carrier and the active element, a first packaging layer is formed on one side of the active element, which is far away from the carrier, and the active element and the plurality of first bonding wires are packaged by the first packaging layer, so that a packaging whole is formed, the active element is packaged in the first packaging layer, then the thickness of a part of the first packaging layer is removed from one side of the first packaging layer, which is far away from the carrier, so that any one of the plurality of first bonding wires is formed into two independent second bonding wires, the active element and/or the electric connecting ends of the carrier are led out through the second packaging layer, the active element and the plurality of first bonding wires are packaged by the first packaging layer, and the first bonding wires are connected with the first end face, and the first bonding wires are connected with the carrier or the first bonding wires, and the final electric bonding pads are connected with the active element and the first bonding wires or the first bonding wires.
Therefore, in the method for manufacturing the chip structure provided by the embodiment of the application, the electrical connection ends of the active elements are led out through the plurality of second bonding wires, the first packaging layer is formed, and the first packaging layer exposes the end faces of the second bonding wires, so that the stacked active elements and the first elements are electrically connected by the second bonding wires, the phenomenon of poor packaging reliability of the chip structure caused by electrically connecting the stacked active elements and the first elements in a punching and metal plating mode is avoided, and the packaging reliability of the chip structure is improved.
In addition, in the method for manufacturing the chip structure provided by the embodiment of the application, the active element is fixed on the surface of the carrier, and then the active element and/or the electric connection end of the carrier is led out through the second bonding wire so as to be electrically connected with the first element, and finally the active element and the plurality of second bonding wires are packaged through the first packaging layer to form a packaging whole, so that the active element is packaged in the first packaging layer to form an active substrate structure, and the problems of longer production period and higher cost caused by embedding the active element into the passive substrate to form the active substrate structure are solved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for fabricating a chip structure according to an embodiment of the present application;
fig. 2 to 17 are schematic structural diagrams after each process step in the method for manufacturing a chip structure according to an embodiment of the present application is completed;
fig. 18 is a schematic structural diagram of a chip structure according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
As described in the background section, the existing chip structure formed by electrically connecting different stacking levels through embedding, punching and metal plating is poor in packaging reliability, long in production period and high in cost.
The inventor researches and discovers that the method is long in production period and high in manufacturing cost due to the mode that the active element is embedded into the passive substrate to form the active substrate structure in the existing scheme. Moreover, the problem of hole punching offset during the subsequent hole punching process and poor electroplating during the metal electroplating process in the through hole can occur, which results in poor packaging reliability of the chip structure.
Therefore, the embodiment of the application provides a preparation method of a chip structure, which is used for improving the packaging reliability of the chip structure, shortening the production period and reducing the cost. The following describes a method for manufacturing a chip structure according to an embodiment of the present application with reference to the accompanying drawings.
Specifically, as shown in fig. 1, the method for manufacturing a chip structure provided by the embodiment of the application includes:
s10: an active element 20 is secured to a first side surface of the carrier 10.
On the basis of the above embodiment, in one embodiment of the present application, the carrier is a substrate, for example, a PCB board, and in another embodiment of the present application, the carrier may be a metal frame, so as to further reduce the manufacturing cost of the chip structure. Alternatively, in one embodiment of the present application, the carrier is a copper frame, which is not limited in this regard, as the case may be.
On the basis of any of the foregoing embodiments, in one embodiment of the present application, the active element is an Integrated Circuit (IC), which is not limited in this aspect of the present application, and in other embodiments of the present application, the active element may also be other active electronic elements, where appropriate.
On the basis of any one of the above embodiments, in one embodiment of the present application, fixing the active element on the first side surface of the carrier includes: the active element is fixed on the first side surface of the carrier by using a bonding process, but the application is not limited thereto, and in other embodiments of the application, the active element may be fixed on the first side surface of the carrier by using other processes, as the case may be.
Specifically, as shown in fig. 2, in the embodiment of the present application, by means of adhesion, the fixing of the active element 20 on the first side surface of the carrier 10 includes:
forming a first adhesive layer 21 on a first side surface of the carrier 10;
The active element 20 is placed on the side of the first adhesive layer 21 facing away from the carrier 10 to fix the active element to the carrier first side surface with the first adhesive layer.
In another embodiment of the present application, the fixing the active element 20 on the first side surface of the carrier 10 by means of adhesion further includes: the first adhesive layer 21 is formed on the first side surface of the active element, and then a side of the first adhesive layer 21 facing away from the active element 20 is adhered to the first side surface of the carrier, so that the first adhesive layer fixes the active element on the first side surface of the carrier.
It should be noted that, in the preparation method provided by the embodiment of the application, the active element is fixed on the first side surface of the supporting body, and then the active element is encapsulated by the first encapsulation layer, so that the active substrate structure is formed.
S20: a plurality of first bonding wires 4 are formed on one side of the active element 20 away from the carrier 10, two connection ends of the first bonding wires 4 are electrically connected to any one of the carrier and the active element, and the height of the first bonding wires 4 is higher than the surface of one side of the active element 20 away from the carrier 10.
On the basis of the above embodiment, in one embodiment of the present application, as shown in fig. 3, both connection ends of the first bonding wire 4 are electrically connected to the carrier 10; in another embodiment of the present application, as shown in fig. 4, both connection ends of the first bonding wire 4 are electrically connected to the active element 20; in yet another embodiment of the present application, as shown in fig. 5, one connection end of the first bonding wire 4 is electrically connected to the carrier 10, and the other connection end is electrically connected to the active element 20, which is not limited in this application, and it is only necessary to ensure that the two connection ends of the first bonding wire are electrically connected to either one of the carrier and the active element, as the case may be.
S30: as further shown in fig. 3-5, a first encapsulation layer 40 is formed on a side of the active element 20 facing away from the carrier 10, and the first encapsulation layer 40 encapsulates the active element 20 and the plurality of first bonding wires 4.
On the basis of the above embodiment, in one embodiment of the present application, the first encapsulation layer is a plain epoxy resin film, in another embodiment of the present application, the material of the first encapsulation layer is a plastic encapsulation material, but the present application is not limited thereto, and in other embodiments of the present application, the material of the first encapsulation layer may be other encapsulation materials, and it is only required to ensure that the first encapsulation layer encapsulates the active element and the plurality of first bonding wires to form a package whole, and isolate the active element from the external environment, as the case may be.
S40: as shown in fig. 6 to 8, the thickness of the first package layer and the first bonding wire portion are removed from the side, away from the carrier, of the first package layer until one of the first bonding wires forms two independent second bonding wires, and the end face, away from the carrier, of the second bonding wire is exposed from the first package layer after the removal of the thickness.
In one embodiment of the present application, removing the first encapsulation layer portion thickness and the first wire bond portion from a side of the first encapsulation layer facing away from the carrier comprises: and polishing the side, away from the carrier, of the first encapsulation layer by adopting a polishing process to remove the thickness of the part, away from the carrier, of the first encapsulation layer and the first bonding wire part, but the application is not limited to this, and in other embodiments of the application, other processes can be adopted to remove the thickness of the part of the first encapsulation layer and the first bonding wire part from the side, away from the carrier, of the first encapsulation layer, as the case may be.
In the above embodiment, when the first package layer encapsulates the active element and the plurality of first bonding wires, the plurality of first bonding wires are located inside the first package layer, and when the first package layer is removed from the side of the first package layer facing away from the carrier, the first bonding wires are located within the removed portion of the first package layer, so that the first bonding wires can be removed from the side of the first package layer facing away from the carrier, so that one first bonding wire forms two independent second bonding wires, i.e., the plurality of first bonding wires form multiple independent second bonding wires.
Specifically, on the basis of the above embodiment, in one embodiment of the present application, both connection ends of the first bonding wires are electrically connected to the carrier, and when the thickness of the first packaging layer is removed from the side of the first packaging layer away from the carrier, so that the plurality of first bonding wires 4 form a plurality of independent second bonding wires 30, as shown in fig. 6, the plurality of second bonding wires 30 are electrically connected to the carrier 10, and the electrical connection ends of the carrier are led out through the second bonding wires, so that the first element is electrically connected to the carrier through the second bonding wires; in another embodiment of the present application, both connection ends of the first bonding wires are electrically connected to the active element, and when the first package layer is removed from the side of the first package layer away from the carrier, so that the plurality of first bonding wires 4 form a plurality of independent second bonding wires 30, as shown in fig. 7, the plurality of second bonding wires 30 are electrically connected to the active element 20, and the electrical connection ends of the active element are led out through the second bonding wires, so that the first element is electrically connected to the active element through the second bonding wires; in yet another embodiment of the present application, one connection end of the first bonding wire is electrically connected to the carrier, the other connection end is electrically connected to the active element, and when the first encapsulation layer is removed from the side of the first encapsulation layer facing away from the carrier, so that the plurality of first bonding wires 4 form a plurality of independent second bonding wires 30, as shown in fig. 8, the plurality of second bonding wires 30 includes at least one first sub bonding wire 31 and at least one second sub bonding wire 32, the first sub bonding wire 31 is electrically connected to the active element 20, the second sub bonding wire 32 is electrically connected to the carrier 10 to lead out the electrical connection end of the active element through the first sub bonding wire, and the second sub bonding wire leads out the electrical connection end of the carrier, so that the first element is electrically connected to the active element and the carrier through the first sub bonding wire and the second sub bonding wire, respectively.
It should be noted that if an active element is embedded into a substrate to form an active substrate structure, and then electrical connection between different elements is achieved by punching and metal plating, the production period is generally more than 4 weeks, and the time is long, in the embodiment of the present application, the active element is fixed on the first side surface of the carrier, then the active element and/or the electrical connection end of the carrier are led out through the plurality of second bonding wires, finally the active element and the plurality of second bonding wires are encapsulated by using the first encapsulation layer, the active element is encapsulated in the first encapsulation layer to form an active substrate structure, the active element is prevented from being embedded into the substrate through the second bonding wires and the subsequent first elements, and the stacked active element and the first elements are not required to be electrically connected in a punching and metal plating mode, so that the production period can be shortened to 1-2 days, the production period of the chip structure is greatly shortened, and the production cost is reduced.
As shown in fig. 9, on the basis of any one of the above embodiments, in one embodiment of the present application, the preparation method further includes:
While forming a plurality of first bonding wires on the side of the active element 20 away from the carrier 10, forming a plurality of sixth bonding wires 33 on the side of the active element 20 away from the carrier 10, wherein one connecting end of the sixth bonding wires 33 is electrically connected with the carrier 10, the other connecting end is electrically connected with the active element 20, the height of the sixth bonding wires 33 is smaller than the height of the first bonding wires 4, and the first encapsulation layer 40 completely encapsulates the sixth bonding wires 33.
It should be noted that, in the embodiment of the present application, the sixth bonding wire may be formed before the first bonding wire, may be formed later than the first bonding wire, or may be formed simultaneously with the first bonding wire.
It should be further noted that, in an embodiment of the present application, the first packaging layer completely encapsulates the sixth bonding wire, so as to avoid that one end of the sixth bonding wire, which is away from the carrier, is exposed outside the first packaging layer, and is oxidized, contaminated or shorted with other electrical elements by the external environment, which affects the performance of the chip structure.
Moreover, in the embodiment of the present application, the height of the bonding wires can be controlled to control the bonding wires to be exposed, and as shown in fig. 9, since the height of the sixth bonding wire 33 is smaller than the height of the first bonding wire 4, when the thickness of the first packaging layer 40 and the first bonding wire portion are removed from the side of the first packaging layer 40 away from the carrier 10, only the thickness of the first packaging layer needs to be controlled to be removed, so that the portion of the first bonding wire 4 located separately on the first packaging layer 40 can be removed, so that two independent second bonding wires 30 are formed by one first bonding wire 4, and the sixth bonding wire 33 is still completely wrapped by the first packaging layer 40.
S50: as shown in fig. 10, a plurality of first bonding pads 50 are formed on a side of the first encapsulation layer 40 facing away from the carrier 10, and the plurality of first bonding pads 50 are in one-to-one correspondence with and electrically connected to the plurality of second bonding wires 30.
In one embodiment of the present application, forming a plurality of first pads on a side of the first encapsulation layer facing away from the carrier includes: forming a plurality of first bonding pads on a side of the first encapsulation layer, which is away from the carrier, by adopting an electroplating process, and in another embodiment of the present application, forming a plurality of first bonding pads on a side of the first encapsulation layer, which is away from the carrier, includes: the electroless plating process is adopted to form a plurality of first bonding pads on the side, away from the carrier, of the first encapsulation layer, but the application is not limited thereto, and in other embodiments of the application, other forming processes may be adopted to form a plurality of first bonding pads on the side, away from the carrier, of the first encapsulation layer, as the case may be.
It should be noted that, electroplating (Electroplating) is a process of plating a thin layer of other metals or alloys on the surface of some metals by using the electrolysis principle, that is, the electroplating process is a process of adhering a metal film on the surface of the metal or other material workpiece by using the electrolysis, thereby playing roles of preventing oxidation (such as rust) of the metal, improving the wear resistance, conductivity, reflectivity, corrosion resistance (such as copper sulfate) of the metal, improving the appearance, and the like; electroless plating (Electroless plating), also known as electroless plating, is a process that uses strong reducing agents in solutions containing metal ions to reduce the metal ions to metal and deposit the metal ions on the surfaces of various materials to form a dense coating without the need for electrical energization, based on the principle of redox reactions.
Specifically, in one embodiment of the present application, forming a plurality of first pads on a side of the first encapsulation layer facing away from the carrier includes:
Coating a layer of photoresist on one side of the first packaging layer, which is away from the carrier, so as to form a first photoresist layer;
Exposing and developing the first photoresist layer to form a first photoresist pattern exposing positions of a plurality of first bonding pads to be formed, wherein the positions of the first bonding pads correspond to the positions of the second bonding wires deviating from one side end surface of the carrier;
Forming a metal layer on one side of the first photoresist pattern, which is away from the first packaging layer, by adopting an electroplating process;
And removing the first photoresist pattern and the part of the metal layer, which is positioned on the surface of the first photoresist pattern, so as to form a plurality of first bonding pads on one side of the first packaging layer, which is away from the carrier, wherein the plurality of first bonding pads are in one-to-one correspondence with the plurality of second bonding wires and are electrically connected.
In the embodiment of the present application, the first bonding pads are located on a surface of the first packaging layer, which is opposite to the carrier, and are in one-to-one correspondence with and electrically connected to the end surfaces of the plurality of second bonding wires, which are opposite to the carrier, so that the first bonding pads are used as the electrical connection ends of the active element and/or the carrier, and the first element is electrically connected to the plurality of second bonding wires through the electrical connection with the plurality of first bonding pads, thereby realizing the electrical connection with the active element and/or the carrier.
In the embodiment of the present application, the second bonding wires are electrically connected to the first element through the first bonding pad, so that the problem that the difficulty of the electrical connection process between the first element and the second bonding wires is high and the electrical connection performance between the first element and the second bonding wires is affected due to the fact that the end faces of the plurality of second bonding wires, which face away from the carrier, are smaller can be avoided.
S60: a first element 60 is fixed on the side of the first bonding pad 50 facing away from the first encapsulation layer 40, and the first element 60 is electrically connected to the first bonding pad 50.
It should be noted that, on the basis of the above embodiment, in one embodiment of the present application, the first element is an active element; in another embodiment of the present application, the first element is a passive element, which is not limited in this regard, and is specifically determined according to the requirements of the chip structure.
Based on the above embodiments, in one embodiment of the present application, the electrical connection ends of the first element 60 are oriented toward the active element 20 so that the electrical connection path between the first element and the active element (and/or the carrier) is short.
Specifically, in one embodiment of the present application, as shown in fig. 11, the plurality of second bonding wires 30 are electrically connected to the active element 20, in this embodiment of the present application, a side of the active element facing the first element has an electrical connection end, the electrical connection end of the active element is electrically connected to the second bonding wire, and the other end of the second bonding wire is electrically connected to the electrical connection end of the first element facing the active element through the first bonding pad, so as to achieve electrical connection between the first element and the active element, and make an electrical connection path between the first element and the active element shorter.
In another embodiment of the present application, as shown in fig. 12, the plurality of second bonding wires 30 are electrically connected to the carrier 10, in this embodiment of the present application, a side of the carrier facing the first element has an electrical connection end, the electrical connection end of the carrier is electrically connected to the second bonding wire, and the other end of the second bonding wire is electrically connected to the electrical connection end of the first element facing the active element through the first bonding pad, so as to achieve electrical connection between the first element and the carrier, and make an electrical connection path between the first element and the carrier shorter.
In yet another embodiment of the present application, as shown in fig. 13, the plurality of second bonding wires 30 includes a first sub-bonding wire 31 and a second sub-bonding wire 32, where the first sub-bonding wire 31 is electrically connected to the active element 20, the second sub-bonding wire 32 is electrically connected to the carrier 10, in an embodiment of the present application, a side of the active element facing the first element has an electrical connection end, the electrical connection end of the active element is electrically connected to the first sub-bonding wire, and the other end of the first sub-bonding wire is electrically connected to the electrical connection end of the first element facing the active element through the first bonding pad, so as to implement the electrical connection between the first element and the active element, and make an electrical connection path between the first element and the active element shorter; the bearing body is provided with an electric connection end towards one side of the first element, the electric connection end of the bearing body is electrically connected with the second sub bonding wire, and the other end of the second sub bonding wire is electrically connected with the electric connection end of the first element towards one side of the active element through the first bonding pad, so that the electric connection of the first element and the bearing body is realized, and the electric connection path between the first element and the bearing body is shorter.
On the basis of the above embodiment, in one embodiment of the present application, as further shown in fig. 13, when the electrical connection end of the first element 60 faces the active element 20, the first element 60 is electrically connected to the first pad 50 through the ball 61.
On the basis of the foregoing embodiments, in one embodiment of the present application, the electrically connecting the first element to the first pad through the ball implant includes: a Reflow (Reflow) process is used to electrically connect the first element to the first pad through the ball stud, but the present application is not limited thereto, and the present application is specifically limited as the case may be.
Reflow (Reflow) is performed by remelting solder that was previously dispensed onto the first pad, so that the solder on the first pad is melted and then fusion-soldered with the first element; or, the reflow soldering is to melt the solder by heating so as to utilize the melted solder to weld the first element and the first bonding pad which are already attached together, and then cool the solder by cooling of the reflow soldering so as to solidify the first element and the first bonding pad together; or, reflow soldering is to melt solder on the first element and fuse the solder with the first bonding pad by re-melting the solder pre-distributed on the electrical connection end of the first element.
Specifically, in one embodiment of the present application, the electrical connection between the first element and the first pad through the ball implant includes:
Ball implantation is carried out on the surface of one side of the first element, which is provided with the electric connecting end, and the ball implantation corresponds to the electric connecting end of the first element one by one and is electrically connected with the electric connecting end of the first element;
and adopting a reflow soldering process to electrically connect one side surface of the first element, on which the balls are planted, with one side surface of the first bonding pad, which is away from the first packaging layer, wherein the planted balls are in one-to-one correspondence with the first bonding pads and are electrically connected, so that the first element is electrically connected with the first bonding pads through the planted balls.
On the basis of the above embodiment, in one embodiment of the present application, as further shown in fig. 13, the preparation method further includes:
A second encapsulation layer 41 is formed encapsulating at least the void between the first element 60 and the first encapsulation layer 40.
Specifically, in the embodiment of the present application, the electrical connection end of the first element 60 faces the active element 20 (i.e., the electrical connection end of the first element 60 faces the first packaging layer 40), the first bonding pad 50 is located on one side of the first packaging layer 40 facing away from the carrier, and the electrical connection end of the first element 60 is electrically connected with the first bonding pad 50 through the ball-planting 61, so that the ball-planting 61 and the first bonding pad 50 are disposed in a gap between the first element 60 and the first packaging layer 40, and the second packaging layer 41 can encapsulate the ball-planting 61 and the first bonding pad 50 to protect the ball-planting and the first bonding pad from being separated from each other in a subsequent process, so that the chip structure is damaged.
On the basis of the above embodiments, in one embodiment of the present application, the material of the second encapsulation layer is Underfill (Underfill), but the present application is not limited thereto, and in other embodiments of the present application, the material of the second encapsulation layer may be other encapsulation materials, as the case may be.
In another embodiment of the present application, as shown in fig. 14, when the electrical connection end of the first element 60 faces the active element 20, the preparation method further includes: the third encapsulation layer 42 is formed on the side of the first encapsulation layer 40 away from the carrier 10, and the third encapsulation layer 42 encapsulates the first element 60, the ball 61 and the first bonding pad 50, so as to protect the ball and the first bonding pad and protect the first element, but the application is not limited thereto, and the application is not limited thereto as the case may be.
On the basis of the above embodiments, in one embodiment of the present application, the third encapsulation layer is a flavored plain epoxy resin film, but the present application is not limited thereto, and is specifically limited thereto as the case may be.
In another embodiment of the present application, as shown in fig. 15, the electrical connection end of the first element 60 faces away from the active element 20, and in particular, in an embodiment of the present application, the first element 60 is electrically connected to the first bonding pad 50 through the third bonding wire 70, so that the first element is electrically connected to the active element through the third bonding wire and the second bonding wire sequentially, but the present application is not limited thereto, and in other embodiments of the present application, the first element may also be electrically connected to the first bonding pad through other electrical connection manners, as the case may be.
On the basis of the above embodiment, in one embodiment of the present application, the first element is fixed on a side surface of the first packaging layer, which is opposite to the carrier, and optionally, the first element is adhered on a side surface of the first packaging layer, which is opposite to the carrier, but the present application is not limited thereto.
Specifically, in one embodiment of the present application, continuing to refer to fig. 15, fixing the first element 60 on a surface of the first encapsulation layer 40 on a side facing away from the carrier 10 includes:
Forming a second adhesive layer 61 on the side of the first encapsulation layer 40 facing away from the carrier 10;
The first element 60 is placed on the side of the second adhesive layer 61 facing away from the first encapsulation layer 40, so that the first element is glued to the side of the first encapsulation layer facing away from the carrier body by means of the second adhesive layer.
On the basis of any one of the above embodiments, in one embodiment of the present application, as further shown in fig. 15, the preparation method further includes:
The fourth encapsulation layer 43 is formed on the side of the first encapsulation layer 40 away from the carrier 10, and the fourth encapsulation layer 43 encapsulates the first element 60, the third bonding wire 70 and the first bonding pad 50 to protect the first element 60, the third bonding wire 70 and the first bonding pad 50, but the present application is not limited thereto, and the present application is specifically limited thereto as the case may be.
On the basis of the above embodiments, in one embodiment of the present application, the fourth encapsulation layer is a flavored plain epoxy resin film, but the present application is not limited thereto, and is specifically limited thereto as the case may be.
On the basis of any one of the above embodiments, in one embodiment of the present application, as shown in fig. 16 and 17, the preparation method further includes: at least one second element 80 is fixed on the side of the first bonding pad 50 facing away from the first encapsulation layer 40 before the first element 60 is fixed on the side of the first bonding pad 50 facing away from the first encapsulation layer 40, and the first element 60 is fixed on the side of the second element 80 facing away from the active element 20. Optionally, in an embodiment of the present application, the second element 80 is electrically connected to at least one of the first pads 50, and the second element 80 is electrically connected to the first pad 50 through a fourth bonding wire 90, so that the chip structure is formed by stacking at least three elements, which is not limited in this aspect of the present application, as the case may be.
On the basis of the above embodiment, in one embodiment of the present application, the second element is an active element; in another embodiment of the present application, the second component is a passive component, which is not limited in this aspect, and is specifically determined according to the requirements of the chip structure.
On the basis of any of the above embodiments, in one embodiment of the present application, the passive element is a passive electronic element, but the present application is not limited thereto, and in other embodiments of the present application, the passive element may be a passive element, as the case may be.
Specifically, in one embodiment of the present application, continuing to refer to fig. 16 and 17, fixing at least one second element 80 on a side of the first pad 50 facing away from the first encapsulation layer 40 includes:
forming a third adhesive layer 81 on the side of the first encapsulation layer 40 facing away from the carrier;
placing the second element 80 on the side of the third adhesive layer 81 facing away from the first encapsulation layer 40, so as to fix the second element on the surface of the first encapsulation layer facing away from the carrier by using the third adhesive layer;
forming the fourth bonding wire 90 electrically connecting the second element and the first bonding pad 50 on the side of the second element 80 facing away from the first encapsulation layer 40;
forming a plurality of seventh bonding wires on a side of the second element 80 facing away from the first encapsulation layer 40, wherein two connection ends of the seventh bonding wires are electrically connected to any one of the second element and the first bonding pad;
Forming a fifth encapsulation layer 44 on a side of the second element 80 away from the first encapsulation layer 40, where the fifth encapsulation layer 44 encapsulates the second element 80, the first bonding pad 50, the fourth bonding wire 90, and the seventh bonding wire to protect the third active element 80, the fourth bonding wire 90, the first bonding pad 50, and the seventh bonding wire;
removing part of the thickness of the fifth packaging layer 44 from the side, away from the first packaging layer 40, of the fifth packaging layer 44 until one seventh bonding wire forms two independent eighth bonding wires 7, and the fifth packaging layer exposes the end surface, away from the bearing body, of the eighth bonding wire, so that the subsequent first element and the eighth bonding wire are electrically connected;
A plurality of second bonding pads 51 are formed on a side, facing away from the first packaging layer 40, of the fifth packaging layer 44, and the plurality of second bonding pads 51 are in one-to-one correspondence with the plurality of eighth bonding wires 7 and are electrically connected, so that the problem that the electric connection process difficulty between the first element and the eighth bonding wires is high and the electric connection performance between the second element and the eighth bonding wires is affected due to the fact that the end face, facing away from the fifth packaging layer, of the plurality of eighth bonding wires is small can be avoided;
a first element 60 is fixed on the side of the second bonding pad 51 facing away from the fifth encapsulation layer 44, the first element 60 being electrically connected to the second bonding pad 51.
In the embodiment of the present application, since the two connection ends of the seventh bonding wire are electrically connected to any one of the second element and the first bonding pad, when one seventh bonding wire forms two independent eighth bonding wires, in one embodiment of the present application, the eighth bonding wire is electrically connected to only the first bonding pad, in another embodiment of the present application, the eighth bonding wire is electrically connected to only the second element, and in yet another embodiment of the present application, a part of the eighth bonding wire is electrically connected to the first bonding pad, and a part of the eighth bonding wire is electrically connected to the second element.
When the eighth bonding wire is electrically connected to the first bonding pad, the first element may be electrically connected to the second bonding wire through the eighth bonding wire and the first bonding pad in sequence, and when the eighth bonding wire is electrically connected to the second element, the first element may be electrically connected to the second bonding wire through the eighth bonding wire, the second element and the first bonding pad in sequence.
On the basis of any one of the above embodiments, in one embodiment of the present application, the first element is electrically connected to at least one of the second elements. In one embodiment of the present application, the first element is electrically connected to the second element, that is, the first element is directly electrically connected to the second element through the eighth bonding wire, that is, one end of the eighth bonding wire is electrically connected to the first element, and the other end of the eighth bonding wire is electrically connected to the second element; in another embodiment of the present application, the first element and the second element are electrically connected to each other, that is, the first element is electrically connected to the first pad through an eighth bonding wire, and the second element is simultaneously electrically connected to the first pad through a fourth bonding wire, so as to achieve the electrical connection between the first element and the second element, which is not limited in this aspect of the present application, according to circumstances.
Alternatively, in one embodiment of the present application, when the electrical connection end of the first element faces the active element, as shown in fig. 16, the first element 60 is electrically connected to the second pad 51 through a ball, and in another embodiment of the present application, the electrical connection end of the first element faces away from the active element, as shown in fig. 17, the first element 60 is electrically connected to the second pad 51 through a fifth bonding wire 70, which is not limited in this aspect of the present application.
Therefore, in the method for manufacturing the chip structure provided by the embodiment of the application, the electrical connection ends of the active elements are led out through the plurality of second bonding wires, the first packaging layer is formed, and the first packaging layer exposes the end faces of the second bonding wires, so that the stacked active elements and the first elements are electrically connected by the second bonding wires, the phenomenon of poor packaging reliability of the chip structure caused by electrically connecting the stacked active elements and the first elements in a punching and metal plating mode is avoided, and the packaging reliability of the chip structure is improved.
In addition, in the method for manufacturing the chip structure provided by the embodiment of the application, the active element is fixed on the surface of the carrier, and then the active element and/or the electric connection end of the carrier is led out through the second bonding wire so as to be electrically connected with the first element, and finally the active element and the plurality of second bonding wires are packaged through the first packaging layer to form a packaging whole, so that the active element is packaged in the first packaging layer to form an active substrate structure, and the problems of longer production period and higher cost caused by embedding the active element into the passive substrate to form the active substrate structure are solved.
Correspondingly, the embodiment of the application also provides a chip structure. 11-13, the chip structure provided by the embodiment of the application includes:
a carrier 10;
an active element 20 secured to a first side surface of the carrier 10;
A plurality of second bonding wires 30, each second bonding wire 30 being electrically connected to at least one of the carrier 10 and the active element 20;
The first encapsulation layer 40 is located at the first side of the carrier 10 and encapsulates the plurality of second bonding wires 30 and the active element 20, and the first encapsulation layer 40 exposes an end surface of the plurality of second bonding wires 30 facing away from the carrier 10;
the first bonding pad 50 is located on a surface of the first packaging layer 10 facing away from the carrier 10 and electrically connected with the second bonding wire 30;
a first element 60 located on a side of the first bonding pad 50 facing away from the first encapsulation layer 40, the first element 60 being electrically connected to at least one of the first bonding pads 50.
On the basis of the above embodiment, in one embodiment of the present application, the first bonding pad is located on a surface of the first packaging layer, which is opposite to the side of the carrier, and is in one-to-one correspondence and electrically connected with the end surfaces of the sides of the plurality of second bonding wires, which are opposite to the side of the carrier, so that the first bonding pad is used as an electrical connection end of the active element and/or the carrier, and the first element is electrically connected with the plurality of second bonding wires through the electrical connection with the plurality of first bonding pads, thereby realizing the electrical connection with the active element and/or the carrier.
It should be noted that, in the embodiment of the present application, the second bonding wires are electrically connected to the first element through the first bonding pad, so that the problem that the end surface of the side, facing away from the carrier, of the plurality of second bonding wires is smaller, resulting in a greater difficulty in the electrical connection process between the first element and the second bonding wires and affecting the electrical connection performance between the first element and the second bonding wires can be avoided.
In addition, in the chip structure provided by the embodiment of the application, the electrical connection ends of the active elements are led out through the plurality of second bonding wires, the first packaging layer is formed, and the end faces of the second bonding wires are exposed by the first packaging layer, so that the stacked active elements and the first elements can be electrically connected by the second bonding wires, the phenomenon that the packaging reliability of the chip structure is poor due to the fact that the stacked active elements and the first elements are electrically connected in a punching and metal plating mode is avoided, and the packaging reliability of the chip structure is improved.
In addition, in the chip structure provided by the embodiment of the application, the active element is fixed on the surface of the carrier, the active element and/or the electric connection ends of the carrier are led out through the second bonding wires, and finally the active element and the plurality of second bonding wires are packaged through the first packaging layer, so that the active carrier structure is formed, the active element is not required to be transferred to a special substrate factory to be embedded into a passive substrate to form the active substrate structure, the use of substrate materials is reduced, the manufacturing process is simplified, and the preparation cost of the chip structure is reduced.
On the basis of the above embodiment, in one embodiment of the present application, the first element is an active element; in another embodiment of the present application, the first element is a passive element, which is not limited in this application, and is specifically determined according to the requirements of the chip structure.
On the basis of the above embodiments, in one embodiment of the present application, the carrier is a substrate, such as a PCB board, and in another embodiment of the present application, the carrier may be a metal frame, so as to further reduce the cost of the chip structure. Alternatively, in one embodiment of the present application, the carrier is a copper frame, which is not limited in this regard, as the case may be.
On the basis of the above embodiment, in one embodiment of the present application, the active element is fixed on the first side surface of the carrier, alternatively, in one embodiment of the present application, the active element is adhered on the first side surface of the carrier, and in particular, with continued reference to fig. 13, the chip structure further includes a first adhesive layer 21, where the active element is fixed on the first side surface of the carrier by the first adhesive layer, but the present application is not limited thereto, and in other embodiments of the present application, the active element may be fixed on the first side surface of the carrier by other manners, as the case may be.
On the basis of the above embodiment, in one embodiment of the present application, as further shown in fig. 11, the plurality of second bonding wires 30 are all electrically connected to the active element 20, so as to lead out the electrical connection end of the active element through the second bonding wires, thereby facilitating the electrical connection between the first element and the active element through the second bonding wires; in another embodiment of the present application, as further shown in fig. 12, the plurality of second bonding wires 30 are all electrically connected to the carrier 10, so as to lead out the electrical connection end of the carrier through the second bonding wires, so as to facilitate the subsequent electrical connection between the first element and the carrier through the second bonding wires; in still another embodiment of the present application, with continued reference to fig. 13, a portion of the second bonding wires of the plurality of second bonding wires are electrically connected to the carrier, and a portion of the second bonding wires are electrically connected to the active element, which is not limited in this regard, as the case may be.
The chip structure provided by the embodiment of the application is described below by taking an example that a part of the second bonding wires are electrically connected with the carrier, and a part of the second bonding wires are electrically connected with the active element.
With continued reference to fig. 13, in one embodiment of the present application, the plurality of second bonding wires 30 includes at least one first sub-bonding wire 31 and at least one second sub-bonding wire 32, the first sub-bonding wire 31 is electrically connected to the active element 20, the second sub-bonding wire 32 is electrically connected to the carrier 10 to draw the electrical connection end of the active element through the first sub-bonding wire, and the second sub-bonding wire draws the electrical connection end of the carrier.
It should be noted that, in the embodiment of the present application, the first sub-bonding wire is electrically connected to the active element, so that the electrical connection end of the active element is led out through the first sub-bonding wire, so that the first element can be electrically connected to the active element through the first sub-bonding wire; the second sub-bonding wires are electrically connected with the carrier, so that the electrical connection ends of the carrier are led out through the second sub-bonding wires, and the first element can be electrically connected with the second sub-bonding wires to realize the electrical connection with the carrier.
It should be further noted that if the active element is embedded into the substrate to form an active substrate structure, and then the electrical connection between different elements is achieved by punching and metal plating, the production cycle is generally more than 4 weeks, and the time is long, in the embodiment of the present application, the active element is fixed on the first side surface of the carrier, then the electrical connection ends of the active element and/or the carrier are led out through the plurality of second bonding wires, and finally the active element and the plurality of second bonding wires are encapsulated by using the first encapsulation layer, the active element is encapsulated in the first encapsulation layer to form an active substrate structure, the active element is prevented from being embedded into the substrate through the second bonding wires and electrically connected with the subsequent first element, and the stacked active element and first element are not required to be electrically connected in a punching and metal plating mode, so that the production period can be shortened to 1-2 days, the production period of the chip structure is greatly shortened, and the production cost is reduced.
As shown in fig. 18, on the basis of the above embodiment, in one embodiment of the present application, the chip structure further includes: at least one sixth bonding wire 33 electrically connecting the active element 20 and the carrier 10 to electrically connect the carrier and the active element, but the present application is not limited thereto, and is specifically determined according to the application requirements of the chip structure.
It should be noted that, in the above embodiment, the first packaging layer completely wraps the sixth bonding wire, so as to prevent one end of the sixth bonding wire, which is away from the carrier, from being exposed outside the first packaging layer, from being oxidized, polluted or shorted with other electrical elements in the external environment, which affects the performance of the chip structure.
On the basis of any of the above embodiments, in one embodiment of the present application, the first encapsulation layer is a flavored epoxy resin film, and in another embodiment of the present application, the material of the first encapsulation layer is a plastic encapsulation material, but the present application is not limited thereto, and in other embodiments of the present application, the first encapsulation layer may be another encapsulation material, and it is only required to ensure that the first encapsulation layer encapsulates the active element and the plurality of second bonding wires to form a package whole, and isolate the active element from the external environment, as the case may be.
On the basis of any of the above embodiments, in one embodiment of the present application, the electrical connection end of the first element 60 faces the active element 20, specifically, with continued reference to fig. 13, the first element 60 is electrically connected to the first bonding pad 50 through the ball implant 61, so that the first element is electrically connected to the active element through the ball implant, the first bonding pad and the second bonding wire in sequence.
On the basis of the above-described embodiment, in one embodiment of the present application, with continued reference to fig. 13, the chip structure further includes a second encapsulation layer 41, where the second encapsulation layer 41 encapsulates at least the gap between the first element 60 and the first encapsulation layer 40. Specifically, in the embodiment of the present application, the electrical connection end of the first element 60 faces the active element 20, that is, the electrical connection end of the first element 60 faces the first packaging layer 40, the first bonding pad 50 is located on a side of the first packaging layer 40 facing away from the carrier 10, the electrical connection end of the first element 60 is electrically connected with the first bonding pad 50 through a ball 61, and the second packaging layer 41 encapsulates a gap between the first element 60 and the first packaging layer 40, that is, encapsulates the ball 61 and the first bonding pad 50, so as to protect the ball and the first bonding pad from being separated from the first bonding pad in a subsequent process, so that the chip structure is damaged.
On the basis of the above embodiments, in one embodiment of the present application, the material of the second encapsulation layer is Underfill (Underfill), but the present application is not limited thereto, and in other embodiments of the present application, the material of the second encapsulation layer may be other encapsulation materials, as the case may be.
In another embodiment of the present application, as further shown in fig. 14, to better protect the first element, the chip structure further includes: the third packaging layer 42 is located on the side of the first packaging layer 40 away from the carrier 10, and encapsulates the first element 60, the ball 61 and the first bonding pad 50, so as to protect the ball and the first bonding pad and protect the first element, but the application is not limited thereto, and the application is not limited thereto as the case may be.
On the basis of the above embodiments, in one embodiment of the present application, the third encapsulation layer is a flavored plain epoxy resin film, but the present application is not limited thereto, and is specifically limited thereto as the case may be.
In another embodiment of the present application, as further shown in fig. 15, the electrical connection end of the first element 60 is located on the side facing away from the active element 20, specifically, in this embodiment of the present application, the first element 60 is electrically connected to the first bonding pad 50 through the third bonding wire 70, so that the first element is electrically connected to the active element through the third bonding wire and the second bonding wire sequentially, but the present application is not limited thereto, and in other embodiments of the present application, the first element may be electrically connected to the first bonding pad through other electrical connection manners, as the case may be.
On the basis of the above embodiment, in one embodiment of the present application, the first element is fixed on a side surface of the first encapsulation layer facing away from the carrier, and optionally, the first element is adhered on a side surface of the first encapsulation layer facing away from the carrier. Specifically, with continued reference to fig. 15, the chip structure further includes a second adhesive layer 61, where the first element 60 is fixed on a surface of the first package layer 40 facing away from the carrier 10 by using the second adhesive layer 61, but the application is not limited thereto, and in other embodiments of the application, the first element may be fixed on a surface of the first package layer facing away from the carrier by other manners, where appropriate.
On the basis of any of the above embodiments, in one embodiment of the present application, as further shown in fig. 15, the chip structure further includes a fourth packaging layer 43, where the fourth packaging layer 43 is located on a side of the first packaging layer 40 facing away from the carrier 10, and encapsulates the first element 60, the third bonding wire 70, and the first bonding pad 50, so as to protect the first element 60, the third bonding wire 70, and the first bonding pad 50, but the present application is not limited thereto, and is specifically limited thereto as the case may be.
On the basis of the above embodiments, in one embodiment of the present application, the fourth encapsulation layer is a flavored plain epoxy resin film, but the present application is not limited thereto, and is specifically limited thereto as the case may be.
On the basis of any of the above embodiments, in one embodiment of the present application, as further shown in fig. 16 and 17, the chip structure further includes: at least one second element 80 located between the first encapsulation layer 40 and the first element 60, the second element 80 is electrically connected to at least one of the first pads 50, and the second element 80 is electrically connected to the first pads 50 through a fourth bonding wire 90, so that the chip structure is formed by stacking at least three elements, which is not limited by the present application, and the present application is specifically limited thereto.
On the basis of the above embodiment, in one embodiment of the present application, the second element is an active element; in another embodiment of the present application, the second component is a passive component, which is not limited in this aspect, and is specifically determined according to the requirements of the chip structure.
On the basis of any of the above embodiments, in one embodiment of the present application, the passive element is a passive electronic element, but the present application is not limited thereto, and in other embodiments of the present application, the passive element may be a passive element, as the case may be.
On the basis of the above embodiment, in one embodiment of the present application, as further shown in fig. 16 and 17, the chip structure further includes: a third adhesive layer 81, where the third adhesive layer 81 is located between the second element 80 and the first packaging layer 40, and fixes the second element on a surface of the first packaging layer facing away from the carrier, but the application is not limited thereto, and the application is specifically limited thereto as the case may be.
On the basis of the above embodiment, in one embodiment of the present application, as further shown in fig. 16 and 17, the chip structure further includes: a plurality of eighth bonding wires 7, where the plurality of eighth bonding wires 7 are electrically connected to at least one of the second element and the first bonding pad, and the present application is not limited thereto, and the present application is specifically limited as the case may be.
On the basis of the above embodiment, in one embodiment of the present application, as further shown in fig. 16 and 17, the chip structure further includes: the fifth packaging layer 44 is disposed between the first packaging layer 40 and the first element 60, encapsulates the second element 80, the eighth bonding wire 7, the fourth bonding wire 90 and the first bonding pad 50, and exposes a side end surface of the plurality of eighth bonding wires facing away from the first packaging layer, so as to facilitate electrical connection between the subsequent first element and the eighth bonding wire while protecting the second element 80, the eighth bonding wire 7, the fourth bonding wire 90 and the first bonding pad 50, but the application is not limited thereto, and is specifically defined as appropriate.
On the basis of the above embodiment, in one embodiment of the present application, as further shown in fig. 16 and 17, the chip structure further includes: the second bonding pads 51 are located on a side surface of the fifth packaging layer 44 facing away from the first packaging layer 40, and are electrically connected with the eighth bonding wires, so as to avoid the problem that the side end surface of the eighth bonding wires facing away from the fifth packaging layer is smaller, which results in a higher difficulty in the electrical connection process between the first element and the eighth bonding wires and affects the electrical connection performance between the first element and the eighth bonding wires.
On the basis of the above embodiments, in one embodiment of the present application, the first element is electrically connected to at least one of the second elements. In one embodiment of the present application, the first element is electrically connected to the second element, that is, the first element is directly electrically connected to the second element through the eighth bonding wire, that is, one end of the eighth bonding wire is electrically connected to the first element, and the other end of the eighth bonding wire is electrically connected to the second element; in another embodiment of the present application, the first element and the second element are electrically connected to each other, that is, the first element is electrically connected to the first pad through an eighth bonding wire, and the second element is simultaneously electrically connected to the first pad through a fourth bonding wire, so as to achieve the electrical connection between the first element and the second element, which is not limited in this aspect of the present application, according to circumstances.
Alternatively, in one embodiment of the present application, when the electrical connection end of the first element faces the active element, as shown in fig. 16, the first element 60 is electrically connected to the second pad 51 through a ball, and in another embodiment of the present application, the electrical connection end of the first element faces away from the active element, as shown in fig. 17, the first element 60 is electrically connected to the second pad 51 through a fifth bonding wire 70, which is not limited in this aspect of the present application.
In summary, in the chip structure provided in the embodiment of the present application, the electrical connection ends of the active elements are led out through the plurality of second bonding wires, and then the first packaging layer is formed, and the first packaging layer exposes the end surfaces of the second bonding wires, so that the stacked active elements and first elements are electrically connected by using the second bonding wires, the phenomenon that the packaging reliability of the chip structure is poor due to the fact that the stacked active elements and first elements are electrically connected by punching and metal plating is avoided, and the packaging reliability of the chip structure is improved.
In the chip structure provided by the embodiment of the application, the active element is fixed on the surface of the carrier, the active element and/or the electric connection end of the carrier is led out through the second bonding wire so as to be electrically connected with the first element, and finally the active element and the plurality of second bonding wires are packaged through the first packaging layer to form a packaging whole, so that the active element is packaged in the first packaging layer to form an active substrate structure, and the problems of longer production period and higher cost caused by embedding the active element into the passive substrate to form the active substrate structure are solved.
In the description, each part is described in a parallel and progressive mode, and each part is mainly described as a difference with other parts, and all parts are identical and similar to each other.
The features described in the various embodiments of the present disclosure may be interchanged or combined with one another in the description to enable those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. A method of manufacturing a chip structure, comprising:
fixing an active element on the first side surface of the carrier;
forming a plurality of first bonding wires on one side of the active element, which is away from the carrier, wherein two connecting ends of the first bonding wires are electrically connected to any one of the carrier and the active element, and the height of the first bonding wires is higher than the surface of the active element, which is away from the carrier;
Forming a first packaging layer on one side of the active element, which is away from the carrier, wherein the first packaging layer packages the active element and the plurality of first bonding wires;
Removing the thickness of the first packaging layer part and the first bonding wire part from one side of the first packaging layer, which is away from the carrier, until any one of the first bonding wires forms two independent second bonding wires, and exposing one side end surface of the second bonding wire, which is away from the carrier, of the first packaging layer after removing part of the thickness;
forming a plurality of first bonding pads on one side, away from the carrier, of the first packaging layer, wherein the plurality of first bonding pads are in one-to-one correspondence with and are electrically connected with a plurality of second bonding wires;
Fixing a first element on one side of the first bonding pad, which is away from the first packaging layer, wherein the first element is electrically connected with at least one first bonding pad;
Before a first element is fixed on the side, away from the first packaging layer, of the first bonding pad, at least one second element is fixed on the side, away from the first packaging layer, of the first bonding pad, and the first element is fixed on the side, away from the active element, of the second element;
the second element is electrically connected with at least one first bonding pad, and the second element is electrically connected with the first bonding pad through a fourth bonding wire;
a second encapsulation layer is formed encapsulating at least the first element and the void between the first encapsulation layers.
2. The manufacturing method according to claim 1, wherein both connection ends of the first bonding wire are electrically connected to the carrier; or, the two connecting ends of the first bonding wire are electrically connected with the active element; or, one connecting end of the first bonding wire is electrically connected with the carrier, and the other connecting end is electrically connected with the active element.
3. The method of manufacturing of claim 1, wherein the electrical connection end of the first element is oriented toward the active element, and the first element is electrically connected to the first bonding pad by a ball implant.
4. The method of manufacturing of claim 1, wherein the first element electrical connection is away from the active element, the first element being electrically connected to the first bonding pad by a third bonding wire.
5. The method of manufacturing according to claim 1, wherein the first element is an active element or the first element is a passive element.
6. The method of manufacturing according to claim 1, wherein the second element is an active element or the second element is a passive element.
7. The method of manufacturing of claim 1, wherein the active element is affixed to the first side surface of the carrier.
8. The method of claim 1, wherein the carrier is a substrate or the carrier is a metal frame.
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