CN112491414B - Locking indicating circuit for monitoring locking state of phase-locked loop circuit in real time - Google Patents
Locking indicating circuit for monitoring locking state of phase-locked loop circuit in real time Download PDFInfo
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- CN112491414B CN112491414B CN202011145211.6A CN202011145211A CN112491414B CN 112491414 B CN112491414 B CN 112491414B CN 202011145211 A CN202011145211 A CN 202011145211A CN 112491414 B CN112491414 B CN 112491414B
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- 238000012544 monitoring process Methods 0.000 title claims abstract description 17
- 238000001914 filtration Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000010355 oscillation Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
- H03L7/146—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail by using digital means for generating the oscillator control signal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The embodiment of the invention discloses a locking indication circuit for monitoring the locking state of a phase-locked loop circuit in real time, which is characterized by comprising the following components: the device comprises a mixer, a filter, an operational amplifier, a comparator and an FPGA chip; wherein the mixer local oscillator receives the phase-locked loopReference signal F of circuit ref The radio frequency end receives a feedback signal F of the phase-locked loop circuit R Generating a mixing signal F IF The method comprises the steps of carrying out a first treatment on the surface of the Mixing the frequency signal F IF In the input filter, the filter is used for mixing the frequency signal F IF Filtering to obtain a clean locking signal F I The F is I Inputting the operational amplifier; the operational amplifier couples the F I Is amplified to obtain an output signal F A Said signal F A Inputting the comparator; the comparator compares the F A Comparing with standard voltage signal to obtain output voltage signal f s The signal f s Inputting the real-time locking information into the FPGA chip, and generating the real-time locking information of the monitoring phase-locked loop circuit through the internal counting and operation of the FPGA chip.
Description
Technical Field
The invention relates to the technical field of electronic information. And more particularly to a lock indication circuit for monitoring the lock state of a phase-locked loop circuit in real time
Background
In high performance atomic frequency standard systems, the output signal of the frequency source is usually required to have high frequency stability. Phase locked loops are one of the important means of achieving this goal. In order to make the phase-locked loop circuit have lower added phase noise, an analog phase detector is generally used as the phase frequency detector of the phase-locked loop circuit. The analog phase detector generally has no locking indication function, and in order to monitor the locking state of the phase-locked loop and analyze possible jitter of the phase-locked loop in real time, a locking indication circuit capable of monitoring the locking state of the phase-locked loop in real time is needed to send back locking state information needed by a system.
Disclosure of Invention
In view of the foregoing, an embodiment of the present invention provides a lock indication circuit for monitoring a lock state of a phase-locked loop circuit in real time, including: the device comprises a mixer, a filter, an operational amplifier, a comparator and an FPGA chip; wherein,,
the local oscillator end of the mixer receives the reference signal F of the phase-locked loop circuit ref The radio frequency end receives a feedback signal F of the phase-locked loop circuit R Generating a mixing signal F IF ；
Mixing the frequency signal F IF In the input filter, the filter is used for mixing the frequency signal F IF Filtering to obtain a clean locking signal F I The F is I Inputting the operational amplifier;
the saidAn operational amplifier subjects the F to I Is amplified to obtain an output signal F A Said signal F A Inputting the comparator;
the comparator compares the F A Comparing with standard voltage signal to obtain output voltage signal f s The signal f s Inputting the real-time locking information into the FPGA chip, and generating the real-time locking information of the monitoring phase-locked loop circuit through the internal counting and operation of the FPGA chip.
In a specific embodiment, the FPGA chip includes:
a counter for measuring the signal f s Pulse number M of (a);
an arithmetic unit for calculating the signal f according to the pulse number M s And a phase value of the phase-locked loop circuit, thereby obtaining locking information of the phase-locked loop circuit.
In a specific example, the F ref 、F R And f s The relation of (2) is: f (f) s ＝F ref -F R 。
In one embodiment, the comparator is a hysteresis comparator for reducing its input signal F A And the noise is carried in.
In one specific example, signal F IF Including lock information and high frequency leakage signals.
In one specific example, the mixer is a double balanced mixer.
In one specific example, the operational amplifier is a voltage scaling circuit built with a resistor network.
In one specific example, the filter is a low pass filter.
In one embodiment, the other input of the operator is adapted to receive a standard clock signal.
The beneficial effects of the invention are as follows:
the circuit obtains the difference between the reference signal and the feedback signal of the specific phase-locked loop circuit through the mixer, and sends the difference into the FPGA through a series of circuit processes to calculate the frequency difference and the phase difference, so that the real-time monitoring of the locking information of the specific phase-locked loop circuit is realized. The circuit has universality and can be matched with any phase-locked loop circuit to finish the monitoring of the locking state.
Drawings
The following describes the embodiments of the present invention in further detail with reference to the drawings.
Fig. 1 shows a schematic diagram of a lock indication circuit for monitoring a lock state of a phase locked loop circuit in real time according to an embodiment of the invention.
Fig. 2 shows a schematic diagram of the composition of an FPGA chip according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the present invention, the present invention will be further described with reference to preferred embodiments and the accompanying drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and that this invention is not limited to the details given herein.
The core of the circuit of the embodiment of the invention extracts the difference between the reference signal and the feedback signal by using the double-balanced mixer, and calculates the frequency difference and the phase difference by using the FPGA to obtain the real-time locking information of the specific phase-locked loop circuit.
As shown in fig. 1, a lock indication circuit for monitoring a lock state of a phase-locked loop circuit in real time includes: mixer 1, filter 2, operational amplifier 3, comparator 4 and FPGA chip 5; wherein,,
the local oscillation end of the mixer 1 receives the reference signal F of the phase-locked loop circuit ref The radio frequency end receives a feedback signal F of the phase-locked loop circuit R Generating a mixing signal F IF ；
Mixing the frequency signal F IF In the input filter 2, the filter is used for mixing the signal F IF Filtering to obtain a clean locking signal F I The F is I Inputting the operational amplifier 3;
the operational amplifier 3 outputs the F signal I Is amplified to obtain an output signal F A Said signal F A Inputting the comparator 4;
the comparator 4 compares the F A Comparing with standard voltage signal to obtain output voltage signal f s The signal f s And inputting the real-time locking information into the FPGA chip 5, and generating the real-time locking information of the monitoring phase-locked loop circuit through the internal counting and operation of the FPGA chip.
In one example, the mixer is a double balanced mixer, where the frequency output may be a direct current signal or a low frequency signal. The available model is ADE-12MH+.
The operational amplifier is a voltage scaling circuit built with a resistor network, in one example, an OPA211 AID.
The F is ref 、F R And f s The relation of (2) is: f (f) s ＝F ref -F R 。
The comparator is a hysteresis comparator for reducing its input signal F A And the noise is carried in.
In one example, the hysteresis comparator is a voltage comparator, and the comparison level of the rising edge and the comparison level of the falling edge of the hysteresis comparator are two levels, so that noise influence possibly brought into an input signal can be effectively reduced. Available model AD8561ARZ.
Signal F IF Including lock information and high frequency leakage signals.
The filter is a low pass filter, in one example, a third order LC low pass filter, or an active low pass filter may be used.
The radio frequency end and the local oscillation end of the mixer are signal input ends of the phase-locked loop locking indication circuit, wherein the local oscillation end of the mixer is a reference signal of a specific phase-locked loop circuit, and the radio frequency end of the mixer is a feedback signal of the specific phase-locked loop circuit. The intermediate frequency output of the mixer is connected with the input end of the low-pass filter, the output end of the filter is connected with the input end of the operational amplifier, the output end of the operational amplifier is connected with the input end of the hysteresis comparator, the output end of the hysteresis comparator is connected with the input end of the FPGA, and the output end of the FPGA returns locking information of the whole system.
As shown in fig. 2, the FPGA chip 5 includes:
a counter 6 for measuring the signal f s Pulse number M of (a);
an operator 7 for calculating the signal f based on the pulse number M s And a phase value of the phase-locked loop circuit, thereby obtaining locking information of the phase-locked loop circuit. Signal f s The frequency value and the phase value of (a) are the input signal F of the lock indication circuit ref And F R Frequency difference and phase difference of (a) are provided.
In the FPGA chip 5, the input end of the counter and the signal to be tested (i.e. f is the above s ) The output end of the counter 6 is connected with one input end of the arithmetic unit 7, the other input end of the arithmetic unit 7 is connected with a standard clock signal, and the output end of the arithmetic unit is the output of the FPGA chip.
The difference between the reference signal and the feedback signal of the specific phase-locked loop circuit is obtained through the double-balanced mixer, and is sent into the FPGA through a series of circuit processes to calculate the frequency difference and the phase difference, so that the real-time monitoring of the locking information of the specific phase-locked loop circuit is realized. The circuit has universality and can be matched with any phase-locked loop circuit to finish the monitoring of the locking state.
It should be understood that the foregoing examples of the present invention are provided merely for clearly illustrating the present invention and are not intended to limit the embodiments of the present invention, and that various other changes and modifications may be made therein by one skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (7)
1. A lock indication circuit for monitoring a lock state of a phase-locked loop circuit in real time, comprising: the device comprises a mixer, a filter, an operational amplifier, a comparator and an FPGA chip;
wherein,,
the local oscillator end of the mixer receives the reference signal F of the phase-locked loop circuit ref The radio frequency end receives a feedback signal F of the phase-locked loop circuit R Extracting the difference between the reference signal and the feedback signal to generate a mixed signal F IF ；
Mixing the frequency signal F IF In the input filter, the filter is used for mixing the frequency signal F IF Filtering to obtain a clean locking signal F I The F is I Inputting the operational amplifier;
the operational amplifier couples the F I Is amplified to obtain an output signal F A Said signal F A Inputting the comparator;
the comparator outputs the output signal F A Comparing with standard voltage signal to obtain output voltage signal f s The signal f s Inputting an FPGA chip, and generating real-time locking information of a monitoring phase-locked loop circuit through internal counting and operation of the FPGA chip;
the mixer is a double balanced mixer and,
the FPGA chip comprises:
a counter for measuring the signal f s Pulse number M of (a);
an arithmetic unit for calculating the signal f according to the pulse number M s And a phase value of the phase-locked loop circuit, thereby obtaining locking information of the phase-locked loop circuit.
2. The circuit of claim 1, wherein the F ref 、F R And f s The relation of (2) is: f (f) s ＝F ref -F R 。
3. The circuit of claim 1, wherein the comparator is a hysteresis comparator for reducing its input signal F A And the noise is carried in.
4. The circuit of claim 1, wherein signal F IF Including lock information and high frequency leakage signals.
5. The circuit of claim 1, wherein the operational amplifier is a voltage scaling circuit built with a resistor network.
6. The circuit of claim 1, wherein the filter is a low pass filter.
7. The circuit of claim 1, wherein the other input of the operator is configured to receive a standard clock signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011145211.6A CN112491414B (en) | 2020-10-23 | 2020-10-23 | Locking indicating circuit for monitoring locking state of phase-locked loop circuit in real time |
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| CN202011145211.6A CN112491414B (en) | 2020-10-23 | 2020-10-23 | Locking indicating circuit for monitoring locking state of phase-locked loop circuit in real time |
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| CN112491414B true CN112491414B (en) | 2023-07-07 |
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| US8265769B2 (en) * | 2007-01-31 | 2012-09-11 | Medtronic, Inc. | Chopper-stabilized instrumentation amplifier for wireless telemetry |
| CN105187060B (en) * | 2015-07-23 | 2018-04-24 | 中国电子科技集团公司第四十一研究所 | The phase-locked loop circuit and its implementation of a kind of low phase noise |
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