CN112509507B - Drive device and display device - Google Patents

Abstract

The invention discloses a driving device, which comprises a multi-stage shift register circuit. The shift register circuits are serially coupled in sequence, wherein each of the shift register circuits comprises a logic unit, an output unit and a switch unit. The logic unit is used for operating according to at least one previous stage shift register signal. The output unit comprises a first output switch and a second output switch. A control terminal of the first output switch is coupled to the logic unit at a first node. A first end of the first output switch is used for outputting a current level shift register signal. A control terminal of the second output switch is coupled to the logic unit at a second node. A first end of the second output switch is coupled to the first end of the first output switch. The switch unit is used for being conducted according to a switch signal, and at least one of the first output switch and the second output switch is closed when the switch unit is conducted.

Description

Drive device and display device

technical field

The present invention relates to a display technology, in particular to a display panel driving device and a display device.

Background technique

When the shift temporary storage circuit in the display device is abnormal due to electrostatic discharge damage or crushing during bonding or other reasons, laser cutting will be performed to disconnect the electrical coupling relationship between the shift temporary storage circuit and the display device , but laser cutting is a destructive process that needs to dig holes in the metal layer, and laser cutting may also fail. All of the above factors may cause the quality of the panel to decline. Therefore, it is one of the important issues in this field to deal with the abnormality of the shift register circuit in a way other than laser cutting.

Contents of the invention

An embodiment of the present application discloses a driving device including a multi-stage shift register circuit. The shift register circuits are sequentially coupled in series, wherein each of the shift register circuits includes a logic unit, an output unit and a switch unit. The logic unit is used to operate at least according to a previous stage shift register signal. The output unit includes a first output switch and a second output switch. A control end of the first output switch is coupled to the logic unit at a first node, and a first end of the first output switch is used for outputting a shift register signal of a stage. A control end of the second output switch is coupled to the logic unit at a second node, and a first end of the second output switch is coupled to the first end of the first output switch. The switch unit is used for turning on according to a switch signal, and turning off at least one of the first output switch and the second output switch when turning on.

A display device of this application includes a set of first shift register circuits and a set of second shift register circuits. Each first shift register circuit in the set of first shift register circuits includes a first logic unit, a first output switch, a second output switch and a first switch unit. The first logic unit is used for at least operating according to a first previous stage shift register signal. A first end of the first output switch is used for outputting a first current-stage shift register signal. A first terminal of the second output switch is coupled to the first terminal of the first output switch. The first switch unit is used for turning on according to a first switch signal, and turning off at least one of the first output switch and the second output switch when turning on. Each second shift register circuit in the group of second shift register circuits includes a second logic unit, a third output switch and a second switch unit. The second logic unit is used for at least operating according to a second previous stage shift register signal. A first end of the third output switch is used for outputting a second current-stage shift register signal. A first terminal of the fourth output switch is coupled to the first terminal of the third output switch. The second switch unit is used for turning on according to a second switch signal, and turning off at least one of the third output switch and the fourth output switch when turning on.

Description of drawings

FIG. 1 is a schematic diagram of a display device according to an embodiment of the present application.

FIG. 2 is a schematic diagram of a driving device in a display device according to an embodiment of the present application.

FIG. 3 is a circuit diagram of a shift register circuit in a display device according to an embodiment of the present application.

FIG. 4 is a schematic diagram of a driving device in a display device according to an embodiment of the present application.

FIG. 5 is a schematic diagram of a driving device in a display device according to an embodiment of the present application.

FIG. 6 is a schematic diagram of a driving device in a display device according to an embodiment of the present application.

FIG. 7 is a schematic diagram of a driving device in a display device according to an embodiment of the present application.

Among them, reference signs:

100: display device

110: drive device

200: drive device

210: drive unit

220: drive unit

211: shift temporary storage circuit

310: logic unit

320: switch unit

330: output unit

332, 334, 322, 324: switch

500: drive unit

510, 520: drive unit

600: drive device

601, 602: decoder

700: drive device

710: welding area

E(1)～E(n): light emitting device

GL(1)～GL(n): gate line

G(1,1)～G(1,n): shift temporary storage circuit

G(2,1)～G(2,n): shift temporary storage circuit

SW(1,1), SW(2,1): switch signal

SL(1,1), SL(2,1): switch line

S(1)～S(n): signal

STV: start signal

CK1, CK2, CK3: clock signal

T1～T6: switch

VGL: enable voltage signal

Q'(n), Q(n), B(n)

VGH: disabled voltage signal

Rst: reset signal

C1: capacitance

SL(1,2)～SL(1,n): switch line

SL(2,2)～SL(2,m): switch line

SW(1,2)～SW(1,n): switch signal

SW(2,2)～SW(2,m): switch signal

G(1,2n-1), G(1,2n): shift temporary storage circuit

G(2,2m-1), G(2,2m): shift temporary storage circuit

d(1,1)～d(1,i): coded signal

d(2,1)～d(2,j): coded signal

Detailed ways

Herein, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although terms such as "first", "second", ... etc. are used herein to describe different elements, these terms are only used to distinguish elements or operations described with the same technical terms. Unless clearly indicated by the context, the terms do not imply any particular order or sequence, nor are they intended to be limiting of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

The following will disclose multiple implementations of this case with diagrams, and for the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the present case. That is, in some embodiments of the present disclosure, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some existing conventional structures and elements will be shown in a simple and schematic manner in the drawings.

FIG. 1 is a schematic diagram of a display device according to an embodiment of the present application. Referring to FIG. 1 , the display device 100 includes a driving device 110 , light emitting devices E( 1 )˜E(n) and gate lines GL( 1 )˜GL(n). In some embodiments, the driving device 110 is coupled to the light emitting devices E( 1 )-E(n) and other driving devices through the gate lines GL( 1 )-GL(n), wherein n is a positive integer. In some embodiments, the driving device 110 is used for providing gate signals to the light emitting devices E( 1 )˜E(n).

In some embodiments, the driving device 110 is designed in the display area (Active Area) of the display device 100 . In some embodiments, the driving device 110 includes a plurality of Gate On Array (Gate On Array) circuits. In some embodiments, the driving device 110 includes multiple shift register circuits. In some embodiments, the light emitting devices E( 1 )˜E(n) include light emitting diodes or other types of light emitting elements.

FIG. 2 is a schematic diagram of a driving device in a display device according to an embodiment of the present application. Referring to FIG. 2 and FIG. 1 , the driving device 200 is an embodiment of the driving device 110 , and the driving device 200 includes a driving unit 210 and a driving unit 220 . In some embodiments, the driving unit 210 includes multi-stage shift register circuits G(1,1)-G(1,n), and the drive unit 220 includes multi-stage shift register circuits G(2,1)-G (2,n). In some embodiments, the shift register circuit G(1,n) of the nth stage in the driving unit 210 is the shift register circuit 211 .

In some embodiments, the drive unit 210 is a repair unit of the drive unit 220 . In some embodiments, the drive unit 220 is a repair unit of the drive unit 210 . In some embodiments, the driving unit 210 (or the driving unit 220) is turned off when abnormal, and the driving unit 220 (or the driving unit 210) as a repair unit is used to provide normal signals to the gate lines GL(1)˜ GL(n) enables the display device 100 to operate normally.

In some embodiments, the switch signal SW(1,1) and the switch signal SW(2,1) are used to turn off the shift register circuits G(1,1)-G(1,n) and the shift register circuits respectively. Circuit G(2,1)~G(2,n). In some embodiments, the switch signal SW(1,1) and the switch signal SW(2,1) are provided to the shift register circuit G( 1,1)~G(1,n) and shift register circuits G(2,1)~G(2,n).

In some embodiments, the shift register circuits G(1,1)~G(1,n) and the shift register circuits G(2,1)~G(2,n) are used to The shift register signal of the previous stage is received and the shift register signal of the present stage is output to the corresponding gate line of the present stage.

For example, in some embodiments, the front-stage gate line corresponding to the shift register circuit G(1,2) and G(2,2) is GL(1), and the corresponding shift register circuit G(1 ,2) and G(2,2)'s current gate line is GL(2). The previous stage shift register signal of the shift register circuit G(1,2) is the first stage shift register signal, that is, the signal S(1). The shift register signal of the current stage of the shift register circuit G(1,2) is the second stage shift register signal, that is, the signal S(2). In some embodiments, the previous shift register signal of the shift register circuit G(1,n) is the (n−1)th stage shift register signal, ie, the signal S(n−1). The shift register signal of the current stage of the shift register circuit G(1,n) is the shift register signal of the nth stage, that is, the signal S(n).

In some embodiments, the shift register circuits G(1,1)˜G(1,n) and the shift register circuits G(2,1)˜G(2,n) are used to receive the start signal STV and the clock signals CK1, CK2, CK3 to normally perform the function of the shift register circuit.

FIG. 3 is a circuit diagram of a shift register circuit in a display device according to an embodiment of the present application. Please refer to FIG. 3 . FIG. 3 is a circuit diagram of the n-th stage shift register circuit 211 shown in FIG. 2 . The shift register circuit 211 includes a logic unit 310 , a switch unit 320 and an output unit 330 .

In some embodiments, the logic unit 310 operates according to the previous shift register signal S(n−1). In some embodiments, the output unit 330 is used to output the shift register signal S(n) of the current stage. In some embodiments, the switch unit 320 is turned on according to the switch signal SW(1,1), and turns off one or more circuit elements in the output unit 330 when turned on. In some embodiments, the switch unit 320 turns off one or more circuit elements in the output unit 330 when the shift register circuit 211 is abnormal, so that the output unit 330 cannot output an abnormal signal.

In some embodiments, the logic unit 310 includes switches T1 - T5 . In some embodiments, the control end of the switch T1 is used to receive the signal S(n-1), the first end of the switch T1 is used to receive the enable voltage signal VGL (for example, a low-level voltage signal), and the first end of the switch T1 Both terminals are coupled to node Q'(n). In some embodiments, the control terminal of the switch T3 is coupled to the node Q'(n), the first terminal of the switch T3 is coupled to the node B(n), and the second terminal of the switch T3 is used to receive the disable voltage signal VGH (for example , high level voltage signal). In some embodiments, the control terminal of the switch T2 and the first terminal of the switch T2 are used to receive the clock signal CK2 , and the second terminal of the switch T2 is coupled to the node B(n). In some embodiments, the control terminal of the switch T5 and the first terminal of the switch T5 are used to receive the reset signal Rst, and the second terminal of the switch T5 is coupled to the node B(n). In some embodiments, the control terminal of the switch T4 is coupled to the node B(n), the first terminal of the switch T4 is coupled to the node Q'(n), and the second terminal of the switch T4 is used to receive the disable voltage signal VGH.

In some embodiments, the output unit 330 includes a switch 332 , a switch 334 and a capacitor C1 . In some embodiments, the control end of the switch 332 is coupled to the node Q(n), the first end of the switch 332 is used to output the primary shift register signal S(n), and the second end of the switch 332 is used to receive Clock signal CK1. In some embodiments, the control terminal of the switch 334 is coupled to the node B(n), the first terminal of the switch 334 is coupled to the first terminal of the switch 332 , and the second terminal of the switch 334 is used for receiving the disable voltage signal VGH. In some embodiments, a first terminal of the capacitor C1 is coupled to the node Q(n), and a second terminal of the capacitor C1 is coupled to the first terminal of the switch 332 .

In some embodiments, the switch 332 and the switch 334 are used to determine the voltage level of the signal S(n) output by the shift register circuit 211 , so the switch 332 and the switch 334 are also called output switches.

In some embodiments, the output unit 330 further includes a switch T6. In some embodiments, the control end of the switch T6 is used to receive the enabling voltage signal VGL, the first end of the switch T6 is coupled to the node Q'(n), and the second end of the switch T6 is coupled to the node Q(n). In some embodiments, the enable voltage signal VGL is a DC voltage signal, so the switch T6 is kept in the on state, so that the voltage level of the node Q'(n) is kept equal to the voltage level of the node Q(n).

In some embodiments, the switch unit 320 includes a switch 322 and a switch 324 . The control end of the switch 322 and the control end of the switch 324 are used to receive the switch signal SW(1,1), the first end of the switch 322 and the first end of the switch 324 are used to receive the disable voltage signal VGH, and the second end of the switch 322 A terminal of the switch 324 is coupled to the node Q′(n), and a second terminal of the switch 324 is coupled to the node B(n). In some embodiments, the second terminal of the switch 322 is coupled to the node Q(n).

In some embodiments, when the shift register circuit 211 is abnormal, the switch 322 is used to turn on according to the switch signal SW(1,1), and when turned on, provide the disable voltage signal VGH to the control terminal of the switch 332 to Turning off the switch 332 makes the switch unit 320 unable to output signals. In some embodiments, when the shift register circuit 211 is abnormal, the switch 324 is used to turn on according to the switch signal SW(1,1), and when turned on, provide the disable voltage signal VGH to the control terminal of the switch 334 for Turning off the switch 334 makes the switch unit 320 unable to output signals.

In some embodiments, switch unit 320 includes switch 322 instead of switch 324 . In some embodiments, switch unit 320 includes switch 324 instead of switch 322 . In some embodiments, the switch unit 320 includes a switch 322 and a switch 324 .

In some embodiments, the switches 322, 324, 332, 334 and the switches T1-T6 may be implemented by P-type metal-oxide-semiconductor transistors (PMOS) or N-type metal-oxide-semiconductor transistors (NMOS) or other circuit elements with switching functions. .

FIG. 4 is a schematic diagram of a driving device in a display device according to an embodiment of the present application. Please refer to FIG. 4 , the shift register circuit 211 shown in FIG. 4 is in an abnormal state. Please refer to FIG. 3 and FIG. 4 , in some embodiments, the switch unit 320 is used to receive the switch signal SW(1,1) when the shift register circuit 211 is abnormal, and turn on according to the switch signal SW(1,1). And at least one of the switch 332 and the switch 334 is turned off. In some embodiments, when the shift register circuit 211 is abnormal, the switch 322 is turned on and provides the disable voltage signal VGH to the node Q'(n) or the node Q(n), so that the switch 332 is turned off. In some embodiments, when the shift register circuit 211 is abnormal, the switch 324 is turned on and provides the disable voltage signal VGH to the node B(n), so that the switch 334 is turned off.

In some embodiments, when the shift register circuit 211 is abnormal, the switch unit 320 turns off at least one of the switch 332 and the switch 334 to prevent the abnormal signal from being output to the gate line GL(n).

FIG. 5 is a schematic diagram of a driving device in a display device according to an embodiment of the present application. Please refer to FIG. 5 and FIG. 1 , the driving device 500 is an embodiment of the driving device 110 . Please refer to FIG. 5 and FIG. 2 , compared with the driving device 200, the driving device 500 further includes a plurality of switch lines SL(1,2)˜SL(1,n) and SL(2,2)˜SL(2,m), They are respectively used to provide a plurality of corresponding switch signals SW(1,2)~SW(1,n) and SW(2,2)~SW(2,m) to corresponding sets of shift register circuits, wherein n and m are both positive integers.

Please refer to FIG. 5 , in some embodiments, each of the switch lines SL(1,1)-SL(1,n) and SL(2,1)-SL(2,m) is coupled to a group The corresponding shift register circuit. In the embodiment shown in FIG. 5 , each set of shift register circuits coupled to each switch line includes two shift register circuits. For example, in the embodiment shown in FIG. 5 , the set of shift register circuits coupled to the switch line SL(1,1) includes shift register circuits G(1,1) and G(1,2 ), the group of shift register circuits is used to receive the switch signal SW(1,1). In some embodiments, the set of shift register circuits coupled to the switch line SL(2,1) includes shift register circuits G(2,1) and G(2,2), and the set of shift register circuits The circuit is used for receiving the switch signal SW(2,1). In some embodiments, the set of shift register circuits coupled to the switch line SL(1,n) includes shift register circuits G(1,2n−1) and G(1,2n), and the set of shift register circuits The temporary storage circuit is used for receiving the switch signal SW(1,n). In some embodiments, the set of shift register circuits coupled to the switch line SL(2,m) includes shift register circuits G(2,2m−1) and G(2,2m), the set of shift register circuits The temporary storage circuit is used for receiving the switch signal SW(2,m).

In the embodiment shown in FIG. 5 , each switch line coupled to each of the switch lines SL(1,1)-SL(1,n) and SL(2,1)-SL(2,m) The group shift register circuit includes two shift register circuits, but the invention is not limited thereto. In some other embodiments, each set of shift register circuits may have different numbers of shift register circuits. For example, in some embodiments, the set of shift register circuits coupled to the switch line SL(1,1) includes K1 shift register circuits, and the set of shift register circuits coupled to the switch line SL(1,2) The shift register circuit includes K2 shift register circuits, and so on, the set of shift register circuits coupled to the switch line SL(1,n) includes Kn shift register circuits. Similarly, in some embodiments, the set of shift register circuits coupled to the switch line SL(2,1) includes L1 shift register circuits, and the set of shift register circuits coupled to the switch line SL(2,2) The bit temporary storage circuit includes L2 shift temporary storage circuits, and so on, the set of shift temporary storage circuits coupled to the switch line SL(2,m) includes Lm shift temporary storage circuits, wherein K1, K2, ... , Kn and L1, L2..., Lm are all positive integers. In different embodiments, K1, K2, . positive integer.

In some embodiments, when any shift register circuit in the set of shift register circuits coupled to the switch line is abnormal, the switch line provides a switch signal to turn off the set of shift register circuits All shift register circuits. In some embodiments, when one group of shift register circuits is closed so that it cannot output signals to the corresponding gate lines, another group or more groups of shift register circuits coupled to these gate lines operate normally to provide normal gate signal to these gate lines.

For example, in the embodiment shown in FIG. 5, if the shift register circuit G(1,3) is abnormal, the switch line SL(1,2) coupled to the shift register circuit G(1,3) ) is used to provide switch signal SW(1,2) to all shift register circuits in the set of shift register circuits coupled with switch line SL(1,2) (in the embodiment shown in FIG. 5 That is, the shift register circuits G(1,3) and G(1,4)), so that the shift register circuits G(1,3) and G(1,4) cannot output signals to the corresponding gate lines GL(3) and GL(4), so the abnormal signal will not be output from this set of shift temporary storage circuits to other parts of the drive device 500. At this time, the shift temporary storage circuits G(2,3) and G(2 ,4) Normal operation, so the switch line SL(2,2) will not provide the switch signal SW(2,2) to close the shift register circuit G(2,3) and G(2,4), so G( 2,3) and G(2,4) can still provide normal gate signals to the gate lines GL(3) and GL(4).

Please refer to FIG. 5 and FIG. 2 , the driving units 510 and 520 are an embodiment of the driving units 210 and 220 . In some embodiments, the driving unit 510 includes two shift register circuits G(1,1) and G(1,2). Similarly, the drive unit 520 includes two shift register circuits G(2,1 ) and G(2,2).

FIG. 6 is a schematic diagram of a driving device in a display device according to an embodiment of the present application. Please refer to FIG. 6 and FIG. 1 , the driving device 600 is an embodiment of the driving device 110 . Compared with the driving device 500 in FIG. 5 , the driving device 600 further includes decoders 601 and 602 .

Please refer to FIG. 6 , decoders 601 and 602 output corresponding switching signals SW(1,1 )~SW(1,n) and SW(2,1)~SW(2,m), wherein i and j are both positive integers.

In some embodiments, n is less than or equal to 2 to the i power, and m is less than or equal to 2 to the j power. In some embodiments, n is greater than i, so a small number of encoded signals d(1,1)˜d(1,i) can be input to the decoder 601 to provide a large number of switching signals SW(1,1) ~SW(1,n). In some embodiments, m is greater than j, so a small number of encoded signals d(2,1)˜d(2,j) can be input to the decoder 602 to provide a large number of switching signals SW(2,1) ~SW(2,m).

FIG. 7 is a schematic diagram of a driving device in a display device according to an embodiment of the present application. Please refer to FIG. 7 and FIG. 1 , the driving device 700 is an embodiment of the driving device 110 . In some embodiments, the driving device 700 includes a pad 710 , and the pad 710 is coupled to the shift register circuits G(1,2) and G(2,2). In some embodiments, the driving device 700 is a hybrid driving device, which can switch lines SL(1,1)~SL(1,n) and SL(2,1)~SL(2,m) providing switch signals SW(1,1)~SW(1,n) and SW(2,1)~SW(2,m) to corresponding sets of shift register circuits to close abnormal shift register circuits, Laser cutting can also be performed through the welding area 710 to disconnect the electrical coupling relationship between the at least one shift register circuit and the drive device 700 when at least one shift register circuit in the drive device 700 is abnormal.

For example, when the shift register circuits G(1,1), G(1,3) and G(2,4) are abnormal, the switch line SL(1,1) provides the switch signal SW(1,1) To close the shift register circuits G(1,1) and G(1,2) coupled to the switch line SL(1,1), so that G(1,1) cannot output abnormal signals to the driving device 700, At the same time, since the shift register circuits G(1,3) and G(2,4) are in the welding area 710, the welding area 710 can perform laser cutting to disconnect the shift register circuit G(1,3 ) and G(2,4) are electrically coupled to the driving device 700 so that the shift register circuits G(1,3) and G(2,4) cannot output signals to the driving device 700 .

In some embodiments, the display device 100 includes some regions lacking space to provide space for the bonding area 710, and laser cutting cannot be performed in these regions to disconnect the shift register circuit and the driving device 700 in these regions. Therefore, the switching signal can be provided through the switch line to close the shift register circuits, so that the shift register circuits cannot output signals to the driving device 700 .

In some embodiments, the pad 710 includes multiple pads, and the multiple pads may be coupled to different shift register circuits, or may be coupled to the same shift register circuit.

The various forms of the driving device 110 provided in the above-mentioned embodiments are used to illustrate the present invention rather than limit the present invention. In other embodiments, the forms of the driving device 110 can also be designed as other appropriate forms. .

To sum up, the driving device and the display device according to an embodiment of the present invention can shut down the shift register circuit in a non-destructive way when the shift register circuit is abnormal, without digging holes in the metal layer and also The possibility of laser cutting failure is avoided, and the abnormal shift temporary storage circuit cannot output abnormal signals by closing the circuit elements in the shift temporary storage circuit through the switch signal.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

Claims (10)

1. A driving device, characterized by comprising:

the multi-stage shift register circuits are coupled in series in sequence, wherein each of the shift register circuits comprises:

a logic unit for operating according to at least one pre-shift register signal;

an output unit, comprising:

a first output switch, a control end of the first output switch is coupled to the logic unit at a first node, and a first end of the first output switch is used for outputting a current level shift register signal; and

a second output switch, a control end of the second output switch is coupled to the logic unit at a second node, and a first end of the second output switch is coupled to the first end of the first output switch; and

the switch unit is used for being conducted according to a switch signal and closing at least one of the first output switch and the second output switch when being conducted.

2. The driving apparatus as claimed in claim 1, wherein the switching unit is configured to receive the switching signal when any one of the shift register circuits is abnormal, and turn off at least one of the first output switch and the second output switch according to the switching signal.

3. The driving apparatus as claimed in claim 1, wherein the switching unit comprises:

the switch is used for being conducted according to the switch signal, a first end of the switch is used for receiving a voltage signal, a second end of the switch is coupled with the first node or the second node, and the voltage signal has a forbidden voltage level when the switch is conducted.

4. The driving apparatus as claimed in claim 1, wherein the switching unit comprises:

the first switch is used for being conducted according to the switch signal, a first end of the first switch is used for receiving a voltage signal, a second end of the first switch is coupled with the first node, and when the first switch is conducted, the voltage signal has a forbidden voltage level; and

the second switch is turned on according to the switch signal, a first end of the second switch is used for receiving the voltage signal, and a second end of the second switch is coupled to the second node.

5. The driving apparatus as recited in claim 1 wherein said logic unit is configured to adjust a voltage level of said first node and a voltage level of said second node according to said pre-shift register signal to control said first output switch and said second output switch.

6. A display device, comprising:

a set of first shift register circuits, each first shift register circuit of the set of first shift register circuits comprising:

a first logic unit for operating according to at least a first pre-shift register signal;

a first output switch, a first end of which is used for outputting a first current level shift register signal;

a second output switch, a first end of which is coupled with the first end of the first output switch; and

the first switch unit is used for being conducted according to a first switch signal and closing at least one of the first output switch and the second output switch when being conducted; and

a set of second shift register circuits, each of the set of second shift register circuits comprising:

a second logic unit for operating according to at least a second pre-shift register signal;

a third output switch, a first end of which is used for outputting a second level shift register signal;

a fourth output switch, a first end of which is coupled to the first end of the third output switch; and

the second switch unit is used for being conducted according to a second switch signal and closing at least one of the third output switch and the fourth output switch when being conducted.

7. The display device according to claim 6, wherein the first switching unit is configured to receive the first switching signal when any one of the first shift register circuits is abnormal, and turn off at least one of the first output switch and the second output switch according to the first switching signal.

8. The display device of claim 6, further comprising:

the shift register circuits comprise a group of n shift register circuits, wherein n is a positive integer greater than or equal to three, and each n shift register circuit in the group of n shift register circuits comprises:

an nth logic unit for operating according to at least an nth previous stage shift register signal;

a (2 n-1) th output switch, a first end of the (2 n-1) th output switch is used for outputting an nth shift register signal;

a 2n output switch, a first end of the 2n output switch is coupled to the first end of the 2n output switch; and

an nth switch unit for switching on according to an nth switch signal and closing at least one of the (2 n-1) th output switch and the 2 n-th output switch when switching on.

9. The display device of claim 8, further comprising:

and the decoder is used for outputting a plurality of switching signals according to a plurality of coding signals, wherein the switching signals comprise the first switching signal to the nth switching signal.

10. The display device of claim 6, further comprising:

and the at least one welding area is coupled with the group of first shift register circuits and is used for executing laser cutting to disconnect the electric coupling relation between the at least one shift register circuit and the display device when the at least one shift register circuit in the driving device is abnormal.

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