CN112527237B - Audio interface circuit, control method thereof and audio equipment - Google Patents
Audio interface circuit, control method thereof and audio equipment Download PDFInfo
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Abstract
The invention provides an audio interface circuit, a control method thereof and audio equipment, wherein the method comprises the following steps: the arbitration logic circuit measures the clock frequency offset between the second audio interface and the first audio interface; the arbitration logic circuit acquires a first current value of a clock adjustment parameter according to the clock frequency offset; the arbitration logic detects a buffer status of the first audio interface, increases the adjustment amount in the first current value and increases the number of clocks in the first current value if a first buffer flag event is detected, and decreases the adjustment amount in the first current value and increases the number of clocks in the first current value if a second buffer flag event is detected. The invention can effectively relieve the problem of audio noise caused by clock deviation between the audio interface of a master mode and the audio interface of a slave mode, and is simple and efficient compared with the prior art.
Description
Technical Field
The invention relates to the technical field of audio, in particular to an audio interface circuit, a control method thereof and audio equipment.
Background
When audio data is transmitted between different audio devices (such as a sound card, a mobile phone, a computer, a sound box, and the like), due to different sources of clocks of the different devices, overflow or underflow of data is inevitable during receiving and transmitting, and due to continuous audio data, frame loss is likely to occur when overflow or underflow occurs, thereby generating audio noise. For example, although theoretically 12M crystal oscillators are provided for two different audio devices, I2S frequency is 48KHz, clock sources of the two audio devices are relatively independent, and due to natural clock deviation (generally not greater than ± 100 PPM), clock deviation between the two audio devices causes asynchronous data transmission, and data inevitably overflows or underflows during receiving and transmitting, thereby easily causing phenomena such as sound loss or distortion.
In order to solve the above problems, the prior art mostly achieves the purpose of synchronization by recovering a clock, for example, a phase-locked loop synchronization or a gaderner algorithm synchronization mode is adopted, but the modes are complex to implement.
Disclosure of Invention
Based on the above situation, a primary objective of the present invention is to provide an audio interface circuit, a control method thereof, and an audio device, which can effectively alleviate the problem of audio noise caused by clock skew between an audio interface in a master mode and an audio interface in a slave mode, and are simpler and more efficient than the prior art.
In order to achieve the above object, a technical solution adopted by the present invention provides a method for controlling an audio interface circuit, where the audio interface circuit includes an arbitration logic circuit, a first audio interface, and a second audio interface, and the first audio interface is configured to send audio data received by the second audio interface, and the method includes:
step S100: the arbitration logic measures a clock frequency offset between the second audio interface operating in a slave mode and the first audio interface operating in a master mode;
step S200: the arbitration logic circuit obtains a first current value of a clock adjustment parameter in pre-stored information according to the clock frequency offset, and then sends a clock adjustment trigger signal to the first audio interface, so that the first audio interface starts to execute a clock frequency adjustment task once according to the first current value, wherein the clock adjustment parameter comprises the number of clocks needing to be adjusted in a single clock frequency adjustment task and an adjustment amount for adjusting an initial value of a clock frequency division counter of the first audio interface;
step S300: the arbitration logic circuit detects a cache state of the first audio interface, if a first cache flag event that a cache change trend is reduced is detected, the step S400 is executed, and if a second cache flag event that the cache change trend is increased is detected, the step S500 is executed;
step S400: the arbitration logic circuit increases the adjustment amount in the first current value and increases the clock number in the first current value to obtain a second current value of the clock adjustment parameter, and then sends a clock adjustment trigger signal to the first audio interface to enable the first audio interface to start executing a clock frequency adjustment task once according to the second current value;
step S500: and the arbitration logic circuit reduces the adjustment amount in the first current value and increases the clock number in the first current value to obtain a third current value of the clock adjustment parameter, and then sends a clock adjustment trigger signal to the first audio interface to enable the first audio interface to start executing a clock frequency adjustment task once according to the third current value.
Further, the first cache flag event is 1/2empty flag event, and the second cache flag event is 1/2 full flag event.
Further, the step S400 further includes: the arbitration logic circuit detects a cache state of the first audio interface, if the arbitration logic circuit detects a third cache flag event, the arbitration logic circuit increases the adjustment amount in the second current value and increases the number of clocks in the second current value to obtain a fourth current value of a clock adjustment parameter, and then sends a clock adjustment trigger signal to the first audio interface to enable the first audio interface to start executing a clock frequency adjustment task once according to the fourth current value, wherein the third cache flag event is a null flag event or a null flag event.
The step S500 further includes: the arbitration logic circuit detects a cache state of the first audio interface, and if the arbitration logic circuit detects a fourth cache flag event, the arbitration logic circuit decreases the adjustment amount in the third current value and increases the clock number in the third current value to obtain a fifth current value of a clock adjustment parameter, and then sends a clock adjustment trigger signal to the first audio interface, so that the first audio interface starts to execute a clock frequency adjustment task once according to the fifth current value, and the fourth cache flag event is a full flag event or a full flag event.
Further, in step S100, the arbitration logic measures a clock frequency offset between the second audio interface and the first audio interface by:
when the audio data received by the second audio interface is sent out by the first audio interface, the arbitration logic circuit detects the cache state of the first audio interface, and if an empty flag event is detected, the value of a clock frequency division counter of the first audio interface is controlled to be equal to
If the full flag event is detected, controlling the value of a clock division counter of the first audio interface to be
And measuring the time from the buffer status of the first audio interface to being full to empty
Wherein
is a preset value and is positive;
the arbitration logic calculates a clock frequency offset between the second audio interface and the first audio interface;
wherein,
is a clock frequency offset between the second audio interface and the first audio interface,
is a value of a buffer depth of the first audio interface,
in order to be the system clock frequency,
and the initial preset value of the clock frequency division counter of the first audio interface is obtained.
In order to achieve the above object, the present invention further provides an audio interface circuit, where the audio interface circuit includes an arbitration logic circuit, a first audio interface capable of operating in a master mode, and a second audio interface capable of operating in a slave mode, where the first audio interface is used to transmit audio data received by the second audio interface, and the arbitration logic circuit can implement the above control method.
Further, the audio interface circuit further comprises a buffer circuit, and the buffer circuit is used for buffering the first audio interface and the second audio interface.
Further, the buffer space of the buffer circuit is a piece of RAM.
Further, the first audio interface is one of an I2S interface, a USB interface, and an SPDIF interface, and the second audio interface is one of an I2S interface, a USB interface, and an SPDIF interface.
In order to achieve the above object, the present invention further provides an audio device, including the above audio interface circuit.
Further, the audio device is a sound card, a PC, a mobile phone, a tablet PC, or a sound box.
The control method of the audio interface circuit provided by the invention comprises the steps of measuring the clock frequency deviation between a second audio interface and a first audio interface in the audio interface circuit, obtaining a first current value of a corresponding clock adjustment parameter according to the clock frequency deviation, detecting the cache state of the first audio interface by an arbitration logic circuit when the second audio interface and the first audio interface carry out audio transmission, and adjusting the clock frequency of the first audio interface by using the cache mark and the first current value of the cache state to reduce the occurrence of overflow or underflow, thereby effectively relieving the problem of audio noise caused by clock deviation, being simpler and more efficient compared with the prior art, and avoiding the cost increase caused by adopting a complex synchronization algorithm.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a flowchart of a control method of an audio interface circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an audio interface circuit according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a clock frequency adjustment task performed once on a first audio interface according to an embodiment of the present invention;
fig. 4 is a schematic diagram of two audio devices for audio transmission according to an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in order to avoid obscuring the nature of the present invention, well-known methods, procedures, and components have not been described in detail.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
It should be noted that step numbers (letter or number numbers) are used to refer to some specific method steps in the present invention only for the purpose of convenience and brevity of description, and the order of the method steps is not limited by letters or numbers in any way. It will be clear to a person skilled in the art that the order of the steps of the method in question, as determined by the technology itself, should not be unduly limited by the presence of step numbers.
Referring to fig. 1, fig. 1 is a flowchart of a control method of an audio interface circuit according to an embodiment of the present invention, where, referring to fig. 2, the audio interface circuit includes an arbitration logic circuit 103, a first audio interface 101 operable in a master mode, and a second audio interface 102 operable in a slave mode, where the first audio interface 101 is configured to send audio data received by the second audio interface 102, a buffer 104 is a buffer of the second audio interface 102, and a buffer 105 is a buffer of the first audio interface 101, and the method includes:
step S100: the arbitration logic measures a clock frequency offset between the second audio interface operating in a slave mode and the first audio interface operating in a master mode;
when audio transmission is performed between the audio device including the arbitration logic circuit and another audio device, the second audio interface 102 is connected to the another audio device, the second audio interface 102 operates in the slave mode, the clock frequency of the second audio interface 102 is determined by the another audio device, and the clock frequency offset between the second audio interface 102 and the first audio interface 101 is the clock frequency between the two audio devices;
step S200: the arbitration logic circuit obtains a first current value of a clock adjustment parameter in pre-stored information according to the clock frequency offset, and then sends a clock adjustment trigger signal to the first audio interface, so that the first audio interface starts to execute a clock frequency adjustment task once according to the first current value, wherein the clock adjustment parameter comprises a clock number B which needs to be adjusted in a single clock frequency adjustment task and an adjustment amount a for adjusting an initial value of a clock frequency division counter of the first audio interface, wherein the adjustment amount is a value which indicates that the clock frequency division counter is increased when positive, and the adjustment amount is a value which indicates that the clock frequency division counter is decreased when negative;
for example, the pre-stored information may be a configuration table, where the configuration table includes a corresponding relationship between different clock frequency offsets and different first current values of the clock adjustment parameter;
referring to fig. 2, Wclk is a clock of the first audio interface, Sysclk is a system clock of the audio device in which the audio interface circuit is located, and the clock adjustment parameters include a clock number B to be adjusted and an adjustment amount a for adjusting an initial value of a clock division counter of the first audio interface in a single clock frequency adjustment task performed on the first audio interface, that is, when the clock frequency adjustment task is performed once on the first audio interface, B clocks of the first audio interface need to be adjusted, and a cycle of each clock to be adjusted increases or decreases | a | cycles of the system clock;
it is understood that, in the configuration table, if the clock of the first audio interface is fast, a in the first current value is positive, and if the clock of the first audio interface is slow, a in the first current value is negative;
in the above pre-stored information, when the clock frequency offset is positive (positive indicates that the clock of the first audio interface is fast), the larger the clock frequency offset is, the larger the clock number B is, and the adjustment amount a is, and when the clock frequency offset is negative (negative indicates that the clock of the first audio interface is slow), the smaller the clock frequency offset is (the larger the absolute value is), the larger the clock number B is, and the adjustment amount a is reduced (the absolute value is increased);
step S300: the arbitration logic circuit detects a cache state of the first audio interface, if a first cache flag event that a cache change trend is decreasing is detected, step S400 is executed, and if a second cache flag event that the cache change trend is increasing is detected, step S500 is executed;
for example, the first cache flag event may be 1/2 null flag event or will null flag event;
for example, the second cache flag event may be 1/2 a full flag event or a to full flag event;
step S400: the arbitration logic circuit increases the adjustment amount in the first current value and increases the clock number in the first current value to obtain a second current value of the clock adjustment parameter, and then sends a clock adjustment trigger signal to the first audio interface to enable the first audio interface to start executing a clock frequency adjustment task once according to the second current value;
if the arbitration logic circuit detects a first buffer flag event (if the first buffer flag event is 1/2 null flag event or will null flag event), it indicates that the clock frequency of the first audio interface is faster and the values of a and B need to be increased, and then the arbitration logic circuit sends a corresponding clock adjustment trigger signal to the first audio interface, so that the first audio interface is enabled to send a corresponding clock adjustment trigger signal
And continuously adjusting the B clocks, so as to accelerate the speed and slow down the clock of the first audio interface, reduce the clock frequency deviation between the second audio interface and the first audio interface as soon as possible, reduce the audio transmission delay,
divide the adjusted value of the counter by the clock of the first audio interface,
an initial preset value of a clock frequency division counter of the first audio interface is set;
step S500: and the arbitration logic circuit reduces the adjustment amount in the first current value and increases the clock number in the first current value to obtain a third current value of the clock adjustment parameter, and then sends a clock adjustment trigger signal to the first audio interface to enable the first audio interface to start executing a clock frequency adjustment task once according to the third current value.
If the arbitration logic circuit detects a second buffer flag event (e.g. the first buffer flag event is 1/2 full flag event or will be full flag event), it indicates that the clock frequency of the first audio interface is slow and needs to decrease the value of a and increase the value of B, and then the arbitration logic circuit sends a corresponding clock adjustment trigger signal to the first audio interface to enable the first audio interface to adjust the clock frequency of the first audio interface
Therefore, the speed is increased, the clock of the first audio interface is increased, the clock frequency offset between the second audio interface and the first audio interface is reduced as soon as possible, and the audio transmission delay is reduced.
In the control method of the audio interface circuit provided by the embodiment of the invention, the clock frequency offset between the second audio interface and the first audio interface in the audio interface circuit is measured, the first current value of the corresponding clock adjustment parameter is obtained according to the clock frequency offset, when the second audio interface and the first audio interface perform audio transmission, the arbitration logic circuit detects the cache state of the first audio interface, and adjusts the clock frequency of the first audio interface by using the cache mark and the first current value of the cache state, so as to reduce the occurrence of overflow or underflow conditions, effectively alleviate the problem of audio noise caused by the clock offset, and compared with the prior art, the control method is simpler and more efficient, and avoids the cost increase caused by adopting a complex synchronization algorithm.
For example, in one embodiment, the first buffer flag event is 1/2empty flag event, and the second buffer flag event is 1/2 full flag event, so that the clock of the first audio interface can be adjusted in time.
Preferably, in an embodiment, the step S400 further includes: the arbitration logic circuit detects a cache state of the first audio interface, if the arbitration logic circuit detects a third cache flag event, the arbitration logic circuit increases the adjustment amount in the second current value and increases the clock number in the second current value to obtain a fourth current value of a clock adjustment parameter, and then sends a clock adjustment trigger signal to the first audio interface to enable the first audio interface to start executing a clock frequency adjustment task once according to the fourth current value, wherein the third cache flag event is a null flag event or a null flag event;
the step S500 further includes: the arbitration logic circuit detects a cache state of the first audio interface, and if the arbitration logic circuit detects a fourth cache flag event, the arbitration logic circuit decreases the adjustment amount in the third current value and increases the clock number in the third current value to obtain a fifth current value of a clock adjustment parameter, and then sends a clock adjustment trigger signal to the first audio interface, so that the first audio interface starts to execute a clock frequency adjustment task once according to the fifth current value, and the fourth cache flag event is a full flag event or a full flag event.
In other words, in the above process, if the trend of overflow or underflow is not changed after the clock frequency adjustment task is executed once, and the trend of overflow or underflow is further increased, the clock frequency adjustment task needs to be executed once again, and in the clock frequency adjustment task, the clock adjustment parameter needs to be further adjusted, that is, the adjustment speed of the clock frequency needs to be increased, so as to avoid overflow or underflow.
For example, in an embodiment, if the arbitration logic circuit detects that the 1/2empty flag bit of the buffer memory 105 is valid (i.e. 1/2empty flag event), it indicates that the clock frequency of the first audio interface is fast, and it needs to increase the values a and B (e.g. a may be increased by 2, B may be increased by 25% on the basis of the first current value, and a second current value of the clock adjustment parameter is obtained), and the clock adjustment parameter update sends a corresponding clock adjustment trigger signal to the first audio interface, so that it performs a clock frequency adjustment task, and then, if it detects that the empty flag bit of the buffer memory 105 is valid (i.e. empty flag event), it indicates that it needs to continue to increase the values a and B (e.g. a may be increased by 25%, B may be increased by 50% on the basis of the second current value, and a corresponding clock adjustment trigger signal is sent to the first audio interface after the clock adjustment parameter update, after that, if it is detected that the empty flag bit of the buffer 105 is valid (i.e. an empty flag event), it indicates that the values a and B still need to be increased (e.g. a may be increased by 50% and B may be increased by 75% based on the fourth current value), and after the clock adjustment parameter is updated, a clock adjustment trigger signal is sent to the first audio interface, so that the clock frequency adjustment task is executed again.
For example, in one embodiment, if the arbitration logic detects that the 1/2 full flag bit of the buffer 105 is valid (i.e. 1/2 full flag event), it indicates that the clock frequency of the first audio interface is slow, and the value of a needs to be decreased and the value of B needs to be increased (e.g. a may be decreased by 2, B may be increased by 25%, and a third current value of the clock adjustment parameter is obtained based on the first current value), the clock adjustment parameter update sends a corresponding clock adjustment trigger signal to the first audio interface, so that the first audio interface performs a clock adjustment task, and then, if the full flag bit of the buffer 105 is detected to be valid (i.e. a may be decreased by 25%, B may be increased by 50%, and a fifth current value is obtained based on the third current value), the clock adjustment parameter update sends a corresponding clock adjustment trigger signal to the first audio interface, after that, if it is detected that the full flag bit of the buffer 105 is valid (i.e. the full flag event), it indicates that the value of a still needs to be decreased and the value of B needs to be increased (e.g. a is decreased by 50% and B is increased by 75% based on the fifth current value), and the clock adjustment parameter is updated and then a corresponding clock adjustment trigger signal is sent to the first audio interface, so that the first audio interface performs the clock frequency adjustment task again.
For example, in one embodiment, in step S100, the arbitration logic measures a clock frequency offset between the second audio interface and the first audio interface by:
when the audio data received by the second audio interface is sent out by the first audio interface, the arbitration logic circuit detects the cache state of the first audio interface, and if an empty flag event is detected, the value of a clock frequency division counter of the first audio interface is controlled to be equal to
If the full flag event is detected, controlling the value of a clock division counter of the first audio interface to be
And measuring theThe time from full buffer state to empty buffer state of the first audio interface
Wherein
is a preset value and is positive;
the arbitration logic calculates a clock frequency offset between the second audio interface and the first audio interface;
wherein,
is a clock frequency offset between the second audio interface and the first audio interface,
is a value of a buffer depth of the first audio interface,
in order to be the system clock frequency,
and the initial preset value of the clock frequency division counter of the first audio interface is obtained.
In this embodiment of the present invention, the arbitration logic circuit obtains the first current value of the clock adjustment parameter from pre-stored information according to the clock frequency offset between the second audio interface and the first audio interface, where the pre-stored information may be a configuration table, the configuration table includes a correspondence between different clock frequency offsets and different first current values of the clock adjustment parameter, and the correspondence may be determined in advance through experiments, specifically, in the case of a known clock frequency offset, an MATLAB model may be established according to the following formula, a configuration table including the correspondence is generated through the MATLAB model, and then the configuration table is saved:
for example, referring to fig. 4, the audio device 1 may include the audio interface circuit described above, where the audio interface circuit includes an arbitration logic circuit, a first audio interface operable in the master mode, and a second audio interface operable in the slave mode, where buffers of the first audio interface and the second audio interface are both FIFO memories, FIFO _1 is a buffer of the second audio interface, and FIFO _2 is a buffer of the first audio interface, where the first audio interface is an I2S interface (master data stream interface) in the master mode, and the second audio interface is an I2S interface (slave data stream interface) in the slave mode;
the audio device 2 includes an interface I2S _1 for audio transmission with the first audio interface and an interface I2S _2 for audio transmission with the second audio interface, where the interface I2S _1 is an I2S interface in the slave mode, and the interface I2S _2 is an I2S interface in the master mode.
The audio device 1 is powered on and then works with default configuration, including a system clock Fs, a preset initial value Fdp of the depth of the FIFO _2, an initial preset value CNT of a clock frequency division counter of the first audio interface, a preset initial value B0 of the clock number B, and a preset initial value a0 of the adjustment amount a, for example, a0 is 8, and B0 is 64;
since the clock adjustment grain (a 0, B0) after the system is powered on is too coarse, which may cause frequent overflow of the FIFO _2 of the audio device 1, it is necessary to obtain relatively accurate a and B by the following steps:
step 1: the audio device 2 sends a section of audio to the audio device 1 through the interface I2S _2, and audio data received by the second audio interface of the audio device 1 passes through the FIFO _1 and the FIFO _2 and is sent to the interface I2S _1 of the audio device 2 through the first audio interface of the audio device 1;
in the audio apparatus 2, the time T from the point of overflow (to be full) to the point of underflow (to be empty) of the FIFO _2 is measured, and the clock frequency offset Fq between the two audio apparatuses can be determined. Assuming that the crystal frequency of the audio device 1 is slightly higher than that of the audio device 2, and the clock frequency of the audio device 1 is slightly higher than that of the audio device 2, the FIFO _2 will have underflow without clock frequency adjustment, so first, when the FIFO _2 is about to underflow, the value of the clock division counter of the first audio interface is adjusted from the initial value CNT to CNT + a0 (a 0 is a preset initial value of an adjustment amount a) to perform coarse adjustment on the clock frequency of the first audio interface from Fs/CNT to Fs/(CNT + a 0), since the coarse adjustment cannot completely clock the audio device 1 and the audio device 2 in synchronization, the FIFO _2 will reach an overflow-imminent state after a period of time, and at this time, the value of the clock division counter is adjusted from CNT + a0 to CNT-a0 to ensure continuous output of audio. The time T from the overflow to the underflow of the FIFO _2 can be measured by circulating once;
when audio data starts to be transmitted, Fs, CNT and Fdp are fixed, and the arbitration logic circuit can obtain the time T from about overflow to about underflow of the FIFO _2 in the equipment 1 only through a timer or a counter;
step 2: substituting the T obtained in the step 1 into the following formula (1) to obtain the clock frequency offset Fq between the audio equipment 1 and the audio equipment 2;
then, a first current value of a clock adjustment parameter corresponding to the clock frequency offset Fq, including a value a and a value B, is obtained by inquiring in a pre-stored configuration table, and then the first current value is sent to a first audio interface, and the first audio interface adjusts the clock frequency according to the values a and B;
in the invention, the range of clock frequency adjustment is considered, so that the clock number B required to be adjusted in one clock frequency adjustment task is introduced;
the configuration table may be obtained by MATLAB modeling in advance, specifically, knowing the frequency offset Fq, an MATLAB model may be established according to formula (2), and the configuration table containing Fq, a, B, Fs/CNT generated by the MATLAB model is imported into the audio device 1;
and 3, step 3: no matter how to set the clock adjustment parameters a and B, the clocks of the first audio interface and the second audio interface in the audio device 1 cannot be adjusted to be in the same frequency and phase, and only two clock frequencies and phases can be infinitely close to each other, so FIFO _2 of the main data stream interface of the audio device 1 may overflow after a certain time, the embodiment of the present invention sends flags of FIFO _2, such as empty, full, underflow, 1/2 overflow (1/2 full ), and 1/2 underflow (1/2 empty ) to the arbitration logic circuit, when any of the above 6 flags is valid, the arbitration logic circuit will give the clock adjustment scheme of the first audio interface, that is, by reasonably setting the values a and B, the transmission delay of the first audio interface of the audio device 1 is minimized, and dynamic power consumption is minimal. It should be noted that, the more appropriate the values of a and B are set, the longer the interval time of clock adjustment is, and the better the effect is;
and 4, step 4: and (3) sending the updated a and B to a first audio interface of the audio device 1, and adjusting the clock of the first audio interface in real time, wherein when any flag bit in the step (3) is valid, the content in the step (4) is repeated.
In the long-time audio data interaction, the values of a and B are flexibly adjusted according to the above 6 flag bits.
For example, when the arbitration logic circuit receives 1/2empty flag bit of FIFO _2 in the audio device 1, it indicates that the clock frequency of the first audio interface is faster, and the values a and B need to be increased (e.g., a is increased by 2 and B is increased by 25% based on the first current value), and similarly, when the empty flag bit is received, the values a and B need to be increased continuously (e.g., a is increased by 25% and B is increased by 50% based on the above change); when the empty flag bit is received, the values of a and B need to be increased continuously (e.g., a is increased by 50% and B is increased by 75% based on the above change).
When the 1/2 full flag bit of FIFO _2 in the audio device 1 is received by the arbitration logic, it indicates that the clock of the first audio interface is slow, and the value of a needs to be decreased and the value of B needs to be increased (e.g. a is decreased by 2 and B is increased by 25% based on the first current value), and likewise, when the flag bit to be full is received, the value of a needs to be decreased and the value of B needs to be increased (e.g. a is decreased by 25% and B is increased by 50% based on the above change); when the full flag bit is received, the values of a and B need to be decreased continuously (e.g., a is decreased by 50% and B is increased by 75% based on the above change).
Wherein, the left and right channels of the audio can be configured separately.
The control method of the audio interface circuit provided by the invention can estimate the clock deviation between the audio interface of the master mode and the audio interface of the slave mode in the audio equipment within 10ms by inputting audio, according to the clock deviation, the arbitration logic circuit gives out the first current value of the clock adjusting parameter of the audio interface of the master mode by inquiring the configuration table, in the data interaction process, 6 flag bits of empty, full, overflow, underflow, 1/2 overflow and 1/2 underflow of the main data stream interface can also be sent into the arbitration logic circuit, once the flag bit is triggered, the arbitration logic circuit gives out a corresponding clock adjusting scheme by combining the first current value, thereby realizing the adjustment of the data stream interface rate, wherein the adjustment of the clock frequency is accompanied with the whole data interaction process, and through the simple and efficient frequency following mechanism, the audio noise caused by overflow or underflow of the audio data can be effectively avoided.
In the invention, the arbitration logic circuit in the audio interface circuit is a logic circuit, so that the control delay can be reduced, the response can be timely carried out, and the performance of the audio interface circuit can be improved.
The invention further provides an audio interface circuit, which includes an arbitration logic circuit, a first audio interface capable of operating in a master mode, and a second audio interface capable of operating in a slave mode, wherein the first audio interface is used for transmitting audio data received by the second audio interface, and the arbitration logic circuit can implement the control method.
Preferably, in an embodiment, the audio interface circuit further includes a buffer circuit, and the buffer circuit is used as a buffer for the first audio interface and the second audio interface, that is, the buffer circuit is shared by the first audio interface and the second audio interface, which is beneficial to simplifying the circuit.
Preferably, in an embodiment, the buffer circuit is a FIFO memory circuit, wherein the arbitration logic circuit may configure the FIFO memory circuit to divide the buffer of the first audio interface and the buffer of the second audio interface.
The cache circuit comprises cache control logic and a cache space, and the cache space can be a piece of RAM.
For example, the first audio interface may be an I2S interface, a USB interface, or an SPDIF interface, and the second audio interface may be an I2S interface, a USB interface, or an SPDIF interface.
The invention also provides audio equipment comprising the audio interface circuit.
For example, the audio device may be a sound card, a PC, a mobile phone, a tablet computer, or a sound box.
In the audio device, the second audio interface working in the slave mode receives audio data sent by another audio device, and the audio data is processed and then sent out through the first audio interface working in the master mode.
The audio data received by the second audio interface may be a stored voice file, or audio data such as recording, accompaniment or background music sent by other interfaces, and after being processed by reverberation or sound change, the processed data is sent to an earphone, a power amplifier or other monitoring devices through the first audio interface.
It will be appreciated by those skilled in the art that the above-described preferred embodiments may be freely combined, superimposed, without conflict.
It will be understood that the embodiments described above are illustrative only and not restrictive, and that various obvious and equivalent modifications and substitutions for details described herein may be made by those skilled in the art without departing from the basic principles of the invention.
Claims (10)
1. A method for controlling an audio interface circuit, the audio interface circuit comprising an arbitration logic circuit, a first audio interface, and a second audio interface, the first audio interface for transmitting audio data received by the second audio interface, the method comprising:
step S100: the arbitration logic measures a clock frequency offset between the second audio interface operating in a slave mode and the first audio interface operating in a master mode;
step S200: the arbitration logic circuit obtains a first current value of a clock adjustment parameter in prestored information according to the clock frequency offset, and then sends a clock adjustment trigger signal to the first audio interface, so that the first audio interface starts to execute a clock frequency adjustment task once according to the first current value, the clock adjustment parameter comprises the number of clocks needing to be adjusted in a single clock frequency adjustment task and an adjustment quantity for adjusting an initial value of a clock frequency division counter of the first audio interface, the prestored information is a configuration table, and the configuration table comprises corresponding relations between different clock frequency offsets and different first current values of the clock adjustment parameter;
step S300: the arbitration logic circuit detects a cache state of the first audio interface, if a first cache flag event that a cache change trend is reduced is detected, the step S400 is executed, and if a second cache flag event that the cache change trend is increased is detected, the step S500 is executed;
step S400: the arbitration logic circuit increases the adjustment amount in the first current value and increases the clock number in the first current value to obtain a second current value of the clock adjustment parameter, and then sends a clock adjustment trigger signal to the first audio interface to enable the first audio interface to start executing a clock frequency adjustment task once according to the second current value;
step S500: and the arbitration logic circuit reduces the adjustment amount in the first current value and increases the clock number in the first current value to obtain a third current value of the clock adjustment parameter, and then sends a clock adjustment trigger signal to the first audio interface to enable the first audio interface to start executing a clock frequency adjustment task once according to the third current value.
2. The method of claim 1, wherein the first cache flag event is an 1/2empty flag event, and wherein the second cache flag event is a 1/2 full flag event.
3. The method according to claim 1, wherein the step S400 further comprises: the arbitration logic circuit detects a cache state of the first audio interface, if the arbitration logic circuit detects a third cache flag event, the arbitration logic circuit increases the adjustment amount in the second current value and increases the clock number in the second current value to obtain a fourth current value of a clock adjustment parameter, and then sends a clock adjustment trigger signal to the first audio interface to enable the first audio interface to start executing a clock frequency adjustment task once according to the fourth current value, wherein the third cache flag event is a null flag event or a null flag event;
the step S500 further includes: the arbitration logic circuit detects a cache state of the first audio interface, and if the arbitration logic circuit detects a fourth cache flag event, the arbitration logic circuit decreases the adjustment amount in the third current value and increases the clock number in the third current value to obtain a fifth current value of a clock adjustment parameter, and then sends a clock adjustment trigger signal to the first audio interface, so that the first audio interface starts to execute a clock frequency adjustment task once according to the fifth current value, and the fourth cache flag event is a full flag event or a full flag event.
4. The method according to any of claims 1-3, wherein in step S100, the arbitration logic measures the clock frequency offset between the second audio interface and the first audio interface by:
when the audio data received by the second audio interface is sent out by the first audio interface, the arbitration logic circuit detects the cache state of the first audio interface, and if an empty flag event is detected, the value of a clock frequency division counter of the first audio interface is controlled to be equal to
If the full flag event is detected, controlling the value of a clock division counter of the first audio interface to be
And measuring the time from the buffer status of the first audio interface to being full to empty
Wherein,
is a preset value and is positive;
the arbitration logic calculates a clock frequency offset between the second audio interface and the first audio interface;
wherein,
is a clock frequency offset between the second audio interface and the first audio interface,
is a value of a buffer depth of the first audio interface,
in order to be the system clock frequency,
and the initial preset value of the clock frequency division counter of the first audio interface is obtained.
5. An audio interface circuit, comprising arbitration logic, a first audio interface operable in a master mode and a second audio interface operable in a slave mode, the first audio interface being configured to transmit audio data received by the second audio interface, the arbitration logic being configured to implement the control method of any of claims 1-4.
6. The audio interface circuit of claim 5, further comprising a buffer circuit that acts as a buffer for the first audio interface and the second audio interface.
7. The audio interface circuit of claim 6, wherein the buffer space of the buffer circuit is a piece of RAM.
8. The audio interface circuit of claim 5, wherein the first audio interface is one of an I2S interface, a USB interface, and an SPDIF interface, and wherein the second audio interface is one of an I2S interface, a USB interface, and an SPDIF interface.
9. Audio device, characterized in that it comprises an audio interface circuit according to any of claims 5-8.
10. The audio device of claim 9, wherein the audio device is a sound card, a PC, a cell phone, a tablet, or a speaker.
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