CN112542442B - A low-cost multi-chip high-speed and high-bandwidth interconnect structure - Google Patents
A low-cost multi-chip high-speed and high-bandwidth interconnect structure Download PDFInfo
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- CN112542442B CN112542442B CN202011563925.9A CN202011563925A CN112542442B CN 112542442 B CN112542442 B CN 112542442B CN 202011563925 A CN202011563925 A CN 202011563925A CN 112542442 B CN112542442 B CN 112542442B
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- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000013473 artificial intelligence Methods 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000000919 ceramic Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 230000006870 function Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- WGQOUDPBYNQAPB-OQSMONGASA-N [(1r,5s)-8-methyl-8-azabicyclo[3.2.1]octan-3-yl] 2-phenyl-3-propanoyloxypropanoate Chemical compound C([C@H]1CC[C@H](N1C)C1)C1OC(=O)C(COC(=O)CC)C1=CC=CC=C1 WGQOUDPBYNQAPB-OQSMONGASA-N 0.000 claims 1
- 238000005476 soldering Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000003466 welding Methods 0.000 abstract description 2
- 230000010354 integration Effects 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 10
- 238000004088 simulation Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 7
- 238000004364 calculation method Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000005672 electromagnetic field Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010353 genetic engineering Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010801 machine learning Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000012549 training Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for individual devices of subclass H10D
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
本发明公开了一种低成本多芯片高速高带宽互连结构，包括：复数个有源芯片、互连基板以及倒装互连凸点；所述互连基板用以实现各个有源芯片之间的金属互连和机械支撑；所述各个有源芯片之间通过超高速接口实现数据交换，共同承担人工智能算力；有源芯片通过所述倒装互连凸点与互连基板以倒装焊的方式连接。本发明不仅可以大幅提升人工智能系统的算力，还能极大地降低人工智能系统的制作成本。
The present invention discloses a low-cost multi-chip high-speed high-bandwidth interconnection structure, comprising: a plurality of active chips, an interconnection substrate and a flip-chip interconnection bump; the interconnection substrate is used to realize metal interconnection and mechanical support between each active chip; the active chips realize data exchange through an ultra-high-speed interface and jointly bear artificial intelligence computing power; the active chips are connected to the interconnection substrate in a flip-chip welding manner through the flip-chip interconnection bump. The present invention can not only greatly improve the computing power of the artificial intelligence system, but also greatly reduce the production cost of the artificial intelligence system.
Description
Technical Field
The invention discloses a low-cost multi-chip high-speed high-bandwidth interconnection structure, and relates to the technical field of system-level integration of artificial intelligent modules.
Background
Artificial intelligence (ARTIFICIAL INTELLIGENCE), abbreviated AI, is a scientific technology for studying and developing theory, methods, techniques and applications for simulating, extending and expanding human intelligence. With the continuous development of artificial intelligence technology in the fields of machine learning, high-performance computing, image recognition, genetic engineering and the like, the amount of data required to be processed by the artificial intelligence technology is increasing in a burst manner. In certain AI training applications, the bandwidth requirements of a single SoC may exceed a few TBs/s. Conventional chip and system integration methods have failed to meet the needs of artificial intelligence technology. At present, the technology of the silicon-based adapter board (Silicon Interposer) is a traditional technology of artificial intelligence system integration, and compared with known products, namely Tesla A100 of NVIDIA, radeon VII, google chip TPU3.0 and the like.
TW201826403A Methods of forming cowos structures discloses a method for producing a cumulative power COWOS (Chip on Wafer on Substrate). In order to improve the integration level, the SOC and HBM (High Bandwidth Memory) are integrated by adopting a silicon-based adapter plate to form a high-bandwidth computing module. However, silicon-based interposer technology is difficult and costly to manufacture. Also, this integration approach is theoretically limited in its upper limit, which is limited by the data processing capabilities of a single SOC.
The traditional artificial intelligence system integration technology is too dependent on the development of moore's law, designs a super chip with strong computing power by continuously improving the integration level of transistors of a single chip, selects a high-cost silicon-based adapter plate technology, and performs traditional packaging after being integrated with an HBM. However, as moore's law goes to end, the size of the transistor gets closer to the limit and the corresponding fabrication costs get higher. In addition, silicon-based interposer is not naturally suitable for large area integration due to the material properties of silicon.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a low-cost multi-chip high-speed high-bandwidth interconnection structure.
The invention adopts the following technical scheme for solving the technical problems:
the low-cost multi-chip high-speed high-bandwidth interconnection structure comprises a plurality of active chips, an interconnection substrate and flip-chip interconnection bumps, wherein the interconnection substrate is used for realizing metal interconnection and mechanical support among the active chips, the active chips are used for realizing data exchange through an ultra-high-speed interface and jointly bearing artificial intelligence calculation force, and the active chips are connected with the interconnection substrate in a flip-chip welding mode through the flip-chip interconnection bumps.
The plurality of active chips are used for bearing the calculation force of the artificial intelligence system. If the calculation requirement of the system exceeds the data transmission quantity and calculation force of a single active chip, all the active chips can simultaneously acquire external transmission data, and all the active chips realize data exchange through an ultra-high speed interface and jointly bear artificial intelligence calculation force. The main advantage of the parallel computing is that the parallel computing using a plurality of identical active chips is creatively proposed, so that the computational power requirement of a single chip can be reduced, and the design and manufacturing cost of the chip are greatly reduced.
As a preferred scheme, the structures and functions of the active chips are identical, and the active chips are separate small systems which can be independently interconnected with external data or can be integrated according to an array. The number of integrated chips can be flexibly designed according to the calculation force requirement of the system. Different from different system integration of different chips, the array type integration mode greatly reduces the integration difficulty.
Preferably, the ultra-high speed interface for interconnecting the active chips comprises NRZ, PAM4, PAM8 and other high speed interconnection interfaces. The high-speed interface rate of a single channel which is commercially used at present can reach 112Gbps, and the high-speed high-bandwidth interconnection requirement can be met.
The metal interconnection comprises a horizontal interconnection and a vertical interconnection, wherein the horizontal interconnection is mainly provided by a metal wire, the metal interconnection can be manufactured by an exposure and etching method, and the vertical interconnection is manufactured by a laser blind buried hole or mechanical through hole method.
In particular embodiments, the choices available for the flip-chip interconnect bumps include C4 bumps, copper bumps, or other metal bumps.
Preferably, the flip-chip interconnection bumps are provided with a specific bump arrangement mode, wherein each pair of differential signal bumps are not adjacent, and the middle of each pair of differential signal bumps are separated by a pair of ground bumps. The specific bump array can greatly reduce crosstalk between different channels while not affecting the single channel interconnect performance.
Compared with the prior art, the technical scheme has the following technical effects that the multi-chip is integrated by utilizing the low-cost substrate technology, so that the parallel computation of the multi-chip is realized, and the computation power of the artificial intelligent system is greatly improved. So that the improvement of the system performance is not solely dependent on the improvement of the computing power of a single SOC. Under the condition of the same calculation power, compared with a single SOC chip architecture, the unique multi-chip parallel architecture can greatly reduce the design difficulty and the production cost.
Drawings
FIG. 1 is a cross-sectional view of a package structure in one embodiment of the invention;
FIG. 2 is a top view of a package structure including a plurality of active chips and their interconnections in accordance with one embodiment of the present invention;
FIG. 3 illustrates a single active die and bump arrangement in accordance with an embodiment of the present invention;
FIG. 4 is a graph of simulation results using a three-dimensional full wave electromagnetic field simulation tool in accordance with the present invention;
FIG. 5 is a diagram showing the results of an eye simulation at the receiving end in accordance with the present invention;
the semiconductor device comprises 101-active chips, 102-flip-chip interconnection bumps of the chips, 103-metal interconnection between the active chips, 104-substrate vertical electric interconnection, 105-substrate horizontal electric interconnection, 106-solder balls, 201-signal bumps and 202-power supply bumps.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
The technical scheme of the invention is further described in detail below with reference to the accompanying drawings:
Referring to fig. 1-2, the present invention describes in detail a low-cost multi-chip high-speed high-bandwidth interconnection structure suitable for artificial intelligence system integration, which comprises a plurality of active chips, a low-cost interconnection substrate and flip-chip interconnection bumps, wherein the schematic structure is shown in fig. 1, and the top view is shown in fig. 2. The plurality of active chips 101 are each mounted on a low cost interconnect substrate for providing metal interconnection and mechanical support between the individual active chips 101. The low-cost interconnection substrate comprises an organic medium substrate or a low-temperature co-fired ceramic substrate or a high-temperature co-fired ceramic substrate. The metal interconnections 103 between the active chips may be implemented on an interconnection substrate, including a substrate horizontal electrical interconnection 105 in a horizontal direction and a substrate vertical electrical interconnection 104 in a vertical direction. And data exchange is realized among the active chips through an ultra-high speed interface, wherein the ultra-high speed interface comprises NRZ, PAM4, PAM8 and other high-speed interconnection interfaces. The flip-chip interconnect bumps 102 of the chip include C4 bumps, copper bumps, or other metal bumps through which the active chip is connected to the interconnect substrate. The flip-chip interconnect bumps should have a specific arrangement, as shown in fig. 2, where each pair of differential signal bumps are not adjacent, and are separated by a pair of ground bumps. The specific bump array can greatly reduce crosstalk between different channels while not affecting the single channel interconnect performance. The single active chip and its bump arrangement are shown in fig. 3, where signal bumps 201 are spaced apart from power bumps 202.
The invention adopts the three-dimensional full-wave electromagnetic field simulation tool to model the passive interconnection structure, and can accurately compare the transmission characteristics of different structures based on the traditional bump arrangement and the specific bump arrangement. According to the simulation result shown in fig. 4, in the passive structure corresponding to the specific bump array, the crosstalk between different channels is only below-40 dB at the nyquist frequency of 2 times, which is far better than the isolation of-30 dB based on the conventional bump array. Simulation results demonstrate that a particular bump arrangement facilitates interconnection between active chips.
The invention utilizes a time domain eye diagram simulation tool ADS to cascade a chip active model IBIS AMI model and S parameter models of all passive channels, and simulates an eye diagram result at a receiving end. According to the simulation result shown in fig. 5, when the transmission speed of a single channel is 112Gbps (only one differential pair of transmission data, and when the channel contains multiple differential pairs, the channel transmission data is multiplied), the eye diagram of the receiving end is still clearly open, which proves the possibility of high-speed and high-bandwidth transmission between active chips.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention. The present invention is not limited to the preferred embodiments, and the present invention is described above in any way, but is not limited to the preferred embodiments, and any person skilled in the art will appreciate that the present invention is not limited to the embodiments described above, while the invention has been described with respect to specific examples including presently preferred modes of carrying out the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described embodiments that fall within the spirit and scope of the invention as set forth in the appended claims.
Claims (4)
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| CN202011563925.9A CN112542442B (en) | 2020-12-25 | 2020-12-25 | A low-cost multi-chip high-speed and high-bandwidth interconnect structure |
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| CN202011563925.9A CN112542442B (en) | 2020-12-25 | 2020-12-25 | A low-cost multi-chip high-speed and high-bandwidth interconnect structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101047160A (en) * | 2006-03-29 | 2007-10-03 | 台湾积体电路制造股份有限公司 | Semiconductor wiring packaging structure and connection method with integrated circuit |
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| JPH10173002A (en) * | 1996-12-06 | 1998-06-26 | Toshiba Corp | Bare chip flip chip bonding method |
| US7342310B2 (en) * | 2004-05-07 | 2008-03-11 | Avago Technologies General Ip Pte Ltd | Multi-chip package with high-speed serial communications between semiconductor die |
| JP2012033786A (en) * | 2010-07-31 | 2012-02-16 | Kyocer Slc Technologies Corp | Wiring board |
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| CN101047160A (en) * | 2006-03-29 | 2007-10-03 | 台湾积体电路制造股份有限公司 | Semiconductor wiring packaging structure and connection method with integrated circuit |
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