CN112563132B - Rapid thinning and polishing method for surface heterostructure - Google Patents
Rapid thinning and polishing method for surface heterostructure Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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Abstract
The invention provides a rapid thinning polishing method of a surface heterostructure, which utilizes chemical reagents to change the surface state and property of a metal material in the thinning polishing process, reduces the grinding force required by separation of the metal material, and controls the removal rate of the metal and photoresist to be at the same level. The process method abandons pure mechanical grinding of the cast iron disc, avoids the stretching deformation of the metal structure caused by pure physical grinding, effectively controls the figure size precision and the plane flatness, and ensures that the thinning and polishing rate can reach 2-3 mu m/min.
Description
Technical Field
The invention relates to the field of substrate polishing, in particular to a rapid thinning polishing method of a surface heterostructure.
Background
With the rapid development of the semiconductor technology field, semiconductor devices have become more complex. In order to improve the integration level and reduce the manufacturing cost, the size of the components is lower and lower, the number of the original components in the unit area of the chip is larger and larger, and the in-plane wiring cannot meet the distribution requirement of the components with high density, so that only a multilayer wiring structure can be adopted. And when the metal layer is excessively stacked on the wafer substrate, the surface relief of the chip is more obvious. The most intuitive negative effect of the surface relief is that a smooth photoresist film is difficult to obtain in the photoresist homogenizing process of the subsequent photoetching process, so that the size of a photoetching pattern is difficult to accurately control by adjusting the exposure amount in the exposure and development process, and the deviation of the size is fatal to the performance influence of a semiconductor device.
The planarization process of semiconductor wafer is to grind homogeneous or heterogeneous material on the surface of wafer substrate to eliminate material of certain sacrificial thickness, and to planarize the surface in chemical polishing mode to raise the homogeneity of homogeneous or heterogeneous material. If the material of the wafer surface is single, the sacrificial thickness material can be removed rapidly and efficiently by adopting a mechanical grinding method, the thickness difference is controlled in a small range, and then the surface height is flattened by adopting a chemical mechanical polishing method, so that the roughness is reduced. However, devices in the semiconductor processing industry often are combined patterns of various materials on the surface, the hardness and toughness of the materials are greatly different, and the mechanical polishing method can lead to inconsistent removal rate of the surface materials, so that a more protruding structure in the further polishing process can cause stretching deformation in the polishing hard contact process, and therefore, the polishing rate needs to be reduced to control the accuracy of the patterns.
The existing rapid thinning polishing method for the surface heterostructure can effectively solve the problem that the combined patterns of various materials on the surface have large differences in hardness and toughness, the removal rate of the surface materials is inconsistent due to the adoption of a mechanical polishing method, and the problem that a more prominent structure in the further polishing process can cause stretching deformation in the polishing hard contact process is solved.
Disclosure of Invention
The invention provides a rapid thinning polishing method for a surface heterostructure, which aims to solve the problems that in the prior art, the cutting rates of different materials are different in the flattening process due to different hardness and toughness of heterogeneous materials, so that the thickness difference of a surface heterogeneous pattern is larger after the flattening process, and the performance of a metal structure device is influenced due to the tensile deformation or damage of soft metal in the thinning process of a pure mechanical mill.
The invention provides a rapid thinning polishing method of a surface heterostructure, which comprises the following steps of:
s1, measuring the thickness of a heterogeneous pattern on the surface of a wafer to be processed of a substrate by using a thickness gauge, and recording the height of the highest pattern of the heterogeneous pattern and the mode range height in the heterogeneous pattern;
s2, installing a polyurethane disc on a wafer thinning machine, and chemically thinning and mechanically thinning a matrix through the polyurethane disc;
S3, measuring the height of the highest pattern and the height of the mode range in the surface heterogeneous pattern of the substrate subjected to primary chemical thinning and mechanical thinning by adopting a thickness gauge, and if the thickness difference exceeds a thinning preset value, performing step S2; if the measured thickness difference meets the requirement of the thinning preset value, performing step S4;
S4, removing the polyurethane disc on the wafer thinning machine, installing a soft flannelette disc for polishing on the wafer thinning machine, and chemically polishing and mechanically polishing the substrate by using the soft polishing flannelette disc for polishing;
S5, measuring the thickness of the surface heterogeneous patterns on the upper surface of the semiconductor substrate subjected to the mechanochemical polishing by adopting a thickness gauge, and repeating the step S4 if the thickness difference value of the surface heterogeneous patterns exceeds a polishing preset value; if the measured thickness difference and the overall height of the surface heterogeneous pattern meet the polishing preset value requirement, performing step S6;
s6, finishing the thinning and polishing of the substrate.
After chemical mechanical thinning, the thickness difference between the highest pattern and the mode range pattern on the surface of the semiconductor substrate should be controlled within 30 μm. In the step S4, after chemical mechanical polishing, the thickness difference between the highest pattern and the pattern in the height mode range on the surface of the semiconductor substrate is controlled within 3 mu m, and the thickness difference between the adjacent heterogeneous patterns on the surface of the semiconductor substrate is controlled within 1 mu m;
according to the rapid thinning polishing method of the surface heterostructure, as an optimal mode, a substrate comprises a surface heterostructure and a semiconductor substrate, and the surface heterostructure is arranged on the upper surface of the semiconductor substrate; the surface heterogeneous pattern comprises surface photoresist and surface metal, wherein the surface photoresist is a columnar structure which is perpendicular to the semiconductor substrate, the upper surface of the semiconductor substrate is fully distributed by the surface photoresist, and gaps among the surface metals are filled.
The surface metal material and the surface photoresist material have thickness difference, the surface metal is a plurality of columns and cuboids which are distributed by sector antennas, distributed in a honeycomb shape and distributed randomly and are perpendicular to the substrate, and gaps between adjacent metal materials are all made of the surface photoresist material.
According to the rapid thinning polishing method for the surface heterostructure, in the step S3, a preset thinning value is 0-30 mu m as an optimal mode.
According to the rapid thinning polishing method for the surface heterostructure, as an optimal mode, the chemical thinning and mechanical thinning, and chemical polishing and mechanical polishing removal rates are the same.
According to the rapid thinning polishing method for the surface heterostructure, in the step S4, as an optimal mode, the surface roughness of the surface heterostructure pattern after chemical polishing and mechanical polishing is smaller than 1nm.
According to the rapid thinning polishing method for the surface heterostructure, in the step S5, a polishing preset value is 0-1 mu m as a preferable mode.
According to the rapid thinning polishing method for the surface heterostructure, in the preferred mode, the polishing process in the step S4 is adopted, and the stretching rate of the surface metal structure pattern in the length direction is controlled within 3%.
According to the rapid thinning polishing method for the surface heterostructure, as an optimal mode, polishing liquid used for chemical thinning and chemical polishing is a chemical reagent capable of selectively corroding metal.
Aiming at the thinning and polishing process of the heterogeneous patterns on the semiconductor surface, the process method for quickly thinning and flattening the heterogeneous pattern structure on the semiconductor surface is provided, and the method is suitable for the combination of the non-single material of the surface pattern, particularly the soft metal and the photoresist material. In the thinning and polishing process of the process method, the surface state and the property of the metal material are changed by using chemical reagents, the grinding force required by the separation is reduced, and the removal rates of the metal and the photoresist are controlled at the same level. The process method abandons pure mechanical grinding of the cast iron disc, avoids the stretching deformation of the metal structure caused by pure physical grinding, effectively controls the figure size precision and the plane flatness, and ensures that the thinning and polishing rate can reach 2-3 mu m/min.
The invention has the following beneficial effects:
The adopted combined processing method of chemical mechanical thinning and chemical mechanical polishing utilizes the chemical mechanical thinning to carry out primary flattening treatment on the heterogeneous pattern surface of the wafer, quickly removes metal patterns with larger surface thickness difference, controls the thickness difference of the whole pattern on the surface within a certain range, and avoids the phenomenon that the substrate is scratched, and the pattern structure is damaged due to the pause and the contusion when polishing on a soft flannelette disc. And polishing is performed by a physical and chemical combination mode, so that the material removal rate is greatly increased, and the transverse stretching deformation of the graph caused by grinding and hard contact grinding of the cast iron disc is avoided. Meanwhile, as the hardness and density differences of the surface photoresist material and the metal material are large, when a cast iron disc is adopted for hard contact cutting, the cutting speeds of the surface photoresist material and the metal material are different, the final thickness difference depends on the particle size of grinding fluid, a physicochemical combined removal mode on a soft flannelette disc is adopted, the removal rate of the metal material and the photoresist material can be adjusted by changing the proportion of hydrogen peroxide, the thickness difference of each pattern on the surface of the finally obtained wafer substrate is within 1 mu m, the roughness (Ra) of the surface metal material is within 1nm, the surface flatness is within 3 mu m, the thinning rate can be up to 2-3 mu m/min, and the deformation stretching rate in the pattern length direction is controlled within 3%.
Drawings
FIG. 1 is a flow chart of a method for rapid thinning polishing of a surface heterostructure;
FIG. 2 is a schematic diagram of a rapid thinning polishing method of a surface heterostructure;
fig. 3 is a rapid thinning polishing method of a surface heterostructure.
Reference numerals:
1. A surface heterogeneous pattern; 11. a surface photoresist; 12. surface metal; 2. a semiconductor substrate.
Detailed Description
The following description of the embodiments of the present invention will be made more complete in view of the accompanying drawings, in which it is to be understood that the embodiments described are merely some, but not all embodiments of the invention.
Example 1
As shown in fig. 1, a method for rapidly thinning and polishing a surface heterostructure includes the following steps:
S1, turning on a vacuum pump, placing a semiconductor substrate to be processed on a special suction piece tool, vacuumizing and adsorbing, measuring photoresist material patterns and metal material patterns in heterogeneous patterns on the surface of the semiconductor substrate by adopting a contact thickness gauge, and recording the highest value and the mode range value of the height in all patterns;
S2, chemical mechanical thinning, opening a wafer thinning machine, selecting a polyurethane disc according to the material characteristics of the heterogeneous pattern surface, and installing a swing arm. Preparing a 3 mu m cerium oxide suspension and water into grinding liquid according to a certain proportion, and adjusting the drop speed of the guide cylinder to 40-60 drops/min. Preparing a chemical etching solution from the nano silicon oxide suspension, hydrogen peroxide and water according to a certain proportion, adjusting the dripping speed to 60-100 drops/min, fixing the semiconductor substrate to be treated on a grinding tool in a vacuum adsorption mode, and inverting the semiconductor substrate to be treated above the flannelette disc. The rotational speed of the polyurethane disk is adjusted to 20-50 r/min, the substrate is ground for 5-10 min, and the difference between the mode range height of the surface of the substrate and the thickness of the highest pattern is controlled within a required range through chemical mechanical thinning. Washing with deionized water after finishing grinding, wiping with dust-free cloth in the washing process, and finally purging with nitrogen;
S3, measuring the height of the highest pattern and the height of the mode range in the surface heterogeneous pattern 1 of the substrate subjected to primary chemical thinning and mechanical thinning by adopting a thickness gauge, and if the thickness difference exceeds a thinning preset value, performing a step S2; if the measured thickness difference meets the requirement of the thinning preset value, performing step S4;
s4, detaching the polyurethane disc for chemical mechanical thinning, replacing the polyurethane disc with the soft flannelette disc for polishing, and fixing the swing arm. According to the silicon oxide polishing solution: hydrogen peroxide: water=20 (1-5), wherein the ratio of 80 is configured to be mixed with polishing solution, the dripping speed is adjusted to 60-120 drops/min, the cerium oxide grinding liquid configured in the step S2 is opened, the dripping speed is adjusted to 40-60 drops/min, and the cerium oxide grinding liquid are jointly dripped on a soft flannelette disc. The substrate is fixed on a fixture and is inversely arranged on a flannelette disc, a counterweight of 3-5 kg is fixed above the fixture, the rotating speed of the flannelette disc is adjusted to 60-100 revolutions per minute, and the substrate is polished for 10-15 minutes. Closing a cerium oxide grinding fluid guide pipe, adjusting a counterweight on a fixed tool to 5-8 kg, and polishing a substrate for 10-30 min;
s5, measuring the thickness of the surface heterogeneous pattern 1 on the upper surface of the semiconductor substrate 2 subjected to mechanochemical polishing by adopting a thickness gauge, if the thickness difference value of the surface heterogeneous pattern 1 exceeds a polishing preset value, shutting down the polishing step after the cerium oxide suspension guide cylinder, reducing the counterweight, and repeating the step S4; if the measured thickness difference and the overall height of the surface heterogeneous pattern 1 meet the polishing preset value requirement, performing step S6;
S6, measuring the substrate which meets the requirements of the overall height and the thickness difference of the heterogeneous patterns in the step S5 by using a probe type step analyzer, wherein the thickness difference of the heterogeneous patterns is smaller than 1 mu m, the overall thickness difference is controlled within 3 mu m, and the surface roughness of a single material is smaller than 1nm.
Optionally, before step S2, the substrate to be processed is placed on a dedicated grinding tool, and vacuum adsorption is adopted. And (3) installing a polyurethane disc on the wafer thinning machine, installing a swing arm, adopting cerium oxide suspension with the particle size of 3 mu m as grinding liquid, adopting mixed solution of nano-scale silicon oxide suspension, hydrogen peroxide and water as chemical etching liquid, wherein the drop speed of the cerium oxide suspension is 40-60 drops/min, the drop speed of the chemical etching liquid is 60-120 drops/min, the grinding rotating speed is 20-50 revolutions/min, and controlling the mode range height of the surface of the substrate and the thickness difference value of the highest graph within a required range. After finishing the grinding, the grinding is washed by deionized water, and is wiped by dust-free cloth in the washing process, and finally, the grinding is purged by nitrogen.
Further, the chemical etching solution in the step S2 is a silicon oxide suspension: hydrogen peroxide: water=20 (6 to 10): 80.
Further, before step S4, the polyurethane disc of the wafer thinning machine is replaced, a soft flannelette disc is installed, and a swing arm is installed. The chemical mechanical polishing process is divided into two parts: primary chemical mechanical polishing and secondary chemical mechanical polishing.
Further, the primary chemical mechanical polishing and the secondary chemical mechanical polishing are carried out by the following specific processes:
The primary chemical mechanical polishing is carried out, the polishing liquid is cerium oxide suspension with the particle size of 3 mu m and mixed solution of nano-scale silicon oxide suspension, hydrogen peroxide and water, the polishing rotating speed is 60-100 revolutions per minute, the counter weight is 3-5kg, the liquid drop speed of the cerium oxide suspension is 40-60 drops per minute, the mixed polishing liquid of silicon oxide is 60-120 drops per minute, and the polishing time is 10-15 minutes.
And (3) performing secondary chemical mechanical polishing, wherein the polishing solution is a mixed solution of nano-scale silicon oxide suspension, hydrogen peroxide and water, and stopping the cerium oxide suspension liquid drop material when performing secondary chemical mechanical polishing, wherein the polishing rotating speed is 60-100 revolutions per minute, the adding counterweight is 5-8 kg, and the polishing time is 10-30 minutes.
Optionally, the polishing solution in the step S4 is a silicon oxide suspension: hydrogen peroxide: water=20 (1 to 5): 80.
As shown in fig. 2, the base body includes a surface hetero pattern 1 and a semiconductor substrate 2, the surface hetero pattern 1 being provided on the upper surface of the semiconductor substrate 2.
As shown in fig. 3, the surface hetero pattern 1 includes a surface photoresist 11 and a surface metal 12, the surface metal 12 is a plurality of columnar structures perpendicular to the semiconductor substrate 2, and the surface photoresist 11 fills the upper surface of the semiconductor substrate 2 and fills the gaps between the surface metals 12.
And placing the semiconductor substrate to be processed on a special thickness measuring tool, and fixing the semiconductor substrate by adopting a vacuum adsorption mode.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art, who is within the scope of the present invention, should make equivalent substitutions or modifications according to the technical scheme of the present invention and the inventive concept thereof, and should be covered by the scope of the present invention.
Claims (8)
1. A rapid thinning and polishing method for a surface heterostructure is characterized by comprising the following steps of: the method comprises the following steps:
s1, measuring the thickness of a wafer surface heterogeneous pattern (1) to be processed of a substrate by using a thickness gauge, and recording the height of the highest pattern of the surface heterogeneous pattern (1) and the mode range height in the surface heterogeneous pattern (1);
s2, installing a polyurethane disc on a wafer thinning machine, and chemically thinning and mechanically thinning the substrate through the polyurethane disc;
Opening a wafer thinning machine, selecting a polyurethane disc according to the material characteristics of the surface heterogeneous patterns (1), and installing a swing arm; preparing a 3 mu m cerium oxide suspension and water into a grinding liquid, and adjusting the dropping speed of a guide cylinder to 40-60 drops/min; preparing a nano silicon oxide suspension, hydrogen peroxide and water into chemical corrosive liquid according to the proportion of 20 (6-10), wherein the dripping speed is adjusted to 60-100 drops/min, and the semiconductor substrate (2) to be treated is fixed on a grinding tool in a vacuum adsorption mode and is inverted above a flannelette disc; adjusting the rotating speed of the polyurethane disc to 20-50 r/min, grinding the semiconductor substrate (2) for 5-10 min, and controlling the mode range height of the surface heterogeneous pattern (1) and the thickness difference value of the highest pattern within a required range through chemical thinning and mechanical thinning; washing with deionized water after finishing grinding, wiping with dust-free cloth in the washing process, and finally purging with nitrogen;
S3, measuring the highest pattern height and mode range height of the surface heterogeneous pattern (1) of the substrate subjected to the chemical thinning and the mechanical thinning by adopting the thickness gauge, and if the thickness difference exceeds a thinning preset value, performing a step S2; if the measured thickness difference meets the requirement of the thinning preset value, performing step S4;
S4, dismantling the polyurethane disc on the wafer thinning machine, installing a soft flannelette disc for polishing on the wafer thinning machine, fixing a swing arm, and carrying out chemical mechanical polishing on the substrate by using the soft polishing flannelette disc for polishing, wherein the chemical mechanical polishing process is divided into two parts: primary chemical mechanical polishing and secondary chemical mechanical polishing;
And (3) performing chemical mechanical polishing once according to a silicon oxide polishing solution: hydrogen peroxide: water=20 (1-5), wherein the proportion of 80 is configured into mixed polishing solution, the dripping speed is adjusted to 60-120 drops/min, the cerium oxide grinding liquid prepared in the step S2 is opened, the dripping speed is adjusted to 40-60 drops/min, and the cerium oxide grinding liquid are jointly dripped on a soft flannelette disc; fixing the semiconductor substrate (2) on a fixture, inversely arranging the fixture on a flannelette disc, fixing 3-5 kg of counterweight above the fixture, adjusting the rotating speed of the flannelette disc to 60-100 rpm, and polishing the semiconductor substrate (2) for 10-15 min;
Closing a cerium oxide grinding fluid guide pipe, adjusting a counterweight on a fixed tool to 5-8 kg, and polishing a substrate for 10-30 min;
S5, measuring the thickness of the surface heterogeneous patterns (1) on the upper surface of the semiconductor substrate (2) subjected to mechanical chemical polishing by adopting the thickness gauge, and repeating the step S4 if the thickness difference value of the surface heterogeneous patterns (1) exceeds a polishing preset value; if the measured thickness difference and the overall height of the surface heterogeneous pattern (1) meet the polishing preset value requirement, performing step S6;
s6, finishing the thinning and polishing of the substrate.
2. The method for rapid thinning and polishing of a surface heterostructure according to claim 1, wherein: the substrate comprises a surface heterogeneous pattern (1) and a semiconductor substrate (2), wherein the surface heterogeneous pattern (1) is arranged on the upper surface of the semiconductor substrate (2); the surface heterogeneous pattern (1) comprises surface photoresist (11) and surface metal (12), wherein the surface metal (12) is of a plurality of columnar structures perpendicular to the semiconductor substrate (2), and the surface photoresist (11) is used for fully distributing the upper surface of the semiconductor substrate (2) and filling gaps among the surface metal (12).
3. The method for rapid thinning and polishing of a surface heterostructure according to claim 1, wherein: in the step S3, the thinning preset value is 0-30 μm.
4. The method for rapid thinning and polishing of a surface heterostructure according to claim 1, wherein: the chemical thinning and the mechanical thinning have the same chemical mechanical polishing removal rate.
5. The method for rapid thinning and polishing of a surface heterostructure according to claim 1, wherein: the surface roughness of the surface hetero pattern (1) after the chemical mechanical polishing in the step S4 is less than 1nm.
6. The method for rapid thinning and polishing of a surface heterostructure according to claim 1, wherein: and in the step S5, the polishing preset value is 0-1 mu m.
7. The rapid thinning polishing method of a surface heterostructure according to claim 2, wherein: and (3) the polishing process in the step S4, wherein the length direction stretching rate of the structural pattern of the surface metal (12) is controlled within 3 percent.
8. The method for rapid thinning and polishing of a surface heterostructure according to claim 1, wherein: the polishing solution used for the chemical thinning and the chemical mechanical polishing is a chemical agent capable of selectively corroding metals.
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| CN113526459B (en) * | 2021-07-16 | 2023-03-24 | 西南交通大学 | Surface planarization method for micro-scale 3D printing copper/nickel heterogeneous microstructure |
| CN114952600B (en) * | 2022-07-11 | 2023-09-19 | 赛莱克斯微系统科技（北京）有限公司 | Planarization method and device for high-frequency transmission microstructure and electronic equipment |
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