CN112597096B - A low-power FPGA partially reconfigurable method and device - Google Patents

Abstract

The invention provides a method and a device for reconstructing an FPGA part with low power consumption. The system device of the scheme of the invention effectively reduces the invalid power consumption of the FPGA static logic area by combining the cutting and reconstruction switching technology of the FPGA static area logic and the clock frequency real-time adjustment mechanism of the memory control interface dormancy and dynamic clock management unit, and further avoids the heat dissipation and stability problems caused by long-term working of the static logic area in a high-frequency state.

Description

A low-power FPGA partially reconfigurable method and device

Technical field

The present invention relates to the field of reconfigurable computing, and in particular to a low-power FPGA partially reconfigurable method and device.

Background technique

The system structure of a computer has a crucial impact on its information processing capabilities. However, it is difficult to find a universal computing architecture that is optimal for all computing tasks. For example, in the fields of machine learning, databases, image processing, communications, and financial computing, computing tasks with different attributes have their own corresponding computing architectures, which often require the design of dedicated customized chip architectures to obtain the best performance. Due to the high research and development costs and long production cycle of specialized computing chips, the industry has been exploring how to use more flexible solutions to solve this problem in recent years.

The idea of reconfigurable computing originated in the 1960s and was first proposed by Gerald Estrin of UCLA. The Estrin team's Fixed-Plus-Variable system is considered by the industry to be a prototype of reconfigurable computing. In Estrin's original vision, reconfigurable computing included a standard CPU as a central control unit and numerous reconfigurable computing units. These reconfigurable computing units are controlled by the central CPU and configured into the corresponding optimal architecture (i.e., hardware programming) when performing corresponding tasks (such as image processing, pattern recognition, scientific operations, etc.). However, limited by the level of electronic technology at the time, it was not until decades later that this design idea was truly realized with the development of programmable devices represented by FPGAs. By 2001, although the clock frequency of the computing unit (FPGA) used in reconfigurable computing was much lower than that of the CPU in the same period, the comprehensive computing power of reconfigurable computing could exceed that of the CPU by several times, and the power consumption was far less than that of the CPU.

FPGA (Field Programmable Gate Arrays) is a semiconductor device based on a matrix of configurable logic blocks connected through programmable interconnects. After such chips are manufactured, they can still be reprogrammed to meet the application or functional requirements required by the user. This characteristic distinguishes FPGAs from application-specific integrated circuits (ASICs), which are custom-built for specific design tasks. The current mainstream FPGA is mainly based on SRAM technology, and developers can reprogram it according to changes in design requirements.

PR (Partial Reconfiguration, Partial Reconfiguration) allows developers to dynamically reconfigure specific areas of the FPGA while the rest of the FPGA design continues to operate normally. This method is very effective in systems with multiple functions and where each functional module can be time-division multiplexed. These functional modules can share the same FPGA device resources in a time-sharing manner and switch dynamically in real time according to scene requirements. Many FPGA manufacturers can already provide relatively complete partially reconfigurable solutions. PR makes it possible to implement more complex, flexible and flexible FPGA systems. Partially reconfigurable solutions require dividing the FPGA's logic resources into two areas: the static logic area and the dynamic logic area. With the help of a partially reconfigurable technical framework, the FPGA system can adjust and divide the dynamic logic area according to the designer's needs, and switch the logic modules in the dynamic area in real time during system operation, dynamically adjusting the system's own hardware architecture. , thereby realizing the concept of reconfigurable computing. At present, mainstream cloud service providers use related technologies such as partial reconfiguration to effectively integrate their self-developed static logic area framework with the overall cloud platform framework to open the dynamic logic area of FPGA to external users. In this usage model, FPGA is deployed on the server side and serves as an acceleration device to provide external services; users remotely upload their own designed logic modules through the network, and run them directly in the FPGA device on the cloud server side and conduct related tests.

Partially reconfigurable solutions require dividing the FPGA's logic resources into two areas: a static logic area and a dynamic logic area. The static logic area will provide external communication interfaces, controller interfaces for onboard DDR3/DDR4/HBM and other memories, and dynamic logic areas. Necessary modules such as the control CPU are reconstructed, and various logical resources are reserved in the dynamic logic area to provide services to users. The static logic area and the dynamic logic area are connected through the on-chip configuration channel interface (such as Xilinx FPGA's ICAP/PCAP and other primitive modules). These primitive modules are channels for partially reconfigurable bit streams to be configured from the static area to the dynamic area. In the existing FPGA partial reconfiguration solutions in the industry, the static area logic, especially the control CPU of the static area logic, often only needs to work during the partial reconfiguration period of the dynamic area, and is often idle at other times. Considering that the FPGA system works most of the time in the stable operation stage of the dynamic area rather than the partially reconfigurable stage, most of the time, the CPU power consumption in the static area can be considered a waste. In addition, considering all possible needs of dynamic area logic, static area logic often needs to implement and provide all external interfaces as much as possible, including FPGA off-chip on-board DDR access control module, high-speed Ethernet module, PCIe, SRIO, Aurora, etc. Various high-speed bus interfaces. Take the DDR4 memory control module interface as an example. Since the DRAM unit needs to be refreshed repeatedly at a high frequency, it has to maintain a high energy consumption state once it is turned on.

Continuously working in the static logic area at a higher clock frequency also increases the burden of device heat dissipation. Long-term excessively high operating temperatures will inevitably affect the stability and life of the FPGA device and its surrounding electronic components. The existing technology only considers the performance of the dynamic area logic configuration and ignores the power consumption balance, so the static logic area is not flexibly adjusted. So far, relevant domestic and foreign research institutions and companies have not proposed a complete feasible solution to reduce the power consumption of FPGA partially reconfigurable systems.

To sum up, there is still room for improvement in the power consumption design of some FPGA reconfigurable systems in the industry, especially the power consumption design in the static area.

Contents of the invention

During the research on the partially reconfigurable design of FPGA, the inventor found that the existing technology only considered the performance of the dynamic area logic configuration and ignored the power consumption balance, so the static logic area was not flexibly adjusted.

The purpose of the present invention is to solve the problem of excessive ineffective power consumption of partially reconfigurable FPGAs existing in the prior art. Based on the cutting and reconstruction switching technology of static area logic and the dynamic clock management and control technology, the present invention designs an FPGA partially reconfigurable system device that saves power consumption without affecting functions or reducing performance.

Specifically, the present invention provides a low-power FPGA partially reconfigurable method, which includes:

Step 1. Cut the complete static area framework of the external interface logic according to the preset interface category, obtain multiple static area logics corresponding to specific interface categories, and place all the static area logic in the form of FPGA static area logic configuration files. In the non-volatile flash memory used for power-on startup configuration outside the FPGA chip;

Step 2. According to the logic characteristics of the dynamic area in the user's dynamic reconstruction instruction, obtain the interface required for user logic operation, and select the FPGA containing the corresponding interface in the non-volatile flash memory according to the interface category to which the interface required for user logic operation belongs. Static area logic configuration file, and then perform dynamic area configuration on the FPGA chip according to the user's dynamic reconstruction instructions.

The low-power FPGA partially reconfigurable method, wherein step 2 includes:

After completing the configuration of the dynamic area in the FPGA chip, the reconstructed dynamic clock unit is set up to dynamically adjust the clock of the CPU soft core and related logic modules in the static logic area of the FPGA chip.

The low-power FPGA partially reconfigurable method, wherein step 2 includes:

According to the usage status of each external memory in the dynamic logic area of the FPGA chip, control instructions are sent to the controller interface module of the external memory, so that the designated storage system works in a self-refresh state or a power-down sleep state.

The low-power FPGA partially reconfigurable method, wherein step 2 includes: selecting an initial default image of the static area logic in the non-volatile flash memory, and performing a second reconstruction under the guidance of the initial default image To guide the FPGA into the multi-boot image switching state, the logic of the static area on the FPGA chip is reconstructed. If the reconstruction fails and is interrupted, it will automatically fall back to the initial state.

The present invention also proposes a low-power FPGA partially reconfigurable system, which includes:

Module 1 is used to tailor the complete static area framework of the external interface logic according to the preset interface category, obtain multiple static area logics corresponding to specific interface categories, and convert all the static area logic to the FPGA static area logic configuration file. The form is placed in the non-volatile flash memory outside the FPGA chip for power-on startup configuration;

Module 2 is used to obtain the interface required for user logic operation based on the logic characteristics of the dynamic area in the user's dynamic reconstruction instruction, and select the corresponding interface included in the non-volatile flash memory according to the interface category to which the interface required for user logic operation belongs. FPGA static area logic configuration file, and then configure the FPGA on-chip dynamic area according to the user's dynamic reconstruction instructions.

The low-power FPGA partially reconfigurable system, wherein the module 2 includes:

After completing the configuration of the dynamic area in the FPGA chip, the reconstructed dynamic clock unit is set up to dynamically adjust the clock of the CPU soft core and related logic modules in the static logic area of the FPGA chip.

The low-power FPGA partially reconfigurable system, wherein the module 2 includes:

According to the usage status of each external memory in the dynamic logic area within the FPGA chip, control instructions are sent to the controller interface module of the external memory to cause the designated storage system to work in a self-refresh state or a power-down sleep state.

The low-power FPGA partially reconfigurable system, wherein the module 2 includes: selecting an initial default image of the static area logic in the non-volatile flash memory, and performing a second reconstruction under the guidance of the initial default image. To guide the FPGA into the multi-boot image switching state, the logic of the static area on the FPGA chip is reconstructed. If the reconstruction fails and is interrupted, it will automatically fall back to the initial state.

It can be seen from the above solutions that the advantages of the present invention are:

Compared with the original technical solutions in the industry, the system device described in the solution of the present invention effectively reduces the cost of FPGA static logic by combining the cutting and reconstruction switching technology of FPGA static area logic and the real-time clock frequency adjustment mechanism of the dynamic clock management unit. It also reduces the ineffective power consumption of the area and further avoids the heat dissipation and stability problems caused by the long-term operation of the static logic area in a high-frequency state.

Description of the drawings

Figure 1 is a schematic diagram of the partially reconfigurable overall framework of FPGA;

Figure 2 is a schematic diagram of the cutting and reconstruction switching technology of FPGA static area logic;

Figure 3 is a schematic diagram of the real-time adjustment mechanism of clock frequency based on the dynamic clock management unit;

Figure 4 is a flow chart of a specific embodiment of the present invention.

Detailed ways

The inventor analyzed the configuration scheme of the static logic area and the dynamic logic area and the power consumption composition of the static area, and proposed that reducing ineffective power consumption can be solved from two aspects:

The first aspect is to dynamically reduce the clock frequency of the static area logic to reduce the dynamic power consumption of the circuit caused by unnecessary high operating frequency, that is, by setting up a dynamically reconfigurable clock unit to replace the static clock in the current industry solution. unit, dynamically adjusts the clock of the CPU in the static logic area to reduce its power consumption in idle state;

The second aspect is to flexibly reduce the idle power consumption of the external controller interface in the static area logic. According to the cloud service provision method, it is divided into two types of sub-scenarios:

In the scenario where the entire FPGA provides services to a single user, multiple independent static area logical configuration schemes are divided on the off-chip NorFlash initialized and configured by the FPGA through multiple boot mirroring switchable modes. Each configuration scheme has a different static area. interface, for example, when the dynamic logical area does not need to access external DDR3 and DDR4 for a certain period of time, the static logical area can be initialized and configured as a framework without a DDR4 controller interface, and then the dynamic area can be configured, thus effectively reducing the cost of external controller access. Additional power consumption caused by idle interface. That is, the static area logic is directly trimmed, and the trimmed specific configuration files are selectively loaded as needed.

In a service scenario where the dynamic area resources of FPGA are divided and shared by multiple users, although the set of multiple user needs needs to be considered (generally, only the most complete static area logical framework with all interface modules can be selected, and in terms of time It is also not suitable for frequent loading of trimmed static area logical images), but in this scenario, the status of relevant static area modules (such as DDR memory control interface, etc.) can still be adjusted by combining the working requirements of the dynamic area, so that these modules do not need to work automatically switches to sleep mode. That is, when the static area logic cannot be cut and switched, for some modules, it is controlled to switch to sleep mode.

Specifically, based on the above concept, the present invention includes the following key technical points:

Key point 1: The solution of this invention first designs a set of soft-core CPUs for partially reconfigurable control, as well as complete external communication interfaces (including SRIO, high-speed Ethernet, Aurora and other high-speed protocol interfaces), external memory access control The static area framework of the interface (including DDR3, DDR4, HBM, etc.) logic, and the bit stream file containing the static area logical framework of all interfaces is used as the system default initialization image and placed outside the FPGA chip for power-on startup configuration. Non-volatile flash memory NorFlash. At the same time, based on the above-mentioned static area framework containing complete external interface logic, we perform classification and cutting, generate static area logic that only contains one or some specific interfaces, place it in other address segments of NorFlash, and record and save these trimmed static area frames. The first address information of the bit stream file stored in NorFlash.

In the actual operation stage, in the scenario where the overall FPGA provides services to a single user, the corresponding static area framework configuration bitstream file in NorFlash is selected based on the dynamic area logic characteristics uploaded by the user and the interface environment required for user logic operation. For example, the management program of the cloud service operation and maintenance center analyzes the dynamic logic that users need to run. If the running and testing of the dynamic logic does not require access to external storage, but only needs to access the external network, it can switch modes through multiple boot images. , load the static area logic that only retains necessary components such as the Ethernet interface and some reconfigurable control soft-core CPUs into the FPGA system after cutting, and then perform partial reconfiguration work on the corresponding areas of the dynamic area logic based on this. In cloud service scenarios where FPGA dynamic area resources need to be divided for multi-user sharing, the soft-core CPU can be partially reconfigurably controlled to send low-power mode to the controller interface module of external memory such as DDR3, DDR4 or HBM. For example, by sending relevant control instructions to make the storage system work in self-refresh mode or even power-down sleep mode, power consumption can still be dynamically reduced without cutting off the static area logic.

Technical effect: By selectively providing a tailored static area logic framework according to the needs of different users, the problem of continuous power consumption of redundant interface logic is avoided. Especially for scenarios where some user logic does not need to access any external memory and external communication interfaces, and only needs to complete all instruction and data interaction through the standard on-chip system bus (if ARM's AMBA protocol), tailored solutions are provided. The static area logic has a significant reduction in power consumption compared to the static area logic that directly and uniformly provides a complete external interface.

Key point 2: The dynamic clock control unit detects the status of some reconfigurable processes. When the dynamic logic area completes the configuration and begins to enter the stable operation stage, the dynamic clock control unit will monitor the clocks of the CPU soft core and other modules in the static area. The signal generation unit is restructured to operate at a lower clock frequency. When the next partial reconfiguration starts, the dynamic clock management unit once again reconstructs the corresponding clock generation unit in the static area to restore it to a high clock frequency output state, thereby ensuring that series modules such as soft-core CPUs can efficiently complete partial reconfiguration Work.

Technical effect: Since the FPGA partially reconfigurable system works most of the time in the stable operation stage of the dynamic logic area, the ineffective power consumption of the static area logic can be significantly reduced through dynamic clock frequency reduction.

The power consumption of FPGA is divided into static power consumption and dynamic power consumption. Dynamic power consumption mainly comes from the high-frequency charging and discharging actions of capacitors in the chip circuit, which can be formulaically described as:

in:

P _{D_avg} is the average dynamic power consumption;

_Cn refers to the equivalent load capacitance of the nth module circuit;

f _n refers to the average frequency of switching action of the n-th module circuit;

V refers to the circuit supply voltage.

It can be seen that the dynamic power consumption of FPGA is basically proportional to the clock frequency referenced when the circuit is running.

In order to make the above-mentioned features and effects of the present invention more clear and understandable, examples are given below and are described in detail with reference to the accompanying drawings.

Figures 1 and 4 show schematic diagrams of the partially reconfigurable overall framework of the FPGA of the present invention. The system device described in the solution of the present invention controls power consumption from two aspects: 1. Clipping and reconstruction switching technology based on FPGA static area logic; 2. Real-time adjustment mechanism of clock frequency based on dynamic clock management unit. By combining the above two aspects, the ineffective power consumption of the FPGA static logic area is effectively reduced. The following uses a Xilinx FPGA chip (model: XCVU37P) as an example to describe the embodiment of the present invention.

As shown in Figure 2, it is the cutting and reconstruction switching technology of FPGA static area logic.

First of all, we conducted a certain survey on the needs of FPGA cloud server users in recent years and found that most of the logic modules uploaded by users only require one or two external interfaces, and some even some user logic modules only need to pass through the chip. The AXI4 interface bus within can complete all instructions and data interactions. Therefore, although providing a complete set of static area logic that includes various external communication interfaces and memory control interfaces can meet the needs of different users, this approach often involves a certain degree of waste of resources and power consumption. For example, for user logic that does not need to access external DDR3, DDR4 and other memories, when these logics are configured into the dynamic logic area of FPGA and start running, their data interaction or caching needs can be met directly through the on-chip bus and on-chip memory. , nevertheless, the static area still needs to maintain the refresh rate of DDR3 and DDR4 uninterruptedly, and has to continue to maintain the operation of the corresponding memory control module in the static area logic. The accumulation of meaningless power consumption over a long period of time will bring significant waste and heat dissipation burden.

To this end, unlike the industry's current solution based on a single, fixed static area framework, the present invention tailors each external interface module in the static area frame one by one, resulting in a static area logical framework with multiple different external interface combinations. Mirror, and store the bit stream configuration files corresponding to these frame mirrors in different address segments in NorFlash off-chip of the FPGA for power-on startup configuration. As shown in the figure, at the first address of 0x00000000 in NorFlash, the bitstream configuration file of the complete static area logical frame image that has not been trimmed and has all external interfaces will be stored. When the FPGA system is powered on again, this file will be automatically loaded. The bitstream file of the complete frame image and completes the initial configuration of the static area frame.

When the first initialization configuration of the static area framework is completed, the cloud server management program will analyze the logic module information that the user is ready to upload and submit. If the user logic requires all types of external interfaces to work and test at this time, the management program will be directly based on the complete The static area logic framework transmits the partially reconfigurable bitstream file corresponding to the user logic to the FPGA system, and then configures the dynamic area. If after analysis, it is believed that the user logic does not need to access all external interfaces, but only needs one or some interfaces, or even does not need any interface and can complete the operation and testing work by relying only on the on-chip bus and on-chip storage resources, management The program will provide the FPGA system with a trimmed static area frame configuration image of the minimum external interface resources required for its operation, provide the first address information of the configuration image stored in NorFlash, guide the FPGA into the multi-boot image switchable mode, and reload the trimmed image. The final configuration bitstream is used to reconstruct the static area logic. If the logic reconstruction of the static area fails due to accidental factors and fails, the system will automatically return to the initial state to ensure that the FPGA can continue to run at least and provide some reconfigurable services. After the reconstruction is completed, the static area will work in a state of providing the minimum resources required by the user, and based on this, subsequent partial reconfiguration of the dynamic area logic will be carried out.

Optionally, for user logic that will be run repeatedly for a long time, in addition to loading and configuring the above-mentioned tailored static area logic, the power of related components of the board-level hardware can also be managed through the cloud server management program, such as appropriately turning off a certain Some onboard communication and storage hardware power supplies are used to further reduce overall system power consumption. However, since this method may disrupt the hardware power-on reset sequence of the server system, it needs to be performed according to the actual situation.

In cloud service scenarios where FPGA dynamic area resources need to be divided for multi-user sharing, when all users in the FPGA system do not need to access external storage for a period of time, the soft-core CPU can be controlled through partial reconfiguration. Send low-power mode instructions to the controller interface module of external memory such as DDR3, DDR4 or HBM (for example, by sending relevant control instructions to make the storage system work in self-refresh mode or even power-down sleep mode) so as not to cut the static area logic. Power consumption can be dynamically reduced while maintaining the integrity of the static area framework.

As shown in Figure 3, the clock frequency real-time adjustment mechanism is based on the dynamic clock management unit.

During the partial reconfiguration process, the bit stream needs to be configured through channels such as ICAP. The solution of the present invention adds a feedback mechanism for the partial reconfiguration state to the ICAP transmission control state machine. When the dynamic clock control unit detects the feedback signal that the dynamic logic area has completed the configuration and entered the stable operation stage, the dynamic clock control unit will reconstruct the exclusive clock generation unit of the CPU soft core and related logic modules in the static area to make it Working at a lower clock frequency, the relevant logic modules include: the on-chip local memory module of the CPU soft core, the storage interactive bus and the control unit, etc. When the next partial reconfiguration starts, the dynamic clock management unit reconfigures the corresponding clock unit in the static area again to restore it to a high clock frequency output state. During the switching process of different clock frequencies, the cross-clock domain problem is solved by directly inserting asynchronous clock FIFO into the CPU soft core and the on-chip interconnection switching unit (generally called Crossbar in English). By dynamically adjusting the clock frequency of relevant modules, it is ensured that soft-core CPU and other series modules can efficiently complete part of the reconfigurable work.

Actual test case:

In the experimental testing of the scheme and device of the present invention, we first set up the necessary units in the FPGA static area framework, including the CPU soft core for partial reconfigurable control and its configured on-chip Local RAM and ICAP channel units And control logic, SPI interface standard NorFlash control interface module and Crossbar unit and necessary FIFO module, while also adding DDR4 controller, Ethernet controller, serial port and other external interfaces.

A detailed evaluation of the design after placement and routing through EDA tools such as VIVADO found that:

For FPGA series models without integrated package HBM, the power consumption of the DDR4 controller is about 1.501~1.609W, which roughly accounts for 22%~28% of the overall static area frame. For FPGA series models with integrated HBM packaging, when the HBM-related components are in the idle state, the power consumption of the HBM memory particles is about 0.240~0.253W, and in the working state, the power consumption of the HBM memory particles is about 0.833~0.890W. At the same time, The logic power consumption of the HBM controller located in the FPGA chip is about 1.155~1.167W, accounting for about 16%~17% of the overall static area frame.

At the same time, considering that the XCVU37P device is an SSI (Stacked Silicon Interconnect, stacked silicon interconnect technology) device with multiple SLRs (Super Logic Region, super logic region), and in order to improve the overall system performance of the FPGA, the static area framework and ICAP channels are often concentrated It is laid out in the main SLR area, that is, SLR0. This layout method may also cause the problem of excessive local temperature within the chip during long-term operation. Through the technology described in the present invention, this actual measurement case is tailored and a set of low-power FPGA partially reconfigurable system is generated. For user logic that does not require external access to DDR4 memory, power consumption may be reduced:

Different types of CPU soft cores in the static area have different power consumption. In the test phase of the work of the present invention, taking the Microblaze soft core and its attached on-chip storage, bus and other modules as an example, when running at a higher clock frequency (200MHz), the CPU soft core and its attached parts in the static area logical framework are The power consumption of the module and the power consumption of the CPU soft core and its auxiliary modules in the static area logical framework after the dynamic clock management unit is downclocked to 25MHz are:

Clock frequency 200MHz 25MHz Soft core power consumption 0.241W 0.030W Power consumption of on-chip local memory module required by soft core 0.211W 0.026W Soft core AXI4 bus power consumption 0.092W 0.029W

In addition, since the main control CPU of the static area logical framework and the on-chip bus frequency are reduced, the power consumption of the Crossbar module is also reduced from 0.336W to 0.148W, saving 55.95% of the power consumption to 0.188W; and the static area backup The power consumption of the on-chip storage Local RAM and its control module also dropped from 0.752W to 0.148W, saving 80.32% of the power consumption to 0.604W.

Combined with other logic modules, the overall power consumption of the static area logic framework is reduced from 3.601W to 2.135W, saving 1.466W of power consumption. Compared with the power consumption of the clock-free dynamic adjustment scheme, the power consumption is reduced by 40.71%, and the effect is significant.

In summary, the solution of the present invention effectively reduces the cost by combining the cutting and reconstruction switching technology of the FPGA static area logic or the low-power mode adjustment technology of the controller interface module with the real-time clock frequency adjustment mechanism of the dynamic clock management unit. The ineffective power consumption of the FPGA static logic area is eliminated. For some user logic that does not need to access off-chip memory, the above technology can even reduce the power consumption of the static area framework by more than 40%. At the same time, the power consumption reduction effect of the solution of the present invention also enables the FPGA system to effectively avoid the heat dissipation and stability problems caused by the long-term operation of the static logic area in a high-frequency state.

The following is a system embodiment corresponding to the above method embodiment. This implementation mode can be implemented in conjunction with the above implementation mode. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be described again in order to reduce duplication. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above-mentioned embodiments.

The present invention also proposes a low-power FPGA partially reconfigurable system, which includes:

Module 1 is used to tailor the complete static area framework of the external interface logic according to the preset interface category, obtain multiple static area logics corresponding to specific interface categories, and convert all the static area logic to the FPGA static area logic configuration file. The form is placed in the non-volatile flash memory outside the FPGA chip for power-on startup configuration;

Module 2 is used to obtain the interface required for user logic operation based on the logic characteristics of the dynamic area in the user's dynamic reconstruction instruction, and select the corresponding interface included in the non-volatile flash memory according to the interface category to which the interface required for user logic operation belongs. FPGA static area logic configuration file, and then configure the FPGA on-chip dynamic area according to the user's dynamic reconstruction instructions.

The low-power FPGA partially reconfigurable system, wherein the module 2 includes:

After completing the configuration of the dynamic area in the FPGA chip, the reconstructed dynamic clock unit is set up to dynamically adjust the clock of the CPU soft core and related logic modules in the static logic area of the FPGA chip.

The low-power FPGA partially reconfigurable system, wherein the module 2 includes:

According to the usage status of each external memory in the dynamic logic area within the FPGA chip, control instructions are sent to the controller interface module of the external memory to cause the designated storage system to work in a self-refresh state or a power-down sleep state.

The low-power FPGA partially reconfigurable system, wherein the module 2 includes: selecting an initial default image of the static area logic in the non-volatile flash memory, and performing a second reconstruction under the guidance of the initial default image. To guide the FPGA into the multi-boot image switching state, the logic of the static area on the FPGA chip is reconstructed. If the reconstruction fails and is interrupted, it will automatically fall back to the initial state.

Claims (6)

1. A low-power FPGA partially reconfigurable method, characterized by: Step 1. According to the preset interface category, tailor the complete static area framework of the external interface logic to obtain multiple static area logics corresponding to specific interface categories, and convert all the static area logic into the form of FPGA static area logic configuration image files. They are placed in different address ranges in the non-volatile flash memory outside the FPGA chip for power-on startup configuration; Step 2: Analyze the logic characteristics of the dynamic area in the user's dynamic reconstruction instructions, obtain the interfaces required for the user's logic operation, and extract the interface information of the interfaces required for the user's logic operation; Step 3. According to the interface information of the interface required for user logic operation, the management program will provide the FPGA system with a trimmed static area frame configuration image file of the minimum external interface resources required for its operation, and provide the configuration image file for storage in NorFlash. The first address information of the interval guides the FPGA into the multi-boot image switchable mode; Step 4. The multi-image startup judgment module selects the FPGA static area logic configuration file containing the corresponding interface in the non-volatile flash memory. Based on the initial default image of the static area logic in the non-volatile flash memory, the initial default image is booted Perform a second reconstruction to guide the FPGA to switch between multiple boot images and reconstruct the logic of the static area in the FPGA chip; if the reconstruction fails and is interrupted, it will automatically fall back to the initial state; Step 5: After completing the secondary reconstruction of the static area logic, perform the FPGA on-chip dynamic area configuration process according to the user's dynamic reconstruction instructions. 2. The low-power FPGA partially reconfigurable method according to claim 1, characterized in that step 5 includes completing the second reconstruction of the static area logic and reducing the static area logic by reconstructing the dynamic clock unit. Dynamic power consumption; the reconstructed dynamic clock unit includes: After completing the configuration of the dynamic area in the FPGA chip, set up the reconstructed dynamic clock unit to dynamically adjust the CPU soft core and related logic modules in the static logic area in the FPGA chip; when the dynamic clock control unit detects the dynamic logic area After completing the configuration of the feedback signal and entering the stable operation stage, the dynamic clock control unit will reconstruct the dedicated clock generation unit of the CPU soft core and related logic modules in the static area so that it works at a lower clock frequency, so The above-mentioned relevant logic modules include: the on-chip local memory module of the CPU soft core, the storage interactive bus and the control unit; when the next partial reconfiguration starts, the dynamic clock management unit once again reconstructs the corresponding clock unit in the static area to restore it to High clock frequency output state. 3. The low-power FPGA partially reconfigurable method according to claim 1, characterized in that step 5 includes completing the second reconstruction of the static area logic and reducing the static area through low-power memory access settings. Logic dynamic power consumption; the low-power memory access settings include: According to the usage status of each external memory in the dynamic logic area within the FPGA chip, control instructions are sent to the controller interface module of the external memory to cause the designated storage system to work in a self-refresh state or a power-down sleep state. 4. A low-power FPGA partially reconfigurable system, characterized by: Module 1 is used to tailor the complete static area framework of the external interface logic according to the preset interface category, obtain multiple static area logics corresponding to specific interface categories, and configure all the static area logic with FPGA static area logic image files The forms are placed in different address ranges in the non-volatile flash memory outside the FPGA chip for power-on startup configuration; Module 2 is used to analyze the logic characteristics of the dynamic area in the user's dynamic reconstruction instructions, obtain the interface required for the user's logic operation, and extract the interface information of the interface required for the user's logic operation. Module 3 is used to operate the user logic according to the interface information required by the interface. The management program will provide the FPGA system with a trimmed static area frame configuration image file of the minimum external interface resources required for its operation, and provide the configuration image file in NorFlash. The first address information in the storage area guides the FPGA to enter the multi-boot image switchable mode; Module 4 is used to enable the multi-mirror startup judgment module to select the FPGA static area logic configuration file containing the corresponding interface in the non-volatile flash memory, based on the initial default image of the static area logic in the non-volatile flash memory. A second reconstruction is performed under the guidance of the image to guide the FPGA to perform multi-boot mirror switching and reconstruct the logic of the static area in the FPGA chip; if the reconstruction fails and is interrupted, it will automatically fall back to the initial state; Module 5 is used to perform the FPGA on-chip dynamic area configuration process according to the user's dynamic reconstruction instructions after completing the second reconstruction of the static area logic. 5. The low-power FPGA partially reconfigurable system according to claim 4, characterized in that the module 5 is also used to reduce the static area by reconstructing the dynamic clock unit after completing the second reconstruction of the static area logic. Area logic dynamic power consumption; the reconstructed dynamic clock unit includes: After completing the configuration of the dynamic area in the FPGA chip, set up the reconstructed dynamic clock unit to dynamically adjust the CPU soft core and related logic modules in the static logic area in the FPGA chip; when the dynamic clock control unit detects the dynamic logic area After completing the configuration of the feedback signal and entering the stable operation stage, the dynamic clock control unit will reconstruct the dedicated clock generation unit of the CPU soft core and related logic modules in the static area so that it works at a lower clock frequency, so The above-mentioned relevant logic modules include: the on-chip local memory module of the CPU soft core, the storage interactive bus and the control unit; when the next partial reconfiguration starts, the dynamic clock management unit once again reconstructs the corresponding clock unit in the static area to restore it to High clock frequency output state. 6. The low-power FPGA partially reconfigurable system as claimed in claim 4, characterized in that the module 5 is also used to reduce the cost through low-power memory access settings after completing the secondary reconstruction of the static area logic. Static area logic dynamic power consumption; the low-power memory access settings include: According to the usage status of each external memory in the dynamic logic area within the FPGA chip, control instructions are sent to the controller interface module of the external memory to cause the designated storage system to work in a self-refresh state or a power-down sleep state.