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CN112597716A - Method for simulation screening of bottleneck units based on STA (station) and SPICE (simulation program with Integrated Circuit emphasis) models - Google Patents

Method for simulation screening of bottleneck units based on STA (station) and SPICE (simulation program with Integrated Circuit emphasis) models Download PDF

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CN112597716A
CN112597716A CN202011474137.2A CN202011474137A CN112597716A CN 112597716 A CN112597716 A CN 112597716A CN 202011474137 A CN202011474137 A CN 202011474137A CN 112597716 A CN112597716 A CN 112597716A
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CN112597716B (en
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江荣贵
董森华
郭超
陈彬
都长鑫
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Nanjing Huada Jiutian Technology Co Ltd
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Abstract

A method for simulating and screening bottleneck units based on STA and SPICE models comprises the following steps: setting experience parameters and screening a time sequence path of the time sequence violation; respectively counting units contained in the time sequence paths of the time sequence violation and the non-violation and associating the units; making a screening strategy of the bottleneck unit, and obtaining a bottleneck unit data set and distinguishing primary and secondary by screening bottleneck characteristic unit operation; checking whether the time sequence path of the time sequence violation is completely covered according to the incidence relation between the time sequence path and the unit, and constructing a new data set for the uncovered time sequence violation time sequence path to execute iteration; and obtaining a final bottleneck unit data set through iteration to carry out time sequence repair. The method for screening the bottleneck unit based on the STA and the SPICE model can comprehensively consider the logical structures and the physical characteristics of the Path and the Cell, quickly screen the bottleneck Cell and accelerate the time sequence repair work of the time sequence violation Path and the time sequence acceptance engineering of the whole IC design.

Description

Method for simulation screening of bottleneck units based on STA (station) and SPICE (simulation program with Integrated Circuit emphasis) models
Technical Field
The invention relates to the technical field of Electronic Design Automation (EDA), in particular to a method for simulation screening of bottleneck cells based on STA and SPICE models.
Background
Timing analysis is a key problem in an ASIC design flow, sta (static Timing analysis) has a fast execution speed, does not require a test vector, and has a Timing path coverage rate of almost 100%, whereas a gate-level or transistor-level Timing simulation method based on an SPICE model can simultaneously complete the analysis of circuit Timing and functions, has high precision, and supports various types of circuits. While the criticality and importance of Local Variation increases as IC processes advance, conventional OCV models ignore the logical progression and physical placement factors of the circuit devices, resulting in STA results that are too pessimistic for most of the Path and too optimistic for a small fraction of the Path. The SPICE model simulation can well identify the physical characteristics of the circuit device, and continuously approaches to a true value in an approximate iteration mode, but the SPICE model simulation has the defect of overlong calculation time. When a Timing Path (Path) with Timing violation occurs, how to quickly locate a bottleneck Cell (Cell) and quickly complete Timing repair (Timing ECO) becomes a core problem that digital IC engineers need to face.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a method for screening bottleneck cells based on simulation of an STA (station) and an SPICE (simulation program with integrated circuit emphasis) model, which can comprehensively consider the logical structures and physical characteristics of Path and Cell, quickly screen the bottleneck Cell and accelerate the time sequence repair work of the time sequence violation Path and the time sequence acceptance engineering of the whole IC design.
In order to achieve the above object, the method for screening bottleneck units based on simulation of the STA and SPICE models provided by the present invention comprises the following steps:
setting experience parameters and screening a time sequence path of the time sequence violation;
respectively counting units contained in the time sequence paths of the time sequence violation and the non-violation and associating the units;
making a screening strategy of the bottleneck unit, and obtaining a bottleneck unit data set and distinguishing primary and secondary by screening bottleneck characteristic unit operation;
checking whether the time sequence path of the time sequence violation is completely covered or not according to the incidence relation between the time sequence path and the unit, and if the time sequence path of the time sequence violation is not completely covered, constructing a new data set for the uncovered time sequence violation time sequence path to execute iteration;
and obtaining a final bottleneck unit data set through iteration to carry out time sequence repair.
Further, the step of setting the experience parameter and screening the timing path of the timing violation further comprises,
screening out a data subset in an original time sequence path data set according to the time sequence analysis key parameter empirical value;
and simulating the time sequence path elements in the data subset to obtain the accurate value of the key parameter.
The method further comprises the steps of making a screening strategy of the bottleneck unit, screening bottleneck characteristic unit data sets through operation, distinguishing primary and secondary data sets, counting total occurrence times of units contained in all time sequence path elements in the time sequence path data subsets and complementary sets thereof, sequencing the units, and extracting the units in sequence to construct a first unit data subset.
Further, the method comprises the steps of judging whether any element in the unit data subsets obtained by the time sequence violation path belongs to the unit data subsets obtained by the non-time sequence violation path, if so, removing the element from the unit data subsets, and sequentially iterating in sequence to obtain a first unit data subset which finally meets the condition.
Furthermore, the step of formulating a screening strategy of the bottleneck unit, obtaining a bottleneck unit data set through screening bottleneck characteristic unit operation and distinguishing primary and secondary comprises the steps of calculating unit delay average absolute differences in non-public time sequence violation path sections and sequencing the unit delay average absolute differences, and extracting units according to the sequence to construct a second unit data subset.
Furthermore, the step of formulating a screening strategy of the bottleneck unit, obtaining a bottleneck unit data set through operation of a screening bottleneck feature unit and distinguishing primary and secondary data further comprises the steps of calculating and sequencing average influence ratios of unit delays in non-public timing violation path sections on slack calculation, and extracting units according to the sequence to construct a third unit data subset.
Furthermore, the method comprises the step of taking the intersection of the first unit data subset, the second unit data subset and the third unit data subset as a main bottleneck unit data set, and taking the complement of the main bottleneck unit data set in the union of the three data subsets as a secondary bottleneck unit data set.
Further, the method comprises the steps of checking whether the time sequence paths of the time sequence violation are completely covered according to the incidence relation between the time sequence paths and the units to judge whether the time sequence paths are ended or enter iteration, checking whether the units are completely covered in all the time sequence violation time sequence paths according to the sequence from the main bottleneck unit dataset to the secondary bottleneck unit dataset, if the units are not completely covered, constructing a new time sequence violation time sequence path dataset for the uncovered time sequence paths, returning to execute a screening strategy for setting a bottleneck unit, and performing operation by a screening bottleneck feature unit to obtain the bottleneck unit dataset and distinguish the primary time from the secondary time sequence paths, and stopping iteration until all the time sequence violation time sequence paths are completely covered.
To achieve the above object, the present invention further provides an electronic device, which includes a memory and a processor, where the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the method for screening bottleneck units based on STA and SPICE model simulation as described above.
To achieve the above object, the present invention further provides a computer-readable storage medium having stored thereon a computer program, which when executed performs the steps of the method for screening bottleneck cells based on STA and SPICE model simulation as described above.
The method for screening the bottleneck unit based on the simulation of the STA and the SPICE model, the electronic equipment and the computer readable storage medium have the following advantages that:
1) the method fully utilizes the advantages of high STA execution speed, full coverage rate and high simulation precision of the SPICE model, comprehensively considers the logical structures and physical characteristics of Path and Cell, is more accurate and fast on the premise of ensuring that the extracted bottleneck Cell data set covers the time sequence violation Path by 100%, can complete screening of the bottleneck Cell data set as soon as possible, and accelerates time sequence repair work of the time sequence violation Path and time sequence acceptance engineering of the whole IC design.
2) The structural association of Path and Cell, the cross calibration of STA and SPICE model simulation results, and the calculation and influence of key time sequence parameters are fully integrated, and a more comprehensive and more accurate bottleneck Cell data set is obtained. In the final determination of the bottleneck Cell data set, the primary and secondary properties are determined by adopting simple operations such as set intersection, solution and complementation, the whole process does not need complex formula calculation, the expansibility is strong, and more bottleneck Cell characteristic description modes can be integrated.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
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The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flowchart of a method for screening bottleneck cells based on STA and SPICE model simulation according to the present invention;
FIG. 2 is a flow chart of a collaborative screening of Paths datasets for timing violations according to an embodiment of the present invention;
FIG. 3 is a flow chart of an iterative screening Bottleneck Cells data set according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flowchart of a method for screening bottleneck units based on STA and SPICE model simulation according to the present invention, and the method for screening bottleneck units based on STA and SPICE model simulation according to the present invention will be described in detail with reference to fig. 1.
First, in step 101, a Path-based STA resultRoughly selecting the Path of the time sequence violation, carefully selecting the Path of the time sequence violation based on the SPICE model simulation result of the Path, and respectively counting and associating the cells contained in the Path of the time sequence violation and the Path of the non-violation. In the step, the advantages of STA and SPICE model simulation are considered. The method is characterized in that a data set positioned to the time sequence violation can be rapidly screened, the STA execution speed is high, the coverage rate is high, the precision is reduced along with the development of the IC process, and the key parameter threshold T is passedslackThe alternative selection set of the sequential violation Path can be preliminarily and quickly screened; the SPICE model simulation has high precision, can verify the circuit function and structure, but consumes longer time, and can further complete accurate screening on an alternative time sequence violation Path data set through simulation.
Preferably, with the advantages of fast performance and full coverage of the STA, a subset Q is preliminarily screened in the original Path data set U, so that each element Path (i) in Q satisfies the following condition:
Figure BDA0002834579280000041
wherein,
Figure BDA0002834579280000042
STA computation delay slack representing path element path (i)STAThe above conditions are satisfied. T isslackAn empirical value representing a key parameter slack of the STA timing analysis, wherein the default value is 0, so as to obtain a path data set of the STA timing violation; and when the positive number threshold value is adopted, partial paths with over-optimistic STA can be screened out to enter the Path data subset Q.
Preferably, each element Path (i) in the screened Path data subset Q is simulated by using SPICE model simulation to obtain an accurate value of its slack key parameter. Screening a subset Q 'of Q so that each element path (j) in Q' satisfies the following condition:
Figure BDA0002834579280000043
wherein,
Figure BDA0002834579280000044
SPICE emulation delay slack representing path element path (j)SPICEThe above conditions are satisfied. Because the simulation precision of the SPICE model is higher, the screening can be carried out by directly using the slack parameter threshold value as 0.
In step 102, a screening strategy of the bottleneck Cells is specified, and the previous N bottleneck Cell characteristics are obtained to obtain a bottleneck Cell data set through simple set operation and distinguish primary and secondary. In the step, a screening strategy of some bottleneck Cells is formulated, such as effective frequency of the Cells, average absolute difference value of Cell delay, average influence of Cell on path delay calculation and the like, and the bottleneck Cell data sets are obtained by taking the Top N bottleneck characteristics Cells through simple set operation and primary and secondary distinguishing.
Preferably, the Path data subset Q' and its complement are counted separately
Figure BDA0002834579280000051
The total number of Cell occurrences contained in all the elements in the Cell (wherein the total number of Cell occurrences on Common Path is kept constant), and the Cell data subsets are sorted from the Top to the bottom in sequence, and the cells with Top N arrays are taken to construct Cell data subsets
Figure BDA0002834579280000052
And
Figure BDA0002834579280000053
a subset of Cell data obtained representing a path of timing violation, and
Figure BDA0002834579280000054
a subset of Cell data representing non-timing violation paths, an
Figure BDA0002834579280000055
Any cell in the list needs to satisfy the following conditions:
Figure BDA0002834579280000056
and is
Figure BDA0002834579280000057
If the cell belongs to both sets, it is selected from
Figure BDA0002834579280000058
Removing the Top and taking the Top N +1 cells
Figure BDA0002834579280000059
And
Figure BDA00028345792800000510
and determining to reserve or eliminate according to the condition of formula 3, and so on until the Cell data subset satisfying formula 3
Figure BDA00028345792800000511
The number of elements in the Cell is N or no new Cell enters
Figure BDA00028345792800000512
I.e. the iterative process is stopped.
Preferably, the Cell delay average absolute difference of the cells in the non-Common Path is sequentially calculated according to equation 4 and sorted from large to small, and the cells arranged with Top N are directly taken to form the Cell data subset
Figure BDA00028345792800000513
Figure BDA00028345792800000514
Wherein, delaySTAIs the unit delay of the unit in each path calculated by the STA table lookupSPICEIs the cell delay of each cell in each path obtained through SPICE simulation,
Figure BDA00028345792800000515
it is an average value calculated for the absolute difference of the cell delays that occur in each path for each cell.
Preferably, the average influence ratio of the unit delay in the non-Common Path to the Slack calculation is calculated according to the formula 5, the formula 6 and the formula 7
Figure BDA0002834579280000061
Finally, according to the sequence from big to small, directly taking the Top Top N arranged cells to form a Cell data subset
Figure BDA0002834579280000062
Establishing a time sequence check:
Figure BDA0002834579280000063
maintaining the timing sequence for checking:
Figure BDA0002834579280000064
average impact factor:
Figure BDA0002834579280000065
wherein, in formula 5, TsetupRepresenting the establishing time of the timing unit of the termination point, uncertaintiy representing the uncertainty of the Clock deviation, crpr representing the pessimistic elimination quantity (Clock recovery Pessimism Roval) of the common path of the Clock, the pessimistic elimination quantity on the common path section of the Clock, and LcellRefers to the cell logic depth, L, of the cellpathThe total logical depth of the unit of the path is indicated; in formula 6, TholdRepresenting the hold time of the end point timing unit; in the formula 7, the compound represented by the formula,
Figure BDA0002834579280000066
an average value is calculated representing the influence of each element in each path delay calculation. The calculation in the formula 5 and the formula 6 is divided into two parts, wherein the former considers the influence of unit delay on the path delay in the setup path and hold path time sequence calculation, and the delaySPICEThe larger the value of (A), the greater its influence; the latter considers the influence of the logic depth of the current Cell in the whole path, and calculates an adjustment coefficient based on the logic depth of the Cell, wherein the adjustment coefficient is in the range of (1.0, 1.1)]The more the Cell logic position is, the closer the ratio approaches 1.1 (according to launch)&data path and capture path, respectively). Equation 7 converts the result of each occurrence of each Cell into a comprehensive influence factor in an arithmetic average manner, and the larger the value of the factor is, the stronger the influence is, and the factor is more worthy of attention.
In this embodiment, the Cell screening module is an extensible bottleneck. If a complex algorithm is adopted to obtain a comprehensive bottleneck Cell characteristic evaluation factor, it becomes difficult and more difficult to interpret a new Cell bottleneck influence factor, and the calculation time is increased. And the Top N data sets of each single Cell bottleneck characteristic are integrated through simple set operation to obtain a final bottleneck Cell data set, when new Cell bottleneck influence factors are blended, the method is relatively simple, and excessive calculation amount cannot be increased.
In step 103, the coverage rate of the time sequence violation Path is checked through the association relationship between the Path and the Cell, if the coverage rate is less than 100%, a new data set is constructed for the uncovered time sequence violation Path to perform the next iteration, and the iteration process is stopped until the coverage rate reaches 100%.
Preferably, a subset of Cell data is taken
Figure BDA0002834579280000071
Taking Cell data subsets as the main bottleneck Cell data set
Figure BDA0002834579280000072
As a candidate bottleneck Cell data set, subset Cell data
Figure BDA0002834579280000073
As a secondary bottleneck Cell dataset. And according to C∩→C*The sequential screening of (1) checks whether the coverage of these cells in all the paths of timing violations reaches 100% (i.e., these cells appear at least once in the Path of each timing violation).
In step 104, if C∪If all the cells in the system can not completely cover all the time sequence violation Path, constructing a new time sequence violation Path data set by the uncovered Path, returning to the step 102, and stopping the iterative process until the coverage rate of all the time sequence violation Path in the step 103 reaches 100%, thereby obtaining a final bottleneck Cell data set CfinalThe timing sequence signing is accelerated as the key data of timing sequence repairing.
In this embodiment, a reasonable data check and iteration strategy. According to the incidence relation between the Path and the Cell, whether the coverage rate of the time sequence violation Path associated with the bottleneck Cell data set reaches 100% is checked to be used as a condition for finishing the iteration process, and the objective requirements of circuit time sequence analysis and time sequence repair are considered. And if the coverage rate does not reach 100%, constructing a new data set by the uncovered time sequence violation Path to execute the next iteration, so that the iteration process can be quickly completed, and the method is more reasonable compared with an iteration strategy for improving the N value of Top N.
In this embodiment, the bottleneck Cell data subset used for coverage rate check at the end of the iterative process is the final result obtained by the iterative process, and the method has the characteristics of high timing violation coverage, reasonable Cell number, obvious bottleneck characteristics, interpretability and the like, and can be further used for subsequent projects such as circuit timing analysis and timing repair.
The method for screening bottleneck units based on simulation of STA and SPICE models according to the present invention is further described below with reference to a specific embodiment.
Fig. 2 is a schematic diagram of a data flow process for cooperatively screening the timings violation Paths according to an embodiment of the present invention.
In this embodiment, as shown in fig. 2, the organization of the timing path is classified according to the timing result simulated by the STA and SPICE models.I.e. at a known empirical parameter TslackThe screening of Path can be directly completed in batch, and the simulation from STA to SPICE model is a process of gradually screening from coarse to fine.
Fig. 3 is a schematic diagram of a process for iteratively screening bottleeck Cells data streams according to an embodiment of the present invention.
In this embodiment, as shown in fig. 3, in a process of screening a bottleneck Cell (bottolenck Cell), characteristics of the number of occurrences of the Cell, an average difference of Cell delays, and a path delay calculation comprehensive influence are taken into consideration, where a front Top N of the number of occurrences is determined by statistical data corresponding to a timing Violation (Violation) and is corrected by statistical data corresponding to a Non-timing Violation (Non-Violation); the front Top N of the unit delay average difference value and the path delay calculation comprehensive influence is directly calculated by the data of the time sequence violation. In the bottleneck unit data set, intersection n is a key Cell data set, and a complement in union u is a secondary Cell data set, and when checking the time sequence violation Path coverage rate, statistical checking needs to be performed according to the sequence by carrying in turn. And when the path coverage rate is less than 100%, constructing a new data set by the uncovered Paths with the timing violation, and repeatedly executing the iterative process until the path coverage rate reaches 100%, wherein the bottleneck unit data subset applied to the checking of the coverage rate is the final screening result of the iterative process. The diagram can be intuitively obtained, and because a simple set operation mode is adopted to synthesize different bottleneck Cell characteristics, more characteristic screening conditions can be added to obtain more accurate results through a Cell bottleneck characteristic extraction module in an extension flow.
The invention provides a method for rapidly positioning a key or bottleneck Cell based on the cross application of STA and SPICE model simulation time sequence results, wherein the STA and SPICE model simulation time sequence results are used in a cross mode, and a set of technical scheme for rapidly positioning the bottleneck Cell is summarized by combining the logical structures and physical characteristics of Path and Cell, so that the time sequence repair and time sequence acceptance links are accelerated, the advantages of high STA running speed, high coverage rate and high SPICE model simulation precision are integrated, and the time period of digital IC design is further shortened. Empirical parameter TslackIs helpful for improvingToo optimistic STA results from OCV, reasonable TslackThe value is beneficial to seeking balance between improving the coverage rate of the STA screening time sequence violation path and reducing the time length of the SIPCE model simulation task, and rich IC experts and engineers can directly set through experience. Furthermore, even if inexperienced, T can be solved dynamically by combining the technical solutions of the present inventionslackIs about to take value
Figure BDA0002834579280000081
The paths with negative values are arranged in the order from small to large, and accurate values need to be obtained by SPICE model simulation to weaken the over-pessimistic influence of STA results; the value of which is regular can be obtained by carrying out SPICE model simulation according to the method until the value is obtained
Figure BDA0002834579280000082
The positive case is that K (K) continuously appears>0) Then stop for a while, then TslackThen taking the value corresponding to the first time of this consecutive sequence
Figure BDA0002834579280000083
In a characteristic module for extracting bottleneck Cell, the occurrence frequency of the Cell is considered firstly, and a time sequence violation path data set Q' and a complementary set thereof are counted
Figure BDA0002834579280000091
Screening and eliminating a Cell data set of Top N, and quickly obtaining the Cell data set through iteration; secondly, considering a Top N Cell data set with a large unit delay average absolute difference in simulation results of the STA and the SPICE model; finally, the average influence of the Cell on each Path delay calculation is considered, the factor is fused with the Setup or Hold time sequence checking rule and the logic depth influence of the Cell in the Path, and a Cell data set of the Top N before the influence factor is taken. No matter which bottleneck characteristic Cell data set is extracted, the interference of Common Cell and destructive Cell is eliminated in advance to enhance and improve the accuracy, the invention fully integrates the structural association of Path and Cell, the cross calibration of STA and SPICE model simulation results and the key time sequenceAnd (3) calculating and influencing parameters, aiming at obtaining a more comprehensive and more accurate bottleneck Cell data set. In the final determination of the bottleneck Cell data set, the primary and secondary properties are determined by adopting simple operations such as set intersection, solution and complementation, the whole process does not need complex formula calculation, the expansibility is strong, and more bottleneck Cell characteristic description modes can be integrated.
The invention provides a repeated iteration strategy for improving the coverage rate of a bottleneck Cell data set on a time sequence violation Path, namely, the uncovered time sequence violation Path is taken as a new data set to be repeatedly executed, so that screening is only needed on the basis of calculation of a first iteration process, and the iteration process can be stopped after the coverage rate is quickly reached to 100%. The other idea is to improve the N value of Top N to improve the coverage rate, but the process is biased to an empirical type and a probabilistic type, the step length M of each increase of the N value is difficult to confirm, the step length M is small, and the iteration times are multiplied; the step length M is large, the number of elements of the screened Cell data set is increased, interference is enhanced, and accuracy is reduced. In contrast, the iterative method adopted by the invention is more accurate and rapid on the premise of ensuring that the extracted bottleneck Cell data set covers the time sequence violation Path by 100%, and can complete screening of the bottleneck Cell data set as soon as possible and accelerate subsequent time sequence repair and time sequence signing engineering. The advantages of high STA execution speed, full coverage rate and high simulation precision of the SPICE model are fully utilized, the logical structures and the physical characteristics of the Path and the Cell are comprehensively considered, and the bottleneck Cell is quickly screened out, so that the time sequence repair work of the time sequence violation Path and the time sequence acceptance engineering of the whole IC design are accelerated.
In an embodiment of the present invention, there is also provided an electronic device, including a memory and a processor, where the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the method for screening bottleneck units based on STA and SPICE model simulation as described above.
In an embodiment of the present invention, there is also provided a computer readable storage medium having stored thereon a computer program which, when running, performs the steps of the method for screening bottleneck cells based on STA and SPICE model simulation as described above.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A method for screening bottleneck units based on simulation of STA and SPICE models is characterized by comprising the following steps:
setting experience parameters and screening a time sequence path of the time sequence violation;
respectively counting units contained in the time sequence paths of the time sequence violation and the non-violation and associating the units;
making a screening strategy of the bottleneck unit, and obtaining a bottleneck unit data set and distinguishing primary and secondary by screening bottleneck characteristic unit operation;
checking whether the time sequence path of the time sequence violation is completely covered according to the incidence relation between the time sequence path and the unit, and constructing a new data set for the uncovered time sequence violation time sequence path to execute iteration;
and obtaining a final bottleneck unit data set through iteration to carry out time sequence repair.
2. The method for screening bottleneck cells based on STA and SPICE model simulation as claimed in claim 1, wherein the step of setting empirical parameters, screening timing paths for timing violations, further comprises,
screening out a data subset in an original time sequence path data set according to the time sequence analysis key parameter empirical value;
and (4) simulating the time sequence path elements in the data subset to obtain a key parameter accurate value, and determining a final time sequence violation path set.
3. The method according to claim 1, wherein the step of formulating a screening policy for the bottleneck unit, obtaining a bottleneck unit data set through a screening bottleneck feature unit operation and distinguishing primary and secondary comprises the steps of counting total occurrence times of units included in all time sequence path elements in the time sequence path data subset and complementary set thereof, sorting the units, and extracting the units in sequence to construct the first unit data subset.
4. The method according to claim 3, further comprising determining whether any element in the unit data subsets obtained from the timing violation path belongs to a non-timing violation path to obtain a unit data subset, if so, removing the element from the unit data subset, and sequentially iterating in order to obtain a first unit data subset that finally satisfies the condition.
5. The method according to claim 4, wherein the step of formulating a screening policy for the bottleneck unit, obtaining a bottleneck unit data set through a screening bottleneck feature unit operation and distinguishing primary and secondary comprises the steps of calculating unit delay mean absolute differences in non-public timing violation path segments and sequencing the same, and extracting units in sequence to construct the second unit data subset.
6. The method according to claim 5, wherein the step of formulating a screening policy for the bottleneck unit, obtaining a bottleneck unit data set through screening bottleneck feature unit operation and distinguishing primary and secondary data further comprises the steps of calculating and sorting average influence ratios of unit delays in non-public timing violation path segments on slack calculation, and extracting units in order to construct a third unit data subset.
7. The method for screening bottleneck cells based on STA and SPICE model simulation as claimed in claim 6, further comprising taking the intersection of the first, second and third subsets of cell data as a primary bottleneck cell data set and taking the complement of the primary bottleneck cell data set in the union of the three subsets of data as a secondary bottleneck cell data set.
8. The method according to claim 1, wherein the step of checking whether the timing paths of the timing violations are completely covered according to the association relationship between the timing paths and the units, and constructing a new data set for the timing violations that are not covered to perform iteration, further comprises the steps of checking whether the units are completely covered in all the timing violations according to the sequence from the primary bottleneck unit data set to the secondary bottleneck unit data set, if not, constructing a new timing violations timing path data set for the timing paths that are not covered, returning to the step of making a screening policy for the bottleneck units, and performing a bottleneck feature unit screening to obtain a bottleneck unit set and distinguishing primary and secondary, and stopping iteration until all the timing violations timing paths are completely covered.
9. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the method for screening bottleneck units based on STA and SPICE model simulation according to any one of claims 1 to 8.
10. A computer-readable storage medium, having stored thereon a computer program, wherein the computer program is configured to, when running, perform the steps of the method for screening bottleneck cells based on STA and SPICE model simulation of any of claims 1 to 8.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114021514A (en) * 2021-11-26 2022-02-08 北京华大九天科技股份有限公司 Method for screening bottleneck unit by SPICE voltage or temperature scanning simulation
CN115017848A (en) * 2022-08-08 2022-09-06 摩尔线程智能科技(北京)有限责任公司 Method and apparatus for converging timing violations of multi-layered circuits
CN115796093A (en) * 2023-01-03 2023-03-14 摩尔线程智能科技(北京)有限责任公司 Circuit timing optimization method, device, electronic equipment and storage medium

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100005429A1 (en) * 2008-07-02 2010-01-07 Synopsys, Inc. Integrated single spice deck sensitization for gate level tools
CN101826124A (en) * 2009-03-06 2010-09-08 台湾积体电路制造股份有限公司 System and method for analyzing integrated circuit performance
US20170004244A1 (en) * 2015-06-30 2017-01-05 Synopsys, Inc. Look-ahead timing prediction for multi-instance module (mim) engineering change order (eco)
CN110598235A (en) * 2019-06-25 2019-12-20 眸芯科技（上海）有限公司 Method and system for repairing time sequence violation in chip design
US20200134114A1 (en) * 2018-10-24 2020-04-30 International Business Machines Corporation Superposition of canonical timing value representations in statistical static timing analysis
WO2020176684A1 (en) * 2019-02-26 2020-09-03 Synopsys, Inc. Novel method to compute timing yield and yield bottleneck using correlated sample generation and efficient statistical simulation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100005429A1 (en) * 2008-07-02 2010-01-07 Synopsys, Inc. Integrated single spice deck sensitization for gate level tools
CN101826124A (en) * 2009-03-06 2010-09-08 台湾积体电路制造股份有限公司 System and method for analyzing integrated circuit performance
US20170004244A1 (en) * 2015-06-30 2017-01-05 Synopsys, Inc. Look-ahead timing prediction for multi-instance module (mim) engineering change order (eco)
US20200134114A1 (en) * 2018-10-24 2020-04-30 International Business Machines Corporation Superposition of canonical timing value representations in statistical static timing analysis
WO2020176684A1 (en) * 2019-02-26 2020-09-03 Synopsys, Inc. Novel method to compute timing yield and yield bottleneck using correlated sample generation and efficient statistical simulation
CN110598235A (en) * 2019-06-25 2019-12-20 眸芯科技（上海）有限公司 Method and system for repairing time sequence violation in chip design

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CHAKRAVARTHI V.S. 等: "Static Timing Analysis(STA)", 《A PRACTICAL APPROACH TO VLSI SYSTEM ON CHIP(SOC) DESIGN》, pages 99 - 116 *
唐拓 等: "专用集成电路静态时序分析", 《微处理机》, no. 2, pages 17 - 18 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114021514A (en) * 2021-11-26 2022-02-08 北京华大九天科技股份有限公司 Method for screening bottleneck unit by SPICE voltage or temperature scanning simulation
CN115017848A (en) * 2022-08-08 2022-09-06 摩尔线程智能科技(北京)有限责任公司 Method and apparatus for converging timing violations of multi-layered circuits
CN115017848B (en) * 2022-08-08 2022-10-25 摩尔线程智能科技(北京)有限责任公司 Method and apparatus for converging timing violations of multi-tiered circuits
CN115796093A (en) * 2023-01-03 2023-03-14 摩尔线程智能科技(北京)有限责任公司 Circuit timing optimization method, device, electronic equipment and storage medium
CN115796093B (en) * 2023-01-03 2023-08-08 摩尔线程智能科技(北京)有限责任公司 Circuit timing optimization method, device, electronic equipment and storage medium

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