CN112599602B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate in which an active region surrounded by a first trench filling structure is formed; At least one third trench on one side of the second trench filling structure is formed in the substrate of the active region, and the bottom wall of the third trench is higher than that of the first trench filling structure a bottom surface; a gate dielectric layer, formed on the inner wall of the third trench and the substrate on the periphery of the third trench; and a gate layer, formed on the gate dielectric layer and close to the third trench part of the trench on the second trench fill structure. The technical solution of the present invention can reduce the on-resistance without reducing the breakdown voltage.

Description

Semiconductor device and method of manufacturing the same

technical field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

Lateral double-diffused metal oxide semiconductor (LDMOS, lateral double-diffused MOS) is now widely used in power integrated circuits (power ICs). The most important parameters of LDMOS are on-resistance (Ron) and breakdown voltage (BV), The smaller the on-resistance, the better, and the larger the breakdown voltage, the better. The two are contradictory. When the on-resistance and breakdown voltage are optimized by adjusting the ion implantation conditions, the size of the field plate region, and the device size, if the on-resistance is to be further reduced, the breakdown voltage will decrease. voltage, it will cause the on-resistance to increase.

For example, as shown in FIG. 1a and FIG. 1b is an LDMOS with a shallow trench isolation structure (STI), an active region A1 is defined according to the layout, and the LDMOS includes a substrate 10 and a body region 11 located in the substrate 10 of the active region. and the drift region 12 , the body contact region 15 and the source region 16 located in the body region 11 and the drain region 17 located in the drift region 12 , the LDMOS further includes a gate dielectric layer 13 and a gate layer located on the substrate 10 in sequence 14 and a shallow trench isolation structure 18 in the substrate 10 in the active region A1. The shallow trench isolation structure 18 is a field oxide layer of LDMOS, the shallow trench isolation structure 18 is located on one side of the gate dielectric layer 13 , a part of the gate layer 14 is located above the channel, and the other part extends laterally to the shallow trench isolation structure Above 18, the portion of the gate layer 14 above the channel constitutes the gate region of the LDMOS, and the portion extending to the shallow trench isolation structure 18 constitutes the field plate. The depth of the shallow trench isolation structure 18 is the same as the depth of the shallow trench isolation structure (not shown) at the periphery of the active region A1, and the gate dielectric layer 13 and the gate layer 14 extend from the body region 11 to the drift region 12. The region 12 surrounds the shallow trench isolation structure 18 , the drain region 17 is located in the drift region 12 on the side of the shallow trench isolation structure 18 away from the gate layer 14 , the body contact region 15 and the source region 16 are located in the gate layer 14 in the body region 11 on the side away from the shallow trench isolation structure 18 . Although the LDMOS with the shallow trench isolation structure shown in FIG. 1a and FIG. 1b has a high breakdown voltage because the shallow trench isolation structure 18 is partially located under the gate layer 14, the current passes through the deeper shallow trench. The bottom of the isolation structure 18 will generate higher on-resistance.

Therefore, how to further reduce the on-resistance while keeping the breakdown voltage unchanged is an urgent problem to be solved at present.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the on-resistance without reducing the breakdown voltage.

To achieve the above object, the present invention provides a semiconductor device, comprising:

a substrate, in which an active region surrounded by a first trench filling structure is formed;

A second trench filling structure and at least one third trench on one side of the second trench filling structure are formed in the substrate of the active region, and the bottom wall of the third trench is higher than all the the bottom surface of the first trench filling structure;

a gate dielectric layer formed on the inner wall of the third trench and the substrate on the periphery of the third trench; and,

A gate layer is formed on the gate dielectric layer and on a portion of the second trench filling structure close to the third trench.

Optionally, a side of the third trench close to the second trench filling structure exposes the second trench filling structure.

Optionally, the length of all the third trenches in the edge direction perpendicular to the side of the second trench filling structure is greater than that of the one side parallel to the second trench filling structure. The length in the edge direction of the side.

Optionally, the semiconductor device includes at least two third trenches, and all the third trenches are sequentially arranged along an edge direction parallel to the one side of the second trench filling structure.

Optionally, the bottom surface of the second trench filling structure is flush with the bottom surface of the first trench filling structure; or, the bottom surface of the second trench filling structure is flush with the bottom wall of the third trench flush.

Optionally, both ends of the second trench filling structure are in contact with sidewalls of the first trench filling structure; both ends of the gate layer are located on the gate dielectric layer and close to the third A portion of the trench extends above the second trench filling structure to the first trench filling structure.

Optionally, the semiconductor device further includes a body region and a drift region formed in the substrate of the active region, a boundary between the body region and the drift region is located below the gate layer, and The drift region surrounds the second trench fill structure, and the third trench extends from the drift region to the body region.

Optionally, the semiconductor device further includes a source region and a drain region, the source region is located in a body region of the gate layer away from the second trench filling structure, and the drain region is located in in the drift region of the second trench filling structure on the side facing away from the source region.

Optionally, an end of the third trench facing away from the second trench filling structure exceeds an end of the gate layer facing away from the second trench filling structure, and the third trench One end of the one facing away from the second trench filling structure extends to the source region.

The present invention also provides a method for manufacturing a semiconductor device, comprising:

providing a substrate;

A first trench, a second trench and at least one third trench are formed in the substrate, the first trench encloses an active area in the substrate, and the second trench is formed In the substrate of the active region, the at least one third trench is formed in the substrate of the active region on one side of the second trench, and the depth of the third trench is smaller than that of the first trench. the depth of a groove;

forming a first trench filling structure in the first trench and forming a second trench filling structure in the second trench;

forming a gate dielectric layer on the inner wall of the third trench and the substrate on the periphery of the third trench; and,

A gate layer is formed on the gate dielectric layer and on a portion of the second trench filling structure close to the third trench.

Optionally, a side of the third groove close to the second groove communicates with the second groove.

Optionally, the length of all the third grooves in the edge direction perpendicular to the side of the second groove is greater than the edge direction parallel to the side of the second groove on the length.

Optionally, the step of forming the first trench, the second trench and the at least one third trench in the substrate includes:

First, a first trench is formed in the substrate, and then a second trench and at least one third trench are simultaneously formed in the substrate. The depth of the second trench is the same as the depth of the third trench. same depth;

Alternatively, a first trench and a second trench are simultaneously formed in the substrate, and then at least one third trench is formed in the substrate, and the depth of the second trench is the same as that of the first trench. The grooves have the same depth.

Optionally, the steps of forming the first trench filling structure in the first trench and forming the second trench filling structure in the second trench include:

forming an insulating dielectric layer to fill the first trench, the second trench and the third trench; and,

The insulating dielectric layer in the third trench is removed to form a first trench filling structure in the first trench and a second trench filling structure in the second trench.

Optionally, both ends of the second trench are communicated with the sidewalls of the first trench; both ends of the gate layer are connected from the gate dielectric layer and a portion close to the third trench. The second trench filling structure extends over the first trench filling structure.

Optionally, the manufacturing method of the semiconductor device further includes forming a body region and a drift region in the substrate of the active region; the boundary between the body region and the drift region is located below the gate layer , the drift region surrounds the second trench, and the third trench extends from the drift region to the body region.

Optionally, the manufacturing method of the semiconductor device further includes forming a source region and a drain region, the source region is located in a body region of the gate layer that is far away from the second trench filling structure, the The drain region is located in the drift region on the side of the second trench filling structure facing away from the source region.

Compared with the prior art, the technical scheme of the present invention has the following beneficial effects:

1. The semiconductor device of the present invention includes at least one third trench on one side of the second trench filling structure, and the bottom wall of the third trench is higher than the bottom surface of the first trench filling structure, and the gate layer formed on the gate dielectric layer and the part of the second trench filling structure close to the third trench, so that the on-resistance can be reduced without reducing the breakdown voltage.

2. The method for manufacturing a semiconductor device of the present invention comprises forming a first trench, a second trench and at least one third trench in a substrate, wherein the first trench is surrounded by a source region, the second trench is formed in the substrate of the active region, the at least one third trench is formed in the substrate of the active region on one side of the second trench, the The depth of the third trench is less than the depth of the first trench; forming a first trench filling structure in the first trench and forming a second trench filling structure in the second trench; forming a gate A dielectric layer is formed on the inner wall of the third trench and the substrate on the periphery of the third trench; and a gate layer is formed on the gate dielectric layer and a portion of the first trench close to the third trench. On the two trench filling structures, the on-resistance can be reduced without reducing the breakdown voltage.

Description of drawings

1a is a layout of an existing LDMOS with a shallow trench isolation structure;

Fig. 1b is a schematic cross-sectional view of the LDMOS with the shallow trench isolation structure shown in Fig. 1a along the AA' direction;

2a is a layout of a semiconductor device according to an embodiment of the present invention;

Fig. 2b is a schematic cross-sectional view of the semiconductor device shown in Fig. 2a along the BB' direction;

Figure 2c is a schematic cross-sectional view of the semiconductor device shown in Figure 2a along the CC' direction;

Fig. 2d is a schematic cross-sectional view of the semiconductor device shown in Fig. 2a along the DD' direction;

Figure 2e is a schematic cross-sectional view of the semiconductor device shown in Figure 2a along the EE' direction;

2f is a layout of a semiconductor device according to another embodiment of the present invention;

Fig. 2g is a schematic cross-sectional view of the semiconductor device shown in Fig. 2f along the FF' direction;

3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

4a to 4m are device schematic diagrams in the method for manufacturing the semiconductor device shown in FIG. 3 .

Wherein, the reference signs in Fig. 1a to Fig. 4m are described as follows:

10-substrate; 11-body region; 12-drift region; 13-gate dielectric layer; 14-gate layer; 15-body contact region; 16-source region; 17-drain region; 18-shallow trench Isolation structure; 20-substrate; 201-pad oxide layer; 202-silicon nitride layer; 203-insulating dielectric layer; 21-first trench filling structure; 211-first trench; 22-second trench filling 221-second trench; 23-third trench; 24-gate dielectric layer; 25-gate layer; 26-body region; 261-source region; 262-body contact region; 27-drift region; 271-drain region; 28-conductive contact plug.

Detailed ways

In order to make the objects, advantages and features of the present invention clearer, the semiconductor device and its manufacturing method proposed by the present invention will be further described in detail below with reference to the accompanying drawings. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

An embodiment of the present invention provides a semiconductor device, referring to FIGS. 2 a to 2 g , the semiconductor device includes a substrate 20 , a second trench filling structure 22 , at least one third trench 23 , a gate dielectric layer 24 and a gate The electrode layer 25, an active region A2 surrounded by the first trench filling structure 21 is formed in the substrate 20; The at least one third trench 23 is formed in the substrate 20 of the active region A2, and the bottom wall of the third trench 23 is higher than the bottom surface of the first trench filling structure 21; the gate The dielectric layer 24 is formed on the inner wall of the third trench 23 and the substrate 20 around the third trench 23; the gate layer 25 is formed on the gate dielectric layer 24 and close to the third trench 23 A portion of the trench 23 is on the second trench filling structure 22 .

The semiconductor device provided by this embodiment will be described in detail below with reference to FIGS. 2a to 2g.

An active region A2 surrounded by the first trench filling structure 21 is formed in the substrate 20 .

The material of the substrate 20 can be any suitable substrate known to those skilled in the art.

The second trench filling structure 22 and the at least one third trench 23 on one side of the second trench filling structure 22 are formed in the substrate 20 of the active region A2, the third trench The bottom wall of the trench 23 is higher than the bottom surface of the first trench filling structure 21 .

The top surfaces of the first trench filling structure 21 and the second trench filling structure 22 may be flush with the top surface of the substrate 20, or the first trench filling structure 21 and the The top surface of the two trench filling structures 22 may be higher than the top surface of the substrate 20 . The first trench filling structure 21 and the second trench filling structure 22 both function as isolation.

所述第一沟槽填充结构21和所述第二沟槽填充结构22的位于所述衬底20中的部分的深度可以为

The bottom surface of the second trench filling structure 22 may be flush with the bottom surface of the first trench filling structure 21 , and the depth of the third trench 23 is smaller than that of the first trench filling structure 21 and the first trench filling structure 21 . The depth of the portion of the second trench filling structure 22 located in the substrate 20, the depth of the third trench 23 may be

The depths of the portions of the first trench filling structure 21 and the second trench filling structure 22 located in the substrate 20 may be

所述第一沟槽填充结构21的位于所述衬底20中的部分的深度可以为

Alternatively, the bottom surface of the second trench filling structure 22 is flush with the bottom wall of the third trench 23 , that is, the depth of the portion of the second trench filling structure 22 located in the substrate 20 is equal to The depths of the third trenches 23 are all smaller than the depths of the first trench filling structures 21 located in the substrate 20 , and the second trench filling structures 22 are located in the substrate 20 . The depth of the part and the depth of the third trench 23 may be

The depth of the portion of the first trench filling structure 21 located in the substrate 20 may be

If the depth of the third trench 23 is smaller than the depths of the portions of the first trench filling structure 21 and the second trench filling structure 22 located in the substrate 20 , the third trench The side of 23 close to the second trench filling structure 22 exposes the top of the sidewall of the second trench filling structure 22 , and the entire sidewalls at both ends of the second trench filling structure 22 are in contact with the second trench filling structure 22 . A sidewall of the trench filling structure 21 is in contact; if the depth of the portion of the second trench filling structure 22 located in the substrate 20 and the depth of the third trench 23 are both smaller than the first trench the depth of the portion of the trench filling structure 21 located in the substrate 20, the entire sidewall of the third trench 23 on the side close to the second trench filling structure 22 and the second trench The sidewalls of the filling structures 22 are in contact, and both ends of the second trench filling structures 22 are in contact with the tops of the sidewalls of the first trench filling structures 21 .

The semiconductor device may include at least two third trenches 23 , and all the third trenches 23 are sequentially arranged along an edge direction parallel to the one side of the second trench filling structure 22 .

The gate dielectric layer 24 is formed on the inner wall of the third trench 23 and the substrate 20 around the third trench 23 . A side of the gate dielectric layer 24 close to the second trench filling structure 22 is in contact with the second trench filling structure 22 , and the gate dielectric layer 24 is parallel to the second trench filling structure Both ends of the one side of 22 in the edge direction are in contact with the first trench filling structure 21 .

The gate layer 25 is formed on the gate dielectric layer 24 and a portion of the second trench filling structure 22 close to the third trench 23 . Both ends of the gate layer 25 (ie, the ends parallel to the edge direction of the one side of the second trench filling structure 22 ) extend from the gate dielectric layer 24 and close to the third trench. A portion of the trench 23 extends from the second trench filling structure 22 to the first trench filling structure 21 . The second trench filling structure 22 is a field oxide layer of the semiconductor device, and the portion of the gate layer 25 located above the channel region defined by the layout constitutes the gate region of the semiconductor device, and extends to the gate region of the semiconductor device. The portion on the second trench-fill structure 22 constitutes a field plate.

The gate layer 25 may cover all the third trenches 23 , that is, the end of the third trench 23 facing away from the second trench filling structure 22 does not extend beyond the gate layer 25 One end of the 22 that faces away from the second trench filling structure 22, as shown in FIG. 2a; or, the gate layer 25 may only cover part of the third trench 23, that is, the third trench 23 The end of the gate layer 25 facing away from the second trench filling structure 22 may extend beyond the end of the gate layer 25 facing away from the second trench filling structure 22, as shown in FIG. 2f.

The semiconductor device further includes a body region 26 and a drift region 27 formed in the substrate 20 of the active region A2 , and the boundary between the body region 26 and the drift region 27 is located at the edge of the gate layer 25 . Below, the drift region 27 surrounds the second trench filling structure 22 , and the third trench 23 extends from the drift region 27 to the body region 26 .

The semiconductor device further includes a source region 261 and a drain region 271, the source region 261 is located in the body region 26 of the gate layer 25 away from the second trench filling structure 22, the drain The region 271 is located in the drift region 27 on the side of the second trench filling structure 22 facing away from the source region 261 . When the source region 261 and the drain region 271 are formed, a body contact region 262 may also be formed in the body region 26 , and the body contact region 262 is located opposite to the source region 261 . In the body region 26 on one side of the gate layer 25 , a first trench filling structure 21 is also spaced between the body contact region 262 and the source region 261 .

As shown in FIGS. 2 a and 2 f , the semiconductor device further includes conductive contact plugs formed on the source region 261 , the drain region 271 , the body contact region 262 and the gate layer 25 . 28, and the conductive contact plug 28 on the gate layer 25 is located above the first trench filling structure 21; and as shown in FIG. 2f and FIG. 2g, the third trench 23 faces away from all One end of the second trench filling structure 22 may extend to the source region 261 , and the bottom of the conductive contact plug 28 is in contact with the source region 261 under the third trench 23 .

In addition, the lengths of all the third trenches 23 in the edge direction perpendicular to the side of the second trench filling structure 22 are greater than those parallel to the second trench filling structure 22 . The length in the edge direction of one side makes the increase of the width of the channel region defined by the layout larger than the increase of the length of the channel region. Since the portion between the source region 261 and the drain region 271 located under the gate dielectric layer 24 is a channel region, the direction between the source region 261 and the drain region 271 is The length direction of the channel region, the length direction of the channel region is perpendicular to the direction of the edge of the side of the second trench filling structure 22, and the width direction of the channel region is parallel to the direction in which the edge of the one side of the second trench filling structure 22 is located, then the length of all the third trenches 23 in the length direction of the channel region is greater than that in the channel region length in the width direction.

2a, 2b and 2e, the transverse cross-sectional pattern of the third groove 23 is a rectangle, and the cross-sectional patterns along the BB' and EE' directions of the third groove 23 are all inverted trapezoids, The short side of the rectangle is connected to the side of the second trench filling structure 22 , and the long side of the rectangle is perpendicular to the side of the second trench filling structure 22 ; defining the third trench 23 The length of the bottom wall in the length direction of the channel region is L1, the length of the sidewall of the third trench 23 in the length direction of the channel region is L3, and the third trench 23 has a length of L3. The length of the bottom wall of the trench 23 in the width direction of the channel region is L2, and the length of the sidewall of the third trench 23 in the width direction of the channel region is L4. When one of the third trenches 23 is used, the length of the channel region is increased by a length L3 (because the entire sidewall of the third trench 23 close to the second trench filling structure 22 is exposed. the second trench filling structure 22, so that the sidewall of the third trench 23 close to the second trench filling structure 22 cannot increase the length of the channel region), the length of the channel region The width is increased by two lengths L4. Since L3=L4, the length of the channel region increases by less than the width of the channel region, and L1>L2, so the width of the channel region The percentage of increase (the ratio of the length of two L4s based on the increase of the length of L2) is greater than the percentage of increase in the length of the channel region (the ratio of the length of one L3 based on the increase of the length of L1), that is, the width of the channel region The magnitude of the increase is greater than the magnitude of the increase in the length of the channel region; the greater the number of the third trenches 23, the greater the increase in the width of the channel region, the greater the width of the channel region The larger the amplitude is, the greater the on-resistance can be reduced without reducing the breakdown voltage.

Especially for the embodiments shown in FIG. 2f and FIG. 2g, since the end of the third trench 23 facing away from the second trench filling structure 22 extends to the source region 261 and exposes the first A sidewall of the trench filling structure 21, so that the end of the third trench 23 facing away from the second trench filling structure 22 cannot increase the length of the channel region, further making the channel region The increase in the width of the channel region is greater than the increase in the length of the channel region.

From the above content, since at least one third trench 23 is formed on one side of the second trench filling structure 22, the at least one third trench 23 extends from the drift region 27 to the The body region 26 increases the width of the channel region without changing the width of the layout. For example, the part of the body region 26 under the gate layer 25 is an effective channel region, The width of the effective channel region is increased by 50% to 100%, and the number of inversion carriers in the channel is increased by 50% to 100%, thereby greatly reducing the on-resistance without reducing the breakdown voltage. .

Furthermore, if the thickness of the portion of the second trench filling structure 22 located in the substrate 20 is the same as the depth of the third trench 23 and both are smaller than the thickness of the first trench filling structure 21 The thickness of the part located in the substrate 20 is reduced, the thickness of the second trench filling structure 22 located in the substrate 20 is reduced, so that the on-resistance is further reduced.

To sum up, the semiconductor device provided by the present invention includes: a substrate in which an active region surrounded by a first trench filling structure is formed; a second trench filling structure and a At least one third trench on one side of the trench filling structure is formed in the substrate of the active region, and the bottom wall of the third trench is higher than the bottom surface of the first trench filling structure; gate dielectric layer, formed on the inner wall of the third trench and the substrate on the periphery of the third trench; and a gate layer, formed on the gate dielectric layer and on the part close to the third trench on the second trench filling structure. The semiconductor device of the present invention can reduce the on-resistance without reducing the breakdown voltage.

An embodiment of the present invention provides a method for manufacturing a semiconductor device. Referring to FIG. 3 , FIG. 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. The method for manufacturing a semiconductor device includes:

Step S1, providing a substrate;

Step S2, forming a first trench, a second trench and at least one third trench in the substrate, the first trench enclosing an active region in the substrate, the second trench A trench is formed in the substrate of the active region, the at least one third trench is formed in the substrate of the active region on one side of the second trench, and the depth of the third trench is less than the depth of the first groove;

Step S3, forming a first trench filling structure in the first trench and forming a second trench filling structure in the second trench;

Step S4, forming a gate dielectric layer on the inner wall of the third trench and the substrate on the periphery of the third trench;

Step S5 , forming a gate layer on the gate dielectric layer and on a portion of the second trench filling structure close to the third trench.

The manufacturing method of the semiconductor device provided by the present embodiment will be described in more detail below with reference to FIGS. 4a to 4m. 4c, 4e, 4g, 4i, 4k, and 4m are schematic cross-sectional views of the semiconductor device along the direction of CC', and Figures 4c, 4e, Figure 4g, Figure 4i, Figure 4k, and Figure 4m correspond to Figure 4b, Figure 4d, Figure 4f, Figure 4h, Figure 4j, and Figure 4l in turn.

According to step S1, a substrate 20 is provided, and the material of the substrate 20 can be any suitable substrate known to those skilled in the art.

According to step S2 , a first trench 211 , a second trench 221 and at least one third trench 23 are formed in the substrate 20 , and the first trench 211 encloses a space in the substrate 20 The active region (ie the active region A2 shown in FIGS. 2a and 2f ), the second trench 221 is formed in the substrate 20 of the active region A2, and the at least one third trench 23 is formed In the substrate 20 of the active region A2 on one side of the second trench 221 , the depth of the third trench 23 is smaller than the depth of the first trench 211 .

The step of forming the first trench 211, the second trench 221 and the at least one third trench 23 in the substrate 20 includes:

所述衬底20中的所述第一沟槽211的深度可以为

First, a first trench 211 is formed in the substrate 20 , and then a second trench 221 and at least one third trench 23 are simultaneously formed in the substrate 20 . Specifically, the pad oxide layer 201 and the silicon nitride layer 202 may be covered on the substrate 20 first; then, as shown in FIG. 4a, the silicon nitride layer 202, the pad oxide layer 201 and part of the The substrate 20 is etched to form a first trench 211 in the substrate 20 with a thickness of As shown, the substrate 20 of the active region A2 surrounded by the first trench 211 and the silicon nitride layer 202 and the pad oxide layer 201 above the substrate 20 are etched to form a second trench a groove 221 and at least one third groove 23, the depth of the second groove 221 is the same as the depth of the third groove 23, and the depth of the second groove 221 and the third groove 23 is less than The depth of the first trench 211, the depth of the second trench 221 and the depth of the third trench 23 in the substrate 20 may be

The depth of the first trench 211 in the substrate 20 may be

所述衬底20中的所述第一沟槽211和所述第二沟槽221的深度可以为

Alternatively, the first trench 211 and the second trench 221 are simultaneously formed in the substrate 20 , and then at least one third trench 23 is formed in the substrate 20 , which is also formed by photolithography and etching. the first trench 211, the second trench 221 and the third trench 23, and the depth of the second trench 221 is the same as the depth of the first trench 211, the The depths of the three trenches 23 are smaller than the depths of the first trenches 211 and the second trenches 221 , and the depth of the third trenches 23 in the substrate 20 may be

The depths of the first trench 211 and the second trench 221 in the substrate 20 may be

If the depth of the second trench 221 is the same as the depth of the third trench 23 and the depths of the second trench 221 and the third trench 23 are smaller than the depth of the first trench 211 , Then the entire sidewall of the third trench 23 on the side close to the second trench 221 is communicated with the second trench 221 (as shown in FIG. 4c ). The end communicates with the top of the sidewall of the first trench 211; if the depth of the second trench 221 is the same as that of the first trench 211 and the depth of the third trench 23 is smaller than that of the first trench 211 If the depths of the groove 211 and the second groove 221 are equal, the side of the third groove 23 close to the second groove 221 communicates with the top of the side wall of the second groove 221, so The entire sidewalls of both ends of the second trench 221 communicate with the first trench 211 .

The manufacturing method of the semiconductor device may include forming at least two of the third trenches 23 in the substrate 20 of the active region A2, all of the third trenches 23 being parallel to the second trenches 23 . The edge directions of the one side of the grooves 221 are arranged in sequence.

According to step S3 , a first trench filling structure 21 is formed in the first trench 211 and a second trench filling structure 22 is formed in the second trench 221 . The first trench filling structure 21 and the second trench filling structure 22 both function as isolation. Its steps include:

First, an insulating dielectric layer 203 is formed to fill in the first trenches 211 , the second trenches 221 and the third trenches 23 , and the insulating dielectric layer 203 buries the silicon nitride layer 202 in the Then, the insulating dielectric layer 203 is planarized by using a chemical mechanical polishing process until the top surface of the silicon nitride layer 202 is exposed, as shown in FIG. 4d and FIG. 4e, the first trench 211 The insulating dielectric layer 203 is connected to the insulating dielectric layer 203 in the second trench 221; then, the silicon nitride layer 202 and the pad oxide layer 201 are removed, as shown in FIG. 4f and FIG. 4g, the remaining The top surface of the insulating dielectric layer 203 is higher than the top surface of the substrate 20; then, the insulating dielectric layer 203 in the third trench 23 is removed by dry etching or wet etching, so that the The first trench filling structure 21 is formed in the first trench 211 and the second trench filling structure 22 is formed in the second trench 221, as shown in FIG. 4h and FIG. A trench filling structure 21 and the second trench filling structure 22 use a different filling pattern from that of the insulating dielectric layer 203 .

The top surfaces of the first trench filling structure 21 and the second trench filling structure 22 may be flush with the top surface of the substrate 20, or the first trench filling structure 21 and the The top surface of the two trench filling structures 22 may be higher than the top surface of the substrate 20 (as shown in FIGS. 4h and 4i ).

According to step S4, a gate dielectric layer 24 is formed on the inner wall of the third trench 23 and the substrate 20 around the third trench 23, as shown in FIG. 4j and FIG. 4k. The gate dielectric layer 24 may be formed by a deposition or thermal oxidation process. The side of the gate dielectric layer 24 close to the second trench 221 is in contact with the second trench filling structure 22 (as shown in FIG. 2d and FIG. 2e ). Both ends of the one side of the second trench 221 in the edge direction are in contact with the first trench filling structure 21 (as shown in FIG. 4j ).

According to step S5, a gate layer 25 is formed on the gate dielectric layer 24 and a portion of the second trench filling structure 22 close to the third trench 23, as shown in FIG. 4l, FIG. 2d and FIG. 2e . And, as shown in FIG. 4l and FIG. 4m, both ends of the gate layer 25 (ie, the ends parallel to the edge direction of the one side of the second trench 221) from the gate dielectric layer 24 and a portion of the second trench filling structure 22 close to the third trench 23 extends to the first trench filling structure 21 . The gate layer 25 can be formed using conventional deposition, photolithography and etching processes.

The second trench filling structure 22 is a field oxide layer of the semiconductor device, and the portion of the gate layer 25 located above the channel region defined by the layout constitutes the gate region of the semiconductor device, and extends to the gate region of the semiconductor device. The portion on the second trench-fill structure 22 constitutes a field plate.

The gate layer 25 may cover all the third trenches 23 , that is, the end of the third trench 23 facing away from the second trench 221 does not extend beyond the back of the gate layer 25 . to one end of the second trench 221, as shown in FIG. 2a; alternatively, the gate layer 25 may only cover a part of the third trench 23, that is, the third trench 23 faces away from the end of the third trench 23. One end of the second trench 221 may extend beyond the end of the gate layer 25 facing away from the second trench 221, as shown in FIG. 2f.

In addition, after forming the first trench 211 , the second trench 221 and the at least one third trench 23 in the substrate 20 and after forming the first trench filling structure 21 in In the first trench 211 and before forming the second trench filling structure 22 in the second trench 221 , the manufacturing method of the semiconductor device further includes forming a body region 26 and a drift region 27 in the second trench 221 . in the substrate 20 of the active region A2. Alternatively, the body region 26 and the drift region 27 may also be formed before the first trench 211 is formed.

As shown in FIG. 2d and FIG. 2e, the boundary between the body region 26 and the drift region 27 is located below the gate layer 25, the drift region 27 surrounds the second trench 221, the first Three trenches 23 extend from the drift region 27 to the body region 26 .

In addition, after forming the gate layer 25 , the manufacturing method of the semiconductor device further includes forming a source region 261 and a drain region 271 , the source region 261 is located on the gate layer 25 away from the second In the body region 26 of the trench filling structure 22 , the drain region 271 is located in the drift region 27 on the side of the second trench filling structure 22 facing away from the source region 261 . When the source region 261 and the drain region 271 are formed, a body contact region 262 may also be formed in the body region 26 , and the body contact region 262 is located opposite to the source region 261 . In the body region 26 on one side of the gate layer 25 , a first trench filling structure 21 is also spaced between the body contact region 262 and the source region 261 .

As shown in FIG. 2a and FIG. 2f, the manufacturing method of the semiconductor device further includes forming conductive contact plugs 28 on the source region 261, the drain region 271, the body contact region 262 and the gate electrode layer 25, and the conductive contact plug 28 on the gate layer 25 is located above the first trench filling structure 21; and as shown in FIG. 2f and FIG. 2g, the back of the third trench 23 One end of the second trench 221 may extend to the source region 261 , and the bottom of the conductive contact plug 28 is in contact with the source region 261 under the third trench 23 .

In addition, the length of all the third trenches 23 in the edge direction perpendicular to the side of the second trench 221 (ie perpendicular to the second trench filling structure 22 ) is greater than that in the direction parallel to the second trench filling structure 22 . The length in the edge direction of the side of the second trench 221 (ie, perpendicular to the second trench filling structure 22 ), so that the width of the channel region defined by the layout increases more than the channel region. increase in length. Since the portion between the source region 261 and the drain region 271 located under the gate dielectric layer 24 is a channel region, the direction between the source region 261 and the drain region 271 is The length direction of the channel region, the length direction of the channel region is perpendicular to the direction of the edge of the side of the second trench filling structure 22, and the width direction of the channel region is parallel to the direction in which the edge of the one side of the second trench filling structure 22 is located, then the length of all the third trenches 23 in the length direction of the channel region is greater than that in the channel region length in the width direction. For details, please refer to the description in the above-mentioned semiconductor device, which will not be repeated here.

It can be known from the above steps that by forming at least one third trench 23 on one side of the second trench filling structure 22, the at least one third trench 23 extends from the drift region 27 to the body region 26, so that the width of the effective channel region is increased without changing the width of the layout, for example, the part of the body region 26 located under the gate layer 25 is an effective channel region, The width of the effective channel region is increased by 50% to 100%, and the number of inversion carriers in the channel is increased by 50% to 100%, thereby greatly reducing the on-resistance without reducing the breakdown voltage. .

Moreover, if the depth of the second trench 221 is the same as the depth of the third trench 23 and both are smaller than the depth of the first trench 211, the second trench filling structure 22 is located at the The thickness in the substrate 20 is reduced, so that the on-resistance is further reduced.

In addition, each step in the above-mentioned manufacturing method of a semiconductor device is not limited to the above-mentioned formation sequence, and the sequence of each step can be adjusted adaptively.

To sum up, the method for manufacturing a semiconductor device provided by the present invention includes: providing a substrate; forming a first trench, a second trench and at least one third trench in the substrate, the first trench A trench encloses an active region in the substrate, the second trench is formed in the substrate of the active region, and the at least one third trench is formed on a side of the second trench. In the substrate of the active region on the side, the depth of the third trench is smaller than the depth of the first trench; a first trench filling structure is formed in the first trench and a second trench filling structure is formed structure in the second trench; forming a gate dielectric layer on the inner wall of the third trench and the substrate on the periphery of the third trench; and forming a gate layer on the gate dielectric layer and on a portion of the second trench filling structure close to the third trench. The manufacturing method of the semiconductor device of the present invention can reduce the on-resistance without reducing the breakdown voltage.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (15)

1. a semiconductor device, is characterized in that, comprises: a substrate, in which an active region surrounded by a first trench filling structure is formed; A second trench filling structure and at least one third trench on one side of the second trench filling structure are formed in the substrate of the active region, and the bottom wall of the third trench is higher than all the the bottom surface of the first trench filling structure, the lengths of all the third trenches in the edge direction perpendicular to the side of the second trench filling structure are greater than those parallel to the second trenches the length in the edge direction of the side of the filling structure; a gate dielectric layer formed on the inner wall of the third trench and the substrate on the periphery of the third trench; and, a gate layer formed on the gate dielectric layer and on a portion of the second trench filling structure close to the third trench, the third trench facing away from the second trench filling structure One end extends beyond the end of the gate layer facing away from the second trench filling structure. 2 . The semiconductor device of claim 1 , wherein a side of the third trench close to the second trench filling structure exposes the second trench filling structure. 3 . 3. The semiconductor device of claim 1, wherein the semiconductor device comprises at least two third trenches, all of the third trenches along a direction parallel to the second trench filling structure The edge directions of the one side are arranged in sequence. 4. The semiconductor device of claim 1, wherein the bottom surface of the second trench filling structure is flush with the bottom surface of the first trench filling structure; or, the second trench filling structure The bottom surface is flush with the bottom wall of the third groove. 5. The semiconductor device of claim 1, wherein both ends of the second trench filling structure are in contact with sidewalls of the first trench filling structure; The gate dielectric layer and a portion of the second trench filling structure close to the third trench extend to the first trench filling structure. 6. The semiconductor device of claim 1, wherein the semiconductor device further comprises a body region and a drift region formed in a substrate of the active region, the body region and the drift region being in contact with each other. An interface is located below the gate layer, and the drift region surrounds the second trench fill structure, and the third trench extends from the drift region to the body region. 7 . The semiconductor device of claim 6 , wherein the semiconductor device further comprises a source region and a drain region, and the source region is located on the gate layer away from the second trench filling. 8 . In the body region of the structure, the drain region is located in the drift region on the side of the second trench filling structure facing away from the source region. 8 . The semiconductor device of claim 7 , wherein an end of the third trench facing away from the second trench filling structure extends onto the source region. 9 . 9. A method of manufacturing a semiconductor device, comprising: providing a substrate; A first trench, a second trench and at least one third trench are formed in the substrate, the first trench encloses an active area in the substrate, and the second trench is formed In the substrate of the active region, the at least one third trench is formed in the substrate of the active region on one side of the second trench, and the depth of the third trench is smaller than that of the first trench. The depth of a groove, the length of all the third grooves in the edge direction perpendicular to the side of the second groove is greater than that on the side parallel to the second groove length in the direction of the edge; forming a first trench filling structure in the first trench and forming a second trench filling structure in the second trench; forming a gate dielectric layer on the inner wall of the third trench and the substrate on the periphery of the third trench; and, forming a gate layer on the gate dielectric layer and on a portion of the second trench filling structure close to the third trench, and an end of the third trench facing away from the second trench filling structure beyond the end of the gate layer facing away from the second trench filling structure. 10 . The method for manufacturing a semiconductor device according to claim 9 , wherein a side of the third trench close to the second trench communicates with the second trench. 11 . 11. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the first trench, the second trench and the at least one third trench in the substrate include: First, a first trench is formed in the substrate, and then a second trench and at least one third trench are simultaneously formed in the substrate. The depth of the second trench is the same as the depth of the third trench. same depth; Alternatively, a first trench and a second trench are simultaneously formed in the substrate, and then at least one third trench is formed in the substrate, and the depth of the second trench is the same as that of the first trench. The grooves have the same depth. 12. The method of claim 9, wherein the first trench filling structure is formed in the first trench and the second trench filling structure is formed in the first trench The steps in two trenches include: forming an insulating dielectric layer to fill the first trench, the second trench and the third trench; and, The insulating dielectric layer in the third trench is removed to form a first trench filling structure in the first trench and a second trench filling structure in the second trench. 13. The method for manufacturing a semiconductor device according to claim 9, wherein both ends of the second trench communicate with sidewalls of the first trench; The gate dielectric layer and a portion of the second trench filling structure close to the third trench extend to the first trench filling structure. 14. The method for manufacturing a semiconductor device according to claim 9, wherein the method for manufacturing a semiconductor device further comprises forming a body region and a drift region in the substrate of the active region; the body region and the The boundary of the drift region is below the gate layer, the drift region surrounds the second trench, and the third trench extends from the drift region to the body region. 15 . The method of manufacturing a semiconductor device according to claim 14 , wherein the method of manufacturing the semiconductor device further comprises forming a source region and a drain region, the source region being located far from the gate layer. 16 . In the body region of the second trench filling structure, the drain region is located in the drift region on the side of the second trench filling structure facing away from the source region.

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