CN112669705B - Display panel and display device - Google Patents
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- CN112669705B CN112669705B CN202011448922.0A CN202011448922A CN112669705B CN 112669705 B CN112669705 B CN 112669705B CN 202011448922 A CN202011448922 A CN 202011448922A CN 112669705 B CN112669705 B CN 112669705B
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- 239000000463 material Substances 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000011982 device technology Methods 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
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Abstract
The present disclosure relates to the field of semiconductor device technologies, and in particular, to a display panel and a display device, where the display panel includes a plurality of first data lines and a plurality of second data lines, and the first data lines and the second data lines extend along a first side of the display panel to a second side opposite to the first side of the display panel; the length of the second data line is greater than that of the first data line, and at least part of the width of the second data line is greater than that of the first data line. The display panel of the embodiment of the application can improve the load difference of the second data line and the first data line, so that the voltages written into the transistor of the display panel by the first data line and the second data line tend to be approximate, and the display uniformity of the display panel is improved.
Description
Technical Field
The present disclosure relates to semiconductor devices, and particularly to a display panel and a display device.
Background
With the continuous development of display technology, the requirements of users for display devices are higher and higher, and particularly in recent years, the high refresh rate is rapidly increased. However, as the complexity of the wiring of the display panel gradually increases, the display uniformity is affected.
Disclosure of Invention
In view of the above, the present disclosure provides a display panel and a display device, which can improve the load difference of data lines caused by different lengths of the data lines and improve the display uniformity of the display panel.
In order to solve the technical problem, the application adopts a technical scheme that: a display panel comprises a plurality of first data lines and a plurality of second data lines, wherein the first data lines and the second data lines extend along one side of the display panel to the other side opposite to one side of the display panel; the second data line extends for a length greater than that of the first data line, and at least a portion of the second data line has a width greater than that of the first data line.
The plurality of second data lines are distributed on two sides of the first data line; the second data line includes an arc portion extending along a display arc corner region arc of the display panel and a straight portion connecting the pixel unit circuits and extending straight, the straight portion having a width corresponding to a width of the first data line, the arc portion having a width larger than the width of the first data line.
The number of the second data lines on one side of the first data lines is multiple, the second data lines are sequentially arranged, and the width of arc line parts of the second data lines is sequentially reduced along the direction in which the second data lines point to the first data lines.
The display panel further comprises a plurality of power supply signal lines, and the overlapping area of the orthographic projection of the power supply signal lines on the plane where the display panel is located and the orthographic projection of the first data lines on the plane where the display panel is located is equal to the overlapping area of the orthographic projection of the power supply signal lines on the plane where the display panel is located and the orthographic projection of the second data lines on the plane where the display panel is located.
Wherein the power signal line facing the second data line includes a plurality of hole structures, and an orthographic projection of the hole structures on a plane of the display panel overlaps with an orthographic projection of the second data line on the plane of the display panel.
Wherein the hole structure is located at an arc portion position where the power signal line directly faces the second data line.
Wherein, along the direction that the second data line points to the first data line, the distribution density of the hole structures or/and the area of the hole structures are reduced.
Wherein at least a portion of the second data line has a thickness greater than the first data line.
Wherein the material of the first data line comprises aluminum, and the material of the second data line comprises molybdenum.
The embodiment of the application also includes a second technical solution, and a display device includes the display panel and a driving circuit, and the driving circuit is used for driving the display panel.
The beneficial effect of this application is: different from the prior art, the display panel of the application is provided with the second data line, the partial width of the second data line is larger than that of the first data line, so that the width of the partial area of the second data line is larger than that of the first data line, the resistance of the second data line can be reduced, and the condition that the resistance of the second data line is larger due to the fact that the length of the second data line is larger than that of the first data line is improved. The embodiment of the application can enable the resistance of the second data line to be close to or equal to that of the first data line. Therefore, the difference of the resistance loads of the second data line and the first data line is improved, so that the resistance loads of the second data line and the first data line are approximate or equal, the voltages written into the transistors of the display panel by the first data line and the second data line tend to be approximate, and the display uniformity of the display panel is improved.
Drawings
FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of another embodiment of a display panel of the present application;
FIG. 3 isbase:Sub>A partial sectional view taken along line A-A of FIG. 2;
fig. 4 is a block diagram of a display device according to an embodiment of the present application.
10, a first data line; 20. a second data line; 21. a straight line portion; 22. an arc portion; 11. a straight line corresponding portion; 12. an arc line corresponding part; 30. a power signal line; 31. a pore structure; 40. a display area; 50. a non-display area; 100. a display panel; 200. a drive circuit; 60. a substrate; 70. an insulating layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In the prior art, currently, due to the arc angle design, a display device (e.g., a mobile phone) has a difference between a metal trace in an arc angle region and a trace in a straight edge region of a display panel, which causes a difference between a data trace in the arc angle region and a RC loading (resistance-capacitance loading) of the data trace in the straight edge region, and voltages written on two sides and the middle of the display panel during charging a DTFT (driving transistor) are different, which causes a gray scale difference, resulting in displaying Mura or displaying non-uniformity.
As shown in fig. 1, the present application provides a display panel 100, which includes a plurality of first data lines 10 and a plurality of second data lines 20, wherein the first data lines 10 and the second data lines 20 extend along a first side of the display panel 100 to a second side of the display panel 100 opposite to the first side; the second data line 20 extends for a length greater than that of the first data line 10, and at least a portion of the second data line 20 has a width greater than that of the first data line 10.
In the embodiment of the present application, by setting at least a part of the width of the second data line 20 to be greater than the width of the first data line 10, the resistance of the second data line 20 can be reduced, and the situation that the resistance of the second data line 20 is greater due to the fact that the length of the second data line 20 is greater than the length of the first data line 10 is improved. The embodiment of the application can make the resistance of the second data line 20 close to or equal to the resistance of the first data line 10, thereby improving the difference of the resistance loads of the second data line 20 and the first data line 10, making the voltages written by the first data line 10 and the second data line 20 to the transistors of the display panel 100 tend to be similar, and improving the uniformity of the display panel 100.
In the embodiment of the present application, the width of all portions of the second data line 20 is not less than the width of the first data line 10, so that the difference between the resistance of the second data line 20 and the resistance of the first data line 10 can be further reduced.
In the embodiment of the present application, a plurality of second data lines 20 are distributed on two sides of the first data line 10; the second data line 20 includes an arc portion 22 extending along an arc of the arc corner of the display panel 100 and a straight portion 21 extending straight, the width of the straight portion 21 is identical to the width of the first data line 10, and the width of the arc portion 22 is greater than the width of the first data line 10. In the embodiment of the present application, since the second data line 20 is located on two sides of the first data line 10, that is, the second data line 20 is more likely to be corroded, the material of the second data line 20 includes metal molybdenum (Mo), the material of the first data line 10 includes metal aluminum (Al), and the corrosion resistance of molybdenum is greater than that of aluminum, so that the possibility of corrosion of the second data line 20 can be reduced, where the resistivity of metal Mo is greater than that of metal Al, and therefore, by setting at least a portion of the width of the second data line 20 to be greater than that of the first data line 10, the difference between the resistance of the second data line 20 and the resistance of the first data line 10 can be reduced, so that the resistance loads of the second data line 20 and the first data line 10 are similar or equal, thereby improving the voltage written by the first data line 10 and the second data line 20 to the transistor of the display panel 100 tends to be similar, and improving the uniformity of the display panel 100. In other embodiments, the material of the second data line 20 may also be the same as the material of the first data line 10, for example, both are metal Al.
In the embodiment of the present application, the width of the first data line 10 is the overall average width of the first data line 10. In a preferred embodiment of the present application, the first data line 10 is a data line with a uniform width.
In the embodiment of the present application, the resistances of the first data line 10 and the second data line 20 are the same or different within an allowable range, so that the display panel 100 meets the display requirement when displaying at a display refresh frequency of 90 hz or more. In the embodiment of the present application, when the resistances of the first data line 10 and the second data line 20 are the same or the difference is within the allowable range, the influence of the resistive load when the second data line 20 and the first data line 10 give the transistor write voltage can be the same or within the allowable range. In the embodiment of the present application, when the difference between the resistances of the first data line 10 and the second data line 20 is within the allowable range, the display panel 100 may meet the display requirement when displaying at the display refresh frequency of 90 hz or more. The embodiment of the application can improve the display uniformity of the display panel 100 at a high refresh rate. In the embodiment of the present application, as shown in fig. 2 and 3, the display panel 100 further includes a plurality of power signal lines 30 and a plurality of pixel circuit units (not shown), the power signal lines 30 overlapping the first data lines 10 and/or the second data lines 20; some pixel circuit units are connected with some power signal lines 30 and the first data lines 10 respectively, and the rest of the pixel circuit units are connected with the rest of the power signal lines 30 and the second data lines 20 respectively, under the same gray scale driving, the data voltage received by the pixel circuit unit connected with the first data line 10 is the same as or within an allowable range of the data voltage received by the pixel circuit unit connected with the second data line 20. In the embodiment of the present application, the power signal line 30 is in a different layer from the first data line 10 and the second data line 20, and overlaps the first data line 10 and the second data line 20. In the embodiment of the present application, the power signal line 30 is used for writing a driving voltage to the pixel circuit unit, and the first data line 10 and the second data line 20 are used for inputting a data voltage to the pixel circuit unit to control the pixel circuit unit to drive the pixel unit.
In the embodiment of the present application, the first data line 10 and the second data line 20 are in the same layer and are both located on the substrate 60, the power signal line 30 is disposed on a side of the first data line 10 and the second data line 20 away from the substrate 60, and the insulating layer 70 is disposed between a layer where the power signal line 30 is located and a layer where the first data line 10 and the second data line 20 are located.
In the embodiment of the present application, the power signal lines 30 are arranged perpendicular to the second data lines 20 and along the direction in which the first data lines 10 extend. In other embodiments, the power signal line 30 may also be parallel to the first data line 10 and arranged along a direction perpendicular to the first data line 10.
Specifically, in the embodiment of the present application, an overlapping area of an orthogonal projection of the power signal line 30 on the plane where the display panel 100 is located and an orthogonal projection of the first data line 10 on the plane where the display panel 100 is located is equal to an overlapping area of an orthogonal projection of the power signal line 30 on the plane where the display panel 100 is located and an orthogonal projection of the second data line 20 on the plane where the display panel 100 is located. In the embodiment of the present application, the parasitic capacitance formed by the first data line 10 and the power signal line 30 is set to be the same as or similar to the parasitic capacitance formed by the second data line 20 and the power signal line 30, so that the influence of the parasitic capacitance on the first data line 10 and the second data line 20 is the same as or similar to that.
In the embodiment of the present application, the power signal line 30 facing the second data line 20 includes a plurality of hole structures 31, and an orthographic projection of the hole structures 31 on a plane of the display panel 100 overlaps with an orthographic projection of the second data line 20 on a plane of the display panel 100. In the embodiment of the present application, by providing the hole structure 31 on the power signal line 30 facing the second data line 20, the situation of a larger parasitic capacitance formed between the second data line 20 and the power signal line 30 due to a larger overlapping area between the second data line 20 and the power signal line 30 can be improved; so that the capacitance formed by the second data line 20 and the power signal line 30 is similar to or equal to the capacitance formed by the first data line 20 and the power signal line 30. In the embodiment of the present application, the hole structure 31 is disposed on the power signal line 30 instead of the second data line 20, so that the hole structure 31 does not affect the data voltage written by the second data line 20 to the pixel circuit unit.
Specifically, as shown in fig. 1 and 2, in the embodiment of the present application, the hole structure 31 is located at a position where the power signal line 30 faces the arc portion 22 of the second data line 20. A parasitic capacitance exists between the power signal line 30 and the second data line 20. In the embodiment of the present application, by providing the hole structure 31 on the power signal line 30 opposite to the arc portion 22 of the second data line 20, the area of the second data line 20 opposite to the power signal line 30 can be reduced, the parasitic capacitance between the arc portion 22 of the second data line 20 and the power signal line 30 can be reduced, the parasitic capacitance formed by the arc portion 22 of the second data line 20 and the power signal line 30 is the same as or different from the parasitic capacitance formed by the first data line 10 and the power signal line 30 within an allowable range, the difference of the data voltages written to the pixel circuit unit by the arc portion 22 of the second data line 20 and the arc corresponding portion 12 of the first data line 10 is improved, the data voltages written to the pixel circuit unit are approximate or the same, and the uniformity of display of the display panel 100 is improved.
In the embodiment of the present application, the number of the second data lines 20 may be one or more, and the number of the plurality of the second data lines in the embodiment of the present application refers to two or more. As shown in fig. 2, when there are a plurality of second data lines 20, the plurality of second data lines 20 are sequentially arranged, and the arc lengths of the plurality of second data lines 20 are different, so that the arc lengths of the second data lines 20 are different from the parasitic capacitance of the power signal line 30; in the embodiment of the present application, the second data line 20 is disposed in the non-display area 50 of the display panel 100, the first data line 10 is disposed in the display area 40 of the display panel 100, and the length of the arc portion 22 of the plurality of second data lines in the direction toward the first data line 10 decreases sequentially, so that the arc portion 22 of the second data line 20 away from the first data line 10 is longer and the arc portion 22 of the second data line 20 close to the first data line 10 is shorter. For this reason, in an embodiment of the present application, the distribution density of the hole structures 31 is reduced in a direction along which the second data line 20 points to the first data line 10.
Specifically, in the direction in which the second data line 20 points to the first data line 10, the distribution density of the hole structures 31 disposed on the arc portions 22 of the power signal line 30 that face several second data lines 20 is reduced, so as to improve the difference between the parasitic capacitances of the arc portions 22 of the second data lines 20 and the power signal line 30 caused by the different arc lengths of the second data lines 20 at different positions.
In other embodiments, the area of the hole structures 31 disposed on the arc portions 22 of the power signal line 30 directly opposite to the plurality of second data lines 20 in the direction pointing to the first data line 10 along the second data line 20 is reduced, or the distribution density and the area of the hole structures 31 disposed on the arc portions 22 of the power signal line 30 directly opposite to the plurality of second data lines 20 in the direction pointing to the first data line 10 along the second data line 20 are reduced, so that the parasitic capacitance of the arc portions 22 of different second data lines 20 is the same as or similar to that of the power signal line 30, thereby improving the condition that the data voltages written to the pixel circuit units by the second data lines 20 at different positions are different, and improving the uniformity of the display panel 100.
In an embodiment of the present application, as shown in fig. 2, the number of the second data lines 20 located on one side of the first data line 10 is multiple, the multiple second data lines 20 are sequentially arranged, and in a direction pointing to the first data line 10 along the second data lines 20, the widths of arcs of the multiple second data lines 20 are sequentially reduced, so that a resistance difference between the multiple second data lines 20 can be reduced, thereby improving a situation that data voltages written to the pixel circuit units by the second data lines 20 at different positions are different, so that the data voltages written to the pixel circuit units by the second data lines 20 at different positions tend to be similar or the same, and improving uniformity of display of the display panel 100.
In an embodiment of the present application, the thickness of at least a portion of the second data line 20 is greater than the thickness of the first data line 10, so that the resistance difference between the second data line 20 and the first data line 10 can be reduced, the voltages written by the first data line 10 and the second data line 20 to the transistors of the display panel 100 tend to be similar, and the uniformity of the display panel 100 is improved.
Further, in the direction pointing to the first data line 10 along the second data line 20, the thicknesses of the arcs of the plurality of second data lines 20 are sequentially reduced, so that the resistance difference between the second data lines 20 can be reduced, the condition that the data voltages written to the pixel circuit units by the second data lines 20 at different positions are different is improved, the data voltages written to the pixel circuit units by the second data lines 20 at different positions tend to be approximate or the same, and the uniformity of display of the display panel 100 can be improved.
The embodiment of the present application further includes a second technical solution, as shown in fig. 4, a display device includes the display panel 100 and the driving circuit 200, where the driving circuit 200 is used for driving the display panel 100. The display device in the embodiment of the application can improve the difference of the resistance loads of the second data line 20 and the first data line 10, so that the resistance loads of the second data line 20 and the first data line 10 are approximate or equal, the voltages written by the first data line 10 and the second data line 20 to the transistors of the display panel 100 tend to be approximate, and the uniformity of the display panel 100 is improved.
The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.
Claims (4)
1. A display panel, comprising:
a plurality of first data lines and a plurality of second data lines extending along a first side of the display panel to a second side opposite to the first side of the display panel;
the second data line extends to a length greater than that of the first data line, and at least part of the second data line has a width greater than that of the first data line;
the plurality of second data lines are distributed on two sides of the first data line;
the second data line comprises an arc line part and a straight line part, the arc line part extends along an arc angle area arc line of the display panel, the width of the straight line part is consistent with that of the first data line, and the width of the arc line part is larger than that of the first data line;
the number of the second data lines on one side of the first data line is multiple, the multiple second data lines are sequentially arranged, and the widths of arc line parts of the multiple second data lines are sequentially reduced along the direction in which the second data lines point to the first data line;
further comprising: a plurality of power signal lines, wherein the overlapping area of the orthographic projection of the power signal lines on the plane of the display panel and the orthographic projection of the first data lines on the plane of the display panel is equal to the overlapping area of the orthographic projection of the power signal lines on the plane of the display panel and the orthographic projection of the second data lines on the plane of the display panel;
the power supply signal line opposite to the second data line comprises a plurality of hole structures, and the orthographic projection of the hole structures on the plane of the display panel is overlapped with the orthographic projection of the second data line on the plane of the display panel;
the hole structure is positioned at an arc part position where the power signal line is opposite to the second data line;
in a direction in which the second data line points toward the first data line, a distribution density of the hole structures or/and an area of the hole structures decreases.
2. The display panel according to claim 1, wherein a thickness of at least a portion of the second data line is greater than a thickness of the first data line.
3. The display panel according to any one of claims 1 to 2, wherein a material of the first data line comprises aluminum, and a material of the second data line comprises molybdenum.
4. A display device characterized by comprising the display panel according to any one of claims 1 to 3.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011448922.0A CN112669705B (en) | 2020-12-09 | 2020-12-09 | Display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011448922.0A CN112669705B (en) | 2020-12-09 | 2020-12-09 | Display panel and display device |
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| CN112669705A CN112669705A (en) | 2021-04-16 |
| CN112669705B true CN112669705B (en) | 2023-02-10 |
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Citations (2)
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| CN111816118A (en) * | 2020-08-28 | 2020-10-23 | 京东方科技集团股份有限公司 | Display panel and display device |
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| KR100831235B1 (en) * | 2002-06-07 | 2008-05-22 | 삼성전자주식회사 | Thin film transistor substrate |
| US20070216845A1 (en) * | 2006-03-16 | 2007-09-20 | Chia-Te Liao | Uniform impedance conducting lines for a liquid crystal display |
| TWI435295B (en) * | 2011-11-11 | 2014-04-21 | Au Optronics Corp | Pixel structure and field emission device |
| CN103941488A (en) * | 2013-11-01 | 2014-07-23 | 上海中航光电子有限公司 | Fringe-field-switching-type liquid crystal display device, array substrate and manufacturing method of array substrate |
| CN104952888A (en) * | 2015-07-20 | 2015-09-30 | 合肥鑫晟光电科技有限公司 | Peripheral circuit for display baseplate, display baseplate and display device |
| CN108281468B (en) * | 2018-01-23 | 2022-03-15 | 京东方科技集团股份有限公司 | Method for manufacturing a display substrate, display substrate, and display device |
| CN207883275U (en) * | 2018-03-12 | 2018-09-18 | 惠科股份有限公司 | Array substrate |
| CN108922469B (en) * | 2018-06-29 | 2021-04-02 | 武汉天马微电子有限公司 | Display panel and display device |
| CN108807488A (en) * | 2018-06-29 | 2018-11-13 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109584776B (en) * | 2019-01-21 | 2021-12-24 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109817643B (en) * | 2019-01-29 | 2021-02-09 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN210223352U (en) * | 2019-06-11 | 2020-03-31 | 重庆惠科金渝光电科技有限公司 | Display panel and display device |
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| KR20170115164A (en) * | 2016-04-05 | 2017-10-17 | 삼성디스플레이 주식회사 | Display device |
| CN111816118A (en) * | 2020-08-28 | 2020-10-23 | 京东方科技集团股份有限公司 | Display panel and display device |
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