CN112689991B - Initialization synchronization device, initialization synchronization method, and camera - Google Patents

Abstract

The embodiment of the application provides an initialization synchronization device, an initialization synchronization method and a camera, and relates to the technical field of video processing. The initialization synchronization apparatus includes: the device comprises a CPU, one or more controllers and a signal processing circuit, wherein each controller of the one or more controllers is coupled to the CPU and the signal processing circuit, and the signal processing circuit is connected with one or more sensors outside the initialization synchronization device. The CPU may control the signal processing circuit to be in a first state for instructing the first controller to connect with each of the one or more sensors through the signal processing circuit. The first controller may simultaneously transmit the initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit, such that each of the sensors can simultaneously receive the initialization signal and complete the initialization configuration at the same time.

Description

Initialization synchronization device, initialization synchronization method and camera

technical field

The present application relates to the technical field of video processing, and in particular to an initialization synchronization device, an initialization synchronization method, and a camera.

Background technique

The video stitching technology refers to the technology of stitching the video images acquired by several cameras to form a panoramic image, and the video stitching technology is usually applied in the panoramic camera.

A traditional panoramic camera includes: multiple cameras and an SOC (System On Chip, System On Chip), each camera includes an image sensor, and each image sensor is connected to the SOC. Before each camera normally acquires an image, the SOC sends an initialization configuration instruction to the image sensor of each camera, so as to complete the initialization configuration of the image sensor. After the initial configuration of each image sensor is completed, each image sensor transmits the acquired images to the SOC, and the SOC can stitch the images acquired by different image sensors to form a panoramic image.

However, at present, the initial configuration of multiple image sensors by the SOC is not synchronized, resulting in that the images acquired by each image sensor are not synchronized. The SOC stitches the asynchronous images, and the display effect of the obtained panoramic image is poor.

Contents of the invention

The present application provides an initialization synchronization device, an initialization synchronization method, and a camera, capable of synchronously initializing a plurality of sensors, so that the images of each image sensor can be synchronously output.

In a first aspect, an initialization synchronization device is provided, including: a central processing unit CPU, one or more controllers, and a signal processing circuit, wherein each controller in the one or more controllers is coupled to the CPU And the signal processing circuit, the signal processing circuit is connected to one or more sensors outside the initialization synchronization device; the CPU is used to control the signal processing circuit to be in a first state, and the first state is used to indicate the first controller The signal processing circuit is connected to each sensor in the one or more sensors, and the first controller is a controller in the one or more controllers; the first controller is used in the signal processing circuit When in the first state, the initialization signal generated by the CPU is simultaneously sent to each sensor in the one or more sensors through the signal processing circuit.

In this application, when the CPU controls the signal processing circuit to be in the first state, the first controller simultaneously sends the initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit, so that each sensor is The initialization signal can be received at the same time, and the initialization configuration can be completed at the same time, which avoids the asynchronous phenomenon of the images acquired by each sensor. If the initialization synchronization device is integrated on the SOC, when the SOC stitches the images acquired by each sensor to obtain a panoramic image, since the initialization signal can be sent to each image sensor through the signal processing circuit at the same time, the images acquired by each sensor are output synchronously. Therefore, the display effect of the panoramic image obtained by splicing is better.

Optionally, the CPU is also used to control the signal processing circuit to be in a second state, and the second state is used to instruct each of the one or more controllers to be connected to a sensor through the signal processing circuit; Each controller is configured to send the initialization signal or parameter modification signal generated by the CPU to the sensor corresponding to each controller when the signal processing circuit is in the second state, and the parameter modification signal is used for The initialization parameter recorded in the sensor is adjusted, and the initialization parameter is the parameter carried in the initialization signal received by the sensor during the initialization process of each sensor.

In this application, due to manufacturing errors among the sensors, when the same initialization parameters are configured for each sensor, the display quality (such as sharpness or color depth, etc.) of images acquired by each sensor will be different. In order to enable each sensor to obtain images with higher display quality, after completing the initialization configuration of each sensor through the initialization synchronization device, the CPU can control the signal processing circuit to be in the second state, and each controller can convert the parameters generated by the CPU to Modification signals are sent to the respective sensors associated with each controller. The parameter modification signal is used to adjust the initialization parameters recorded in the registers of the sensor, so as to ensure that each sensor can obtain images with high display quality. Since the initialization parameters in each sensor can be adjusted by the corresponding controller, it is more efficient to adjust the initialization parameters in each sensor through the initialization synchronization device after the initialization configuration is completed.

Optionally, the signal processing circuit includes: an output processing circuit and an input processing circuit; when the signal processing circuit is in the first state, the first controller sends the output processing circuit to each of the one or more sensors A sensor sends a signal generated by the CPU; when the signal processing circuit is in the first state, the first controller receives a respective response signal generated by each of the one or more sensors through the input processing circuit.

In this application, the CPU in the initialization synchronization device can send a signal to each sensor in one or more sensors through the output processing circuit, and the CPU can also receive the signal generated by each sensor through the input processing circuit, and the signal is processed by the CPU deal with.

Optionally, the output processing circuit includes: one or more digital selectors, the output end of each digital selector in the one or more digital selectors is connected to the corresponding sensor; when the signal processing circuit is in the first state, the input terminal of each digital selector in the one or more digital selectors is connected to the first controller; when the signal processing circuit is in the second state, the one or more digital selectors The input terminal of each digital selector is connected with the corresponding controller.

Optionally, each digital selector includes a first input port, a second input port, a state selection port and an output port, the first input port of each digital selector is connected to the first controller, each digital The second input port of the selector is connected with the corresponding controller, the state selection port of each digital selector is connected with the CPU, and the output port of each digital selector is connected with the corresponding sensor; wherein, for each digital selector When the state selection port of the digital selector receives the indication signal sent by the CPU to indicate that the signal processing circuit is in the first state, the first input port is in the open state, and the second input port is in the off state. Off state; for each digital selector, when the state selection port of the digital selector receives the indication signal sent by the CPU to indicate that the signal processing circuit is in the second state, the first input port is turned off state, the second input port is in the open state.

Optionally, the input processing circuit includes: an AND gate logic circuit; when the signal processing circuit is in the first state, the AND gate logic circuit receives the respective responses generated by each of the one or more sensors After the signal is processed, it is sent to the first controller; when the signal processing circuit is in the second state, each of the one or more controllers receives a response signal generated by a corresponding sensor.

Optionally, the input processing circuit further includes: a signal selector; each sensor in the one or more sensors is connected to the input terminal of the AND gate logic circuit, and the output terminal of the AND gate logic circuit is connected to the signal selector connected to the first input end of the signal selector, the output end of the signal selector is connected to the first controller, and the first sensor corresponding to the first controller is also connected to the second input end of the signal selector; wherein, when When the signal processing circuit is in the first state, the AND gate logic circuit sends the processed signal to the first controller through the signal selector; when the signal processing circuit is in the second state, the signal selector The response signal generated by the first sensor is sent to the first controller.

Optionally, the initialization synchronization device further includes: a connection bus, each of the one or more controllers is coupled to the CPU and the signal processing circuit through the connection bus, and the connection bus is an integrated circuit I2C connection bus and synchronous serial port SSP connection bus one or more.

Assuming that the connection bus in this application is an I2C connection bus, then: the output processing circuit includes: a first output processing circuit for outputting a data signal, and a second output processing circuit for outputting a clock signal; the first output processing circuit The first input port of each digital selector in the circuit is connected to the data port of the first controller, and the second input port of each digital selector in the first output processing circuit is connected to the data port of the corresponding controller. Port connection, the first input port of each digital selector in the second output processing circuit is connected with the clock port of the first controller, the second input port of each digital selector in the second output processing circuit The port is connected to the clock port of the corresponding controller.

The input processing circuit includes: a first input processing circuit for inputting a data signal, and a second input processing circuit for inputting a clock signal.

Optionally, the initialization synchronization device also includes: a system register, the system register is respectively connected to the CPU and the signal processing circuit; the CPU is used to control the register value of the system register to a first value, so that the signal processing circuit In the first state; the CPU is also used to control the register value of the system register to a second value, so that the signal processing circuit is in the second state, wherein the first value is different from the second value.

Optionally, the initialization synchronization device also includes one or more input and output IO interfaces, and the signal processing circuit is connected to the one or more sensors one by one through one or more IO interfaces; wherein, when the signal processing circuit is in the In the first state, the one or more IO interfaces are all connected to the first controller; when the signal processing circuit is in the second state, each controller is connected to the corresponding sensor through an IO interface.

Optionally, the CPU is further configured to: before performing initialization processing on each sensor, send a reset instruction to each sensor, so as to clear the initialization parameters in each sensor.

Optionally, the CPU is also used to: receive the image information obtained by each sensor after initializing each sensor; judge whether the image information obtained by any two sensors is synchronized according to the synchronization signal in the image information; Compensation adjustments are made for sensors whose acquired image information is out of sync. Therefore, the images acquired by each sensor 200 are synchronized, thereby improving the display effect of the panoramic image formed by subsequent splicing.

In a second aspect, an initialization synchronization method is provided, which is applied to an initialization synchronization device, and the initialization synchronization device includes: a CPU, one or more controllers, and a signal processing circuit, wherein each of the one or more controllers Each controller is coupled to the CPU and the signal processing circuit, the signal processing circuit is connected to one or more sensors outside the initialization synchronization device, the method includes: the CPU controls the signal processing circuit to be in a first state, the second A state is used to indicate that the first controller is connected to each sensor in the one or more sensors through the signal processing circuit, and the first controller is a controller in the one or more controllers; the first controller The controller sends the initialization signal generated by the CPU to each sensor in the one or more sensors through the signal processing circuit.

Optionally, the method further includes: the CPU controls the signal processing circuit to be in a second state, and the second state is used to indicate that each of the one or more controllers is connected to a sensor through the signal processing circuit ; each controller sends the initialization signal or parameter modification signal generated by the CPU to the sensor corresponding to each controller, and the parameter modification signal is used to adjust the initialization parameter recorded in the sensor, and the initialization parameter is During the initialization process of each sensor, the parameters carried in the initialization signal received by the sensor.

Optionally, the signal processing circuit includes: an output processing circuit and an input processing circuit; after the CPU controls the signal processing circuit to be in the first state, the method further includes: the first controller sends the output processing circuit to the one Each sensor of the or plurality of sensors transmits the signal generated by the CPU; the first controller receives a response signal generated by each sensor of the one or more sensors through the input processing circuit.

Optionally, the output processing circuit includes: one or more digital selectors, the output end of each digital selector in the one or more digital selectors is connected to the corresponding sensor; the first controller processes the a circuit sending the CPU-generated signal to each of the one or more sensors, comprising: each of the one or more digital selectors controlling a respective input terminal connected to the first controller, Make the first controller send the signal generated by the CPU to the one or more sensors through the one or more digital selectors; after the CPU controls the signal processing circuit to be in the second state, the method further includes: the one Each digital selector in the or multiple digital selectors controls its respective input terminal to be connected to a corresponding controller.

Optionally, the input processing circuit includes: an AND gate logic circuit; the first controller receives the respective response signals generated by each of the one or more sensors through the input processing circuit, including: the first controller receiving a processed signal of the response signal generated by each sensor in the one or more sensors received by the AND gate logic circuit; after the CPU controls the signal processing circuit to be in the second state, the method further includes : Each of the one or more controllers receives a corresponding sensor-generated response signal.

Optionally, the input processing circuit further includes: a signal selector, each of the one or more sensors is connected to the input terminal of the AND gate logic circuit, and the output terminal of the AND gate logic circuit is connected to the signal selector connected to the first input end of the signal selector, the output end of the signal selector is connected to the first controller, and the first sensor corresponding to the first controller is also connected to the second input end of the signal selector; the first The controller receives the processed response signal generated by each of the one or more sensors to be received by the AND gate logic circuit, including: the first controller receives the processed signal by the AND gate logic circuit the signal sent by the signal selector; after the CPU controls the signal processing circuit to be in the second state, the method further includes: the signal selector sends the response signal generated by the first sensor to the first controller .

Optionally, the initialization synchronization device further includes: a system register, the system register is respectively connected to the CPU and the signal processing circuit, and the CPU controls the signal processing circuit to be in the first state, including: the CPU controls the register of the system register The value is the first value, so that the signal processing circuit is in the first state; the CPU controls the signal processing circuit to be in the second state, including: the CPU controls the register value of the system register to be the second value, so that the signal processing circuit The circuit is in a second state, wherein the first value and the second value are different.

Optionally, the initialization synchronization device also includes one or more input and output IO interfaces, and the signal processing circuit is connected to the one or more sensors one by one through one or more IO interfaces; when the CPU controls the signal processing circuit to After the first state, the method also includes: the signal processing circuit controls the one or more IO interfaces to be connected to the first controller; after the CPU controls the signal processing circuit to be in the second state, the method also includes: The signal processing circuit controls each controller to be connected to a corresponding sensor through an IO interface.

Optionally, the method further includes: before performing initialization processing on each sensor, the CPU sends a reset instruction to each sensor, so as to clear initialization parameters in each sensor.

Optionally, the method further includes: after each sensor is initialized, the CPU receives the image information acquired by each sensor; the CPU judges the image information acquired by any two sensors according to the synchronization signal in the image information Whether it is synchronous or not; the CPU compensates and adjusts the sensor whose acquired image information is not synchronous.

It should be noted that, for the principle of the initialization synchronization method in the second aspect, reference may be made to the corresponding part in the initialization synchronization device in the first aspect, which will not be repeated in this application.

In a third aspect, a camera is provided, including: a plurality of cameras and a system-on-chip SOC, the SOC includes: any one of the initialization synchronization devices in the first aspect, each camera includes a sensor, and each sensor is connected to the initialization Synchronous device connection.

Description of drawings

Fig. 1 is a block diagram of a panoramic camera provided by the related art;

Fig. 2 is a block diagram of another panoramic camera provided by related technologies;

FIG. 3 is a block diagram of an initialization synchronization device provided in an embodiment of the present application;

FIG. 4 is a block diagram of another initialization synchronization device provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of an output processing circuit provided by an embodiment of the present application;

Fig. 6 is a schematic diagram of signal transmission in the output processing circuit shown in Fig. 5;

FIG. 7 is a schematic structural diagram of an input processing circuit provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of signal transmission in the output processing circuit shown in FIG. 7 .

By means of the above drawings, specific embodiments of the present application have been shown, which will be described in more detail hereinafter. These drawings and text descriptions are not intended to limit the scope of the concept of the application in any way, but to illustrate the concept of the application for those skilled in the art by referring to specific embodiments.

detailed description

The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

Please refer to FIG. 1 . FIG. 1 is a block diagram of a panoramic camera provided in the related art. The panoramic camera includes: an SOC 01 and multiple cameras (not shown in FIG. 1 ), and each camera may include an image sensor 02 . The SOC 01 is internally provided with an I2C (Inter-Integrated Circuit, integrated circuit) bus 011 and a plurality of INCK (InputClock, operating clock) circuits 012, each image sensor 02 is connected to the I2C bus 011, and the plurality of INCK circuits 012 is connected to a plurality of image sensors 02 in one-to-one correspondence.

When the panoramic camera acquires panoramic images, SOC 01 needs to send initialization configuration instructions to all image sensors 02 through the I2C bus 011 and multiple INCK circuits 012, and each image sensor 02 performs initialization configuration after receiving the initialization configuration instructions. After the image sensor 02 is initialized and configured, it can acquire images and send the acquired images to the SOC 01, so that the SOC 01 stitches the images acquired by different image sensors 02 to obtain a panoramic image.

However, when all the image sensors 02 are connected through an I2C bus 011, the SOC 01 needs to control multiple image sensors 02 one by one for initial configuration, that is, after an image sensor is initialized and configured, the SOC 01 can control the An image sensor is initially configured. Normally, after the initial configuration of the image sensor 02 is completed, the image sensor 02 will immediately send the acquired image to the SOC 01, and the SOC 01 cannot control multiple image sensors 01 to complete the initialization configuration at the same time, so each image sensor 02 The acquired images are not synchronized, and the SOC01 stitches the asynchronous images, and the display effect of the obtained panoramic image is poor.

Please refer to Fig. 2, Fig. 2 is the block diagram of another kind of panoramic camera provided by the related art, the SOC 01 in this panoramic camera is provided with a plurality of I2C buses 011 and a plurality of INCK circuits 012, and the plurality of I2C buses 011 and multiple The image sensors 02 are connected in one-to-one correspondence, and the plurality of INCK circuits 012 are connected in one-to-one correspondence with the plurality of image sensors 02 . At this time, SOC 01 does not need to control multiple image sensors 02 to perform initialization configuration one by one. Although the multiple image sensors 02 can perform initialization configuration at the same time, due to the sequential execution of software, SOC 01 needs to perform initialization configurations one by one through the multiple I2C buses 011. Send an initialization image command to each image sensor 02, the time for each image sensor 02 to complete initialization will still be delayed sequentially, and the SOC 01 still cannot control multiple image sensors 01 to complete the initialization configuration at the same time, resulting in the information obtained by each image sensor 02 The images are not synchronized, and the SOC 01 stitches the asynchronous images, and the display effect of the obtained panoramic images is poor.

Please refer to FIG. 3. FIG. 3 is a block diagram of an initialization synchronization device provided in an embodiment of the present application. The initialization synchronization device 100 may include:

Central Processing Unit (Central Processing Unit, CPU) 10, one or more controllers 20 and signal processing circuit 30, wherein, each controller 20 in the one or more controllers 20 is all coupled to CPU 10 and signal processing circuit A circuit 30, the signal processing circuit 30 is connected with one or more sensors 200 outside the initialization synchronization device. Exemplarily, the sensor 200 in the embodiment of the present application may be an image sensor.

The CPU 10 is used to control the signal processing circuit 30 to be in a first state, the first state is used to instruct the first controller 20a to be connected to each sensor 200 in the one or more sensors 200 through the signal processing circuit 30, the first state A controller 20a is one of the one or more controllers 20 .

The first controller 20a is configured to simultaneously send the initialization signal generated by the CPU 10 to each of the one or more sensors 200 through the signal processing circuit 30 when the signal processing circuit 30 is in the first state.

Exemplarily, the signal processing circuit 30 has multiple input and output interfaces, wherein the multiple input and output interfaces are connected to the sensors one by one. When the signal processing circuit 30 is in the first state, the multiple input and output interfaces of the signal processing circuit 30 are all Connected to the above-mentioned first controller 20a, when the CPU 10 generates an initialization signal, the initialization signal is sent to each sensor 200 through the first controller 20a through a plurality of input and output interfaces at the same time, and each sensor 200 receives the first controller After the initialization signal sent by 20a, the initialization parameters carried in the initialization signal (for example, image resolution, refresh rate, exposure time and gain, etc.) can be written into the register in the sensor 200, after the initialization parameter is written , the initial configuration of the sensor 200 can be completed. Since the first controller 20a sends an initialization signal to each sensor 200 in one or more sensors 200 at the same time through the signal processing circuit 30, each sensor 200 can receive the initialization signal at the same time, and complete the initialization configuration at the same time, This prevents the images acquired by the sensors 200 from being out of sync. If the initialization synchronization device 100 is integrated on the SOC, when the SOC stitches the images acquired by each sensor 200 to obtain a panoramic image, since the initialization signal can be sent to each image sensor 200 through the signal processing circuit 30 at the same time, each sensor 200 can obtain The images are output synchronously, so the display effect of the stitched panoramic images is better.

Further, the CPU 10 is also used to control the signal processing circuit 30 to be in the second state, and the second state is used to indicate that each controller 20 in the one or more controllers 20 communicates with a sensor 200 through the signal processing circuit 30 connected. Each controller 20 is configured to send the initialization signal generated by the CPU 10 to the sensor 200 corresponding to each controller 20 when the signal processing circuit 30 is in the second state.

For example, when the signal processing circuit 30 is in the second state, each sensor 200 is connected to the CPU 10 through its own controller 20 , and the CPU 10 can control each sensor 200 independently.

In the embodiment of the present application, after the initialization synchronization device 100 completes the initial configuration of each sensor 200, each sensor 200 can acquire an image, but due to the manufacturing error between each sensor 200, when each sensor 200 is configured with the same When the parameters are initialized, the display quality (such as sharpness or color depth, etc.) of the images acquired by each sensor 200 will be different. In order to enable each sensor 200 to obtain images with higher display quality, after the initial configuration of each sensor 200 is completed through the initialization synchronization device 100, the CPU 10 controls the signal processing circuit 30 to be in the second state, and each controller 20 can The parameter modification signal generated by the CPU 10 is sent to the sensor 200 respectively corresponding to each controller 20 . The parameter modification signal is used to adjust the initialization parameters recorded in the registers of the sensors 200, so as to ensure that each sensor 200 can obtain images with high display quality. Since the initialization parameters in each sensor 200 can be adjusted by the corresponding controller 20 , it is more efficient to adjust the initialization parameters in each sensor 200 through the initialization synchronization device 100 after the initialization configuration is completed.

In an optional implementation manner, as shown in FIG. 4 , FIG. 4 is a block diagram of another initialization synchronization device provided in an embodiment of the present application. The initialization synchronization device 100 may further include: a system register 40 , the system register 40 is connected to the CPU 10 and the signal processing circuit 30 respectively. The CPU 10 is used to control the register value of the system register 40 to a first value, so that the signal processing circuit 30 is in the first state; the CPU 10 is also used to control the register value of the system register 40 to a second value, so that the signal Processing circuit 30 is in a second state. Wherein, the first value is different from the second value. For example, the first value may be 1, and the second value may be 0. It should be noted that, in FIG. 4, the CPU 10 controls the register value of the system register 40 to control the signal processing circuit 30 to be in the first state or the second state. In another optional implementation manner, the CPU 10 may The direct control signal processing circuit 30 is in the first state or the second state, which is not specifically limited in this embodiment of the present application.

Optionally, the initialization synchronization device 100 may further include: one or more input/output (Input/Output, IO) interfaces, and the signal processing circuit 30 is connected to one or more sensors 200 one by one through one or more IO interfaces. It should be noted that FIG. 4 only schematically shows a schematic diagram of an IO general interface 50 , and the IO general interface 50 includes one or more IO interfaces connected to one or more sensors 200 one by one. In the embodiment of the present application, when the signal processing circuit 30 is in the first state, one or more IO interfaces are connected to the first controller 20a, so that the first controller 20a and each of the one or more sensors 200 Sensor connection; when the signal processing circuit 30 is in the second state, each controller 20 is connected to the corresponding sensor 200 through an IO interface, so that each control 20 in one or more controllers 20 is connected to the corresponding sensor 200 connect.

In the embodiment of the present application, the initialization synchronization device 100 further includes: a connection bus 60 . Each controller 20 in the one or more controllers 20 is coupled to the CPU 10 and the signal processing circuit 30 through the connection bus 60, and the signal processing circuit 30 and the IO general interface 50 can also be connected through the connection bus 60 . Optionally, the connection bus 60 may be one or more of an integrated circuit (Inter-Integrated Circuit, I2C) connection bus and a synchronous serial port (Synchronous Serlal Port, SSP) connection bus. It should be noted that the I2C connection bus may include data traces for transmitting data signals, and clock traces for transmitting clock signals; the SSP connection bus may include three types of signal traces: Input and output data traces (also known as bidirectional data traces), clock traces for transmitting clock signals, and chip select traces for transmitting chip select signals; the SSP connection bus can also include four types of signal traces : Input data traces for transmitting data signals, output data traces for transmitting data signals, clock traces for transmitting clock signals, and chip select traces for transmitting chip select signals. It should be understood that the embodiment of the present application divides the initialization synchronization device from a functional point of view, and there may be other division methods in actual implementation, for example, multiple modules may be combined or integrated into another system. The mutual coupling of various modules may be realized through some interfaces, and these interfaces are usually electrical communication interfaces, but it is not excluded that they may be mechanical interfaces or other forms of interfaces. Thus, modules described as separate components may or may not be physically separate, and may be located at one location or distributed to different locations on the same or different devices. In various embodiments of the present application, coupling refers to interconnection in a specific manner, including direct connection or indirect connection through other devices.

Optionally, as shown in FIG. 4 , the signal processing circuit 30 in the initialization synchronization device 100 includes: an output processing circuit 31 and an input processing circuit 32 .

When the signal processing circuit 30 is in the first state, the first controller 20a sends the signal generated by the CPU 10 to each sensor 200 in the one or more sensors 200 through the output processing circuit 31, for example, the signal generated by the CPU 10 may be is an initialization signal; the first controller 20a receives the response signal that each sensor 200 in the one or more sensors 200 will generate respectively through the input processing circuit 32, for example, the response signal of each sensor 200 is the sensor 200 in An initialization response signal generated after an initialization signal is received.

When the signal processing circuit 30 is in the second state, each controller 20 in the one or more controllers 20 sends the signal generated by the CPU 10 to the corresponding sensor 200 through the output processing circuit 31, for example, the signal generated by the CPU 10 The signal may be modified for a parameter; each controller 20 in the one or more controllers 20 receives a corresponding sensor 200 response signal through the input processing circuit 32, for example, the response signal of each sensor 20 is that the sensor 200 receives The parameter modification response signal generated after the parameter modification signal.

It should be noted that, in the embodiment of the present application, after receiving the response signal sent by the sensor 200, each controller 20 will send the response signal to the CPU 10, and the CPU 10 will perform signal processing.

Please refer to FIG. 5 , which is a schematic structural diagram of an output processing circuit 31 provided in an embodiment of the present application. The output processing circuit includes: one or more digital selectors 311 . In the embodiment of the present application, at least one digital selector 311 among the one or more digital selectors 311 corresponds to a sensor and a controller. The output terminals of the one or more digital selectors 311 are connected with corresponding sensors.

For example, as shown in FIG. 6 , FIG. 6 is a schematic diagram of signal transmission in the output processing circuit 31 shown in FIG. 5 . When the signal processing circuit is in the first state, the signal transmission direction in the output processing circuit 31 is the direction of the solid line in Fig. 6, the input port of each digital selector 311 in the one or more digital selectors 311 Be connected with the first controller, so that the first controller can simultaneously send the signal generated by the CPU to each sensor in one or more sensors; when the signal processing circuit is in the second state, the signal transmission in the output processing circuit 31 The direction is the direction of the dotted line in Fig. 6, the input end of each digital selector 311 in the one or more digital selectors 311 is connected with the corresponding controller, so that each of the one or more controllers controls The sensor can send the signal generated by the CPU to the corresponding sensor.

Optionally, each digital selector 311 includes: a first input port T1, a second input port T2, a state selection port S and an output port Z. The first input port T1 of each digital selector 311 is connected with the first controller; the second input port T2 of each digital selector 311 is connected with the corresponding controller; the state selection port S of each digital selector 311 Connect with CPU, in an optional situation, the state selection port S of each digital selector 311 is connected with CPU through system control register, namely state selection port S is connected with system control register, and system control register is connected with CPU ; The output port Z of each digital selector 311 is connected with the corresponding sensor.

For each digital selector 311, when the state selection port S of the digital selector 311 receives the indication signal sent by the CPU to indicate that the signal processing circuit is in the first state, the first input port T1 of the digital selector 311 In the on state, the second input port T2 of the digital selector is in the off state, so that each of the one or more sensors is connected to the first controller through the output processing circuit 31 .

For each digital selector 311, when the state selection port S of the digital selector 311 receives the indication signal sent by the CPU to indicate that the signal processing circuit is in the second state, the first input port T1 of the digital selector 311 In the OFF state, the second input port T2 of the digital selector is in the ON state, so that each of the one or more sensors is connected to the corresponding controller through the output processing circuit 31 .

Assuming that the connection bus in the initialization synchronization device in the embodiment of the present application is an I2C connection bus, the output processing circuit 31 may include: a first output processing circuit 31a for outputting data signals, and a second output processing circuit 31a for outputting clock signals Output processing circuit 31b. Wherein, the data wires in the I2C connection bus are connected to the first output processing circuit 31a, and the clock wires in the I2C connection bus are connected to the second output processing circuit 31b. Both the first output processing circuit 31 a and the second output processing circuit 31 b may include: one or more signal selectors 311 . The first input terminal T1 of each digital selector 311 in the first output processing circuit 31a is connected to the data port of the first controller, and the first input port T1 of each digital selector 311 in the first output processing circuit 31a The two input ports T2 are connected with the data port of the corresponding controller; the first input port T1 of each digital selector 311 in the second output processing circuit 31b is connected with the clock port of the first controller, and the second output The second input port T2 of each digital selector 311 in the processing circuit 31b is connected to the clock port of the corresponding controller.

Please refer to FIG. 7 , which is a schematic structural diagram of an input processing circuit 32 provided in an embodiment of the present application. The input processing circuit 32 may include: an AND gate logic circuit 321 . For example, as shown in FIG. 8 , FIG. 8 is a schematic diagram of signal transmission in the output processing circuit 31 shown in FIG. 7 . When the signal processing circuit is in the first state, the signal transmission direction in the input processing circuit 32 is the direction of the solid line in FIG. 321 is processed and sent to the first controller; when the signal processing circuit is in the second state, the signal transmission direction in the input processing circuit 32 is the direction of the dotted line in Figure 8, and each controller in one or more controllers A response signal generated by a corresponding sensor is received.

Optionally, the input processing circuit 32 may further include: a digital selector 322 . In the embodiment of the present application, each of the one or more sensors is connected to the input end of the AND gate logic circuit 321; the output end of the AND gate logic circuit 321 is connected to the first input end of the signal selector 322; The output end of the signal selector 322 is connected to the first controller; the first sensor corresponding to the first controller is also connected to the second input end of the signal selector 322 . As shown in Figure 8, when the signal processing circuit is in the first state, the AND gate logic circuit 322 sends the processed signal to the first controller through the signal selector 322; when the signal processing circuit is in the second state, the signal selection The controller 322 sends the response signal generated by the first sensor to the first controller.

Assuming that the connection bus in the initialization synchronization device in the embodiment of the present application is an I2C connection bus, the input processing circuit 32 may include: a first input processing circuit 32a for inputting data signals, and a second input processing circuit 32a for inputting clock signals Input processing circuit 32b. Wherein, the data wires in the I2C connection bus are connected to the first input processing circuit 32a, and the clock wires in the I2C connection bus are connected to the second input processing circuit 32b. Both the first input processing circuit 32a and the second input processing circuit 32b include: an AND gate logic circuit 321 and a signal selector 322, and the connection mode between the AND gate logic circuit 321 and the signal selector 322 is in the first input processing circuit 32a and the second input processing circuit 32b are identical. The following embodiment schematically illustrates the specific connection mode between the AND gate logic circuit 321 and the signal selector 322:

Exemplarily, the AND logic circuit 321 has an output port Z and one or more input ports (T0, T1, T2, . . . , Tn) corresponding to one or more sensors, and the digital selector 322 has a first An input port T1, a second input port T2, a state selection port S and an output port Z. Each sensor in the one or more sensors is connected to the corresponding input port in the AND gate logic circuit 321; the output port Z of the AND gate logic circuit 321 is connected to the first input port T1 of the digital selector; the one or more The first sensor in the three sensors is connected with the second input port T2 of the digital selector 322; the output port Z of the digital selector 322 is connected with the first controller; each of the one or more sensors except the first sensor The sensor is directly connected to the corresponding controller; the state selection port S of the digital selector 322 is connected to the CPU, for example, the state selection port S of the digital selector 322 is connected to the system control register, and the system control register needs to be connected to the CPU.

When the state selection port of the digital selector 322 receives the indication signal sent by the CPU to indicate that the signal processing circuit is in the first state, the first input port T1 of the digital selector 322 is in an open state, and the digital selector 322 The second input port T2 is in an off state. At this time, the response signals generated by each of the one or more sensors are processed by the AND gate logic circuit 321 and sent to the first sensor. It should be noted that, when the signal processing circuit is in the first state, the CPU may control the interruption of the connection between it and each of the one or more controllers except the first controller, at this time, one or more Although the response signals generated by each of the multiple sensors except the first sensor can be sent to the corresponding controllers, these controllers will not send the received response signals to the CPU, so the CPU can only receive When the signal sent by the first controller is processed by the AND gate logic circuit, the CPU only needs to process the signal sent by the first controller.

When the state selection port of the digital selector 322 receives the indication signal sent by the CPU to indicate that the signal processing circuit is in the second state, the second input port T2 of the digital selector 322 is in an open state, and the digital selector 322 The first input port T1 is in an off state. At this time, the response signal generated by the first sensor can be sent to the first controller through the digital selector 322, and the response signal generated by each sensor in one or more sensors except the first sensor is directly sent to the corresponding controller. device. It should be noted that when the signal processing circuit is in the second state, the CPU needs to control the normal connection between it and each of the one or more controllers, and at this time, each of the one or more sensors The generated response signals are sent to the CPU through their corresponding controllers, so that the CPU can process the signals sent by each controller.

In an optional implementation, the output port of the digital selector 322 in the first input processing circuit 32a is connected to the data port of the first controller; the output port of the digital selector 322 in the second input processing circuit 32b is connected to the first controller. A controller clock port connection. Each of the one or more sensors except the first sensor is respectively connected to the data port and the clock port of the corresponding controller.

In the embodiment of the present application, as shown in FIG. 3 or FIG. 4 , the CPU 10 is further configured to: before each sensor 200 is initialized, send a reset command to each sensor 200 to clear the The registers store the initialization parameters. It should be noted that when the CPU 10 sends a reset command to each sensor 200, the CPU 10 may control the signal processing circuit 30 to be in the first state, or may control the signal processing circuit 30 to be in the second state, which is not discussed in the embodiment of the present application. Do limited.

In an optional implementation, since there are some manufacturing errors inside each sensor 200, after the initialization synchronization device 100 initializes each sensor 200, each sensor 200 may acquire the Usually, if the time difference between the two sensors 200 transmitting the captured images to the initialization synchronization device 100 is within 0.15 microseconds, it can be considered that the image information acquired by the two sensors is synchronized . In the embodiment of the present application, in order to further improve the display effect of the subsequently synthesized spliced images, the CPU 10 is also configured to: receive the image information acquired by each sensor 200 after performing initialization processing 30 on each sensor 200; The synchronization signal in the image information is used to judge whether the image information acquired by any two sensors 200 is synchronized; to compensate and adjust the sensor 200 whose acquired image information is not synchronized. Therefore, the images acquired by each sensor 200 are synchronized, thereby improving the display effect of the panoramic image formed by subsequent splicing.

In summary, the initialization synchronization device provided by the embodiment of the present application includes: a CPU, one or more controllers, and a signal processing circuit. When the CPU controls the signal processing circuit to be in the first state, the first controller simultaneously sends the initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit, so that each sensor can simultaneously receive the initialization signal. signal, and complete the initialization configuration at the same time, avoiding the asynchronous phenomenon of the images acquired by each sensor. If the initialization synchronization device is integrated on the SOC, when the SOC stitches the images acquired by each sensor to obtain a panoramic image, since the initialization signal can be sent to each image sensor through the signal processing circuit at the same time, the images acquired by each sensor are output synchronously. Therefore, the display effect of the panoramic image obtained by splicing is better. Further, the CPU can also control the signal processing circuit to be in the second state, and each controller can send the parameter modification signal generated by the CPU to the respective sensor corresponding to each controller, and the parameter modification signal is used to modify the register of the sensor Adjust the initialization parameters recorded in , to ensure that each sensor can obtain images with high display quality. Since the initialization parameters in each sensor can be adjusted by the corresponding controller, it is more efficient to adjust the initialization parameters in each sensor through the initialization synchronization device after the initialization configuration is completed.

The embodiment of the present application also provides an initialization synchronization method, which is applied to the initialization synchronization device shown in Figure 3 or 4, and the method may include:

Step A1, the CPU controls the signal processing circuit to be in the first state, the first state is used to indicate that the first controller is connected to each sensor in one or more sensors through the signal processing circuit, and the first controller is one or more controllers A controller in .

Step B1, the first controller sends the initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit.

Optionally, the initialization synchronization method may also include:

Step A2, the CPU controls the signal processing circuit to be in a second state, and the second state is used to indicate that each of the one or more controllers is connected to a sensor through the signal processing circuit;

Step B2, each controller sends the initialization signal or parameter modification signal generated by the CPU to the sensor corresponding to each controller.

Optionally, after the CPU controls the signal processing circuit to be in the first state, the initialization synchronization method may further include:

Step A3, the first controller sends the signal generated by the CPU to each of the one or more sensors through the output processing circuit.

Step B3, the first controller receives the respective response signals generated by each of the one or more sensors through the input processing circuit.

Optionally, the above step A3 may include: each of the one or more digital selectors controls its respective input terminal to be connected to the first controller, so that the first controller passes through one or more digital selectors Sends a CPU-generated signal to one or more sensors.

After the CPU controls the signal processing circuit to be in the second state, the initialization synchronization method may further include: each digital selector among the one or more digital selectors controls its respective input terminal to be connected to a corresponding controller.

Optionally, the above step B3 may include: the first controller receives the signal after processing the response signal generated by each of the one or more sensors to be received by the AND gate logic circuit.

After the CPU controls the signal processing circuit to be in the second state, the initialization synchronization method may further include: each of the one or more controllers receives a response signal generated by a corresponding sensor.

Optionally, the above step B3 specifically includes: the first controller receives the signal sent by the AND gate logic circuit through the signal selector after processing the signal.

After the CPU controls the signal processing circuit to be in the second state, the initialization synchronization method may further include: the signal selector sends the response signal generated by the first sensor to the first controller.

Optionally, after the CPU controls the signal processing circuit to be in the first state, the initialization synchronization method may further include: the signal processing circuit controls one or more IO interfaces to be connected to the first controller;

After the CPU controls the signal processing circuit to be in the second state, the initialization synchronization method may further include: the signal processing circuit controls each controller to be connected to a corresponding sensor through an IO interface.

Optionally, the CPU controlling the signal processing circuit to be in the first state in the above step A1 may include: the CPU controlling the register value of the system register to be the first value, so that the signal processing circuit is in the first state.

Optionally, the CPU controlling the signal processing circuit in the above step A2 to be in the second state may include: the register value of the CPU controlling the system register is the second value, so that the signal processing circuit is in the second state, wherein the first value and The second value is different.

Optionally, the initialization synchronization method may further include: before performing initialization processing on each sensor, the CPU sends a reset instruction to each sensor, so as to clear the initialization parameters in each sensor.

Optionally, the initialization synchronization method may also include:

Step A4, after each sensor is initialized, the CPU receives the image information acquired by each sensor.

Step B4, the CPU judges whether the image information acquired by any two sensors is synchronized according to the synchronization signal in the image information.

Step C4, the CPU compensates and adjusts the sensors whose acquired image information is not synchronized.

It should be noted that, for the principle of the above initialization synchronization method, reference may be made to the corresponding part in the aforementioned embodiment of the initialization synchronization device, which will not be repeated here.

The embodiment of the present application also provides a camera, the camera can be a panoramic camera, the camera can include: a plurality of cameras and an SOC, the SOC includes: the initialization synchronization device shown in Figure 3 or 4, each camera includes a sensor , the sensor may be an image sensor, and each sensor is connected to the initialization synchronization device.

The above descriptions are only preferred embodiments of the application, and are not intended to limit the application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the application shall be included in the protection of the application. within range.

Claims (21)

1. A synchronization device for initialization, comprising: a central processing unit CPU, one or more controllers and a signal processing circuit, wherein each controller in the one or more controllers is coupled to the The CPU and the signal processing circuit, the signal processing circuit is connected to one or more sensors outside the initialization synchronization device; The CPU is configured to control the signal processing circuit to be in a first state, and the first state is used to instruct the first controller to be connected to each sensor in the one or more sensors through the signal processing circuit, so said first controller is a controller of said one or more controllers; The first controller is configured to simultaneously send the initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit when the signal processing circuit is in the first state a sensor; The CPU is further configured to control the signal processing circuit to be in a second state, and the second state is used to indicate that each of the one or more controllers is connected to a sensor through the signal processing circuit ; Each controller is configured to send the initialization signal or parameter modification signal generated by the CPU to a sensor corresponding to each controller when the signal processing circuit is in the second state, the The parameter modification signal is used to adjust the initialization parameter recorded in the sensor, and the initialization parameter is the parameter carried in the initialization signal received by the sensor during the initialization process of each sensor. 2. The initialization synchronization device according to claim 1, wherein the signal processing circuit comprises: an output processing circuit and an input processing circuit; when the signal processing circuit is in the first state, the first controller sends the CPU-generated signal to each of the one or more sensors via the output processing circuit; When the signal processing circuit is in the first state, the first controller receives, through the input processing circuit, a respective generated response signal of each of the one or more sensors. 3. The initialization synchronization device according to claim 2, characterized in that, The output processing circuit includes: one or more digital selectors, the output end of each digital selector in the one or more digital selectors is connected to the corresponding sensor; When the signal processing circuit is in the first state, the input terminal of each digital selector in the one or more digital selectors is connected to the first controller; When the signal processing circuit is in the second state, an input terminal of each digital selector in the one or more digital selectors is connected to a corresponding controller. 4. The initialization synchronization device according to claim 3, wherein: Each of the digital selectors includes a first input port, a second input port, a state selection port and an output port, the first input port of each of the digital selectors is connected to the first controller, each The second input port of the digital selector is connected to the corresponding controller, the state selection port of each digital selector is connected to the CPU, and the output port of each digital selector is connected to the corresponding sensor ; Wherein, for each of the digital selectors, when the state selection port of the digital selector receives an indication signal sent by the CPU to indicate that the signal processing circuit is in the first state, the second One input port is in an open state, and the second input port is in an off state; For each of the digital selectors, when the state selection port of the digital selector receives an indication signal sent by the CPU to indicate that the signal processing circuit is in the second state, the first input The port is in an off state, and the second input port is in an on state. 5. The initialization synchronization device according to claim 4, characterized in that, The output processing circuit includes: a first output processing circuit for outputting a data signal, and a second output processing circuit for outputting a clock signal; The first input port of each of the digital selectors in the first output processing circuit is connected to the data port of the first controller, and each of the digital selectors in the first output processing circuit The second input port of is connected to the data port of the corresponding controller, The first input port of each of the digital selectors in the second output processing circuit is connected to the clock port of the first controller, and each of the digital selectors in the second output processing circuit The second input port of is connected to the clock port of the corresponding controller. 6. The initialization synchronization device according to claim 2, characterized in that, The input processing circuit includes: an AND gate logic circuit; When the signal processing circuit is in the first state, the AND gate logic circuit processes the received response signal generated by each sensor in the one or more sensors, and sends it to the first controller; Each of the one or more controllers receives a corresponding sensor-generated response signal when the signal processing circuit is in the second state. 7. The initialization synchronization device according to claim 6, characterized in that, The input processing circuit also includes: a signal selector; Each sensor in the one or more sensors is connected to the input terminal of the AND gate logic circuit, the output terminal of the AND gate logic circuit is connected to the first input terminal of the signal selector, and the signal The output end of the selector is connected to the first controller, and the first sensor corresponding to the first controller is also connected to the second input end of the signal selector; Wherein, when the signal processing circuit is in the first state, the AND gate logic circuit sends the processed signal to the first controller through the signal selector; When the signal processing circuit is in the second state, the signal selector sends the response signal generated by the first sensor to the first controller. 8. The initialization synchronization device according to claim 6, characterized in that, The input processing circuit includes: a first input processing circuit for inputting a data signal, and a second input processing circuit for inputting a clock signal. 9. The initialization synchronization device according to any one of claims 1 to 8, wherein the initialization synchronization device further comprises: a system register, the system register being connected to the CPU and the signal processing circuit respectively; The register value used by the CPU to control the system register is a first value, so that the signal processing circuit is in the first state; The CPU is further configured to control the register value of the system register to a second value, so that the signal processing circuit is in the second state, wherein the first value is different from the second value. 10. The initialization synchronization device according to any one of claims 1 to 8, characterized in that, the initialization synchronization device also includes one or more input and output IO interfaces, and the signal processing circuit communicates with one or more IO interfaces The one or more sensors are connected one by one; Wherein, when the signal processing circuit is in the first state, the one or more IO interfaces are all connected to the first controller; When the signal processing circuit is in the second state, each of the controllers is respectively connected to the corresponding sensor through an IO interface. 11. The initialization synchronization device according to any one of claims 1 to 8, characterized in that: The CPU is further configured to: before performing initialization processing on each of the sensors, send a reset instruction to each of the sensors, so as to clear initialization parameters in each of the sensors. 12. The initialization synchronization device according to any one of claims 1 to 8, wherein the CPU is further used for: After performing initialization processing on each of the sensors, receiving image information acquired by each of the sensors; According to the synchronization signal in the image information, it is judged whether the image information acquired by any two sensors is synchronized; Compensation adjustments are made for sensors whose acquired image information is out of sync. 13. An initialization synchronization method, characterized in that it is applied to an initialization synchronization device, and the initialization synchronization device includes: a CPU, one or more controllers, and a signal processing circuit, wherein the one or more controllers Each of the controllers is coupled to the CPU and the signal processing circuit, the signal processing circuit is connected to one or more sensors outside the initialization synchronization device, and the method includes: The CPU controls the signal processing circuit to be in a first state, the first state is used to instruct the first controller to be connected to each sensor in the one or more sensors through the signal processing circuit, and the first the controller is a controller of the one or more controllers; The first controller sends the initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit; The CPU controls the signal processing circuit to be in a second state, the second state is used to instruct each of the one or more controllers to be connected to a sensor through the signal processing circuit; Each controller sends the initialization signal or parameter modification signal generated by the CPU to a sensor corresponding to each controller, and the parameter modification signal is used to adjust the initialization parameters recorded in the sensor, The initialization parameter is a parameter carried in an initialization signal received by the sensor during the initialization process of each sensor. 14. The method according to claim 13, wherein the signal processing circuit comprises: an output processing circuit and an input processing circuit; After the CPU controls the signal processing circuit to be in the first state, the method further includes: the first controller sends the CPU-generated signal to each of the one or more sensors via the output processing circuit; The first controller receives, via the input processing circuit, respective generated response signals of each of the one or more sensors. 15. The method according to claim 14, wherein the output processing circuit comprises: one or more digital selectors, the output terminal of each digital selector in the one or more digital selectors is corresponding to sensor connections; The first controller sends the CPU-generated signal to each of the one or more sensors via the output processing circuit, comprising: The input end of each digital selector controlling the one or more digital selectors is connected to the first controller, so that the first controller sends one or more digital selectors through the one or more digital selectors a plurality of sensors sending signals generated by the CPU; After the CPU controls the signal processing circuit to be in the second state, the method further includes: The respective input terminals of each digital selector among the one or more digital selectors are controlled to be connected with corresponding controllers. 16. The method according to claim 14, wherein the input processing circuit comprises: an AND logic circuit; The first controller receives, via the input processing circuit, respective generated response signals from each of the one or more sensors, comprising: The first controller receives a signal processed by the AND gate logic circuit to receive a response signal generated by each of the one or more sensors respectively; After the CPU controls the signal processing circuit to be in the second state, the method further includes: Each of the one or more controllers receives a corresponding sensor-generated response signal. 17. The method according to any one of claims 13 to 16, wherein the initialization synchronization device further comprises: a system register, the system register is respectively connected to the CPU and the signal processing circuit, The CPU controls the signal processing circuit to be in a first state, including: The CPU controls the register value of the system register to be a first value, so that the signal processing circuit is in a first state; The CPU controls the signal processing circuit to be in a second state, including: The CPU controls the register value of the system register to be a second value, so that the signal processing circuit is in a second state, wherein the first value is different from the second value. 18. The method according to any one of claims 13 to 16, wherein the initialization synchronization device further comprises one or more input and output IO interfaces, and the signal processing circuit communicates with the One or more sensors are connected one by one; After the CPU controls the signal processing circuit to be in the first state, the method further includes: connecting the one or more IO interfaces to the first controller through the signal processing circuit; After the CPU controls the signal processing circuit to be in the second state, the method further includes: Through the signal processing circuit, each of the controllers is respectively connected to the corresponding sensor through an IO interface. 19. The method according to any one of claims 13 to 16, further comprising: Before performing initialization processing on each of the sensors, the CPU sends a reset instruction to each of the sensors to clear initialization parameters in each of the sensors. 20. The method according to any one of claims 13 to 16, further comprising: After performing initialization processing on each of the sensors, the CPU receives image information acquired by each of the sensors; The CPU judges whether the image information acquired by any two sensors is synchronized according to the synchronization signal in the image information; The CPU compensates and adjusts the sensors whose acquired image information is not synchronized. 21. A camera, characterized in that it comprises: a plurality of cameras and a system-on-chip SOC, the SOC comprising: the initialization synchronization device according to any one of claims 1 to 12, each of the cameras includes a sensor, and each Each of the sensors is connected to the initialization synchronization device.

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