CN112735501B - Data interaction method and device, main board and equipment with main board - Google Patents
Data interaction method and device, main board and equipment with main board Download PDFInfo
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- CN112735501B CN112735501B CN202011557544.XA CN202011557544A CN112735501B CN 112735501 B CN112735501 B CN 112735501B CN 202011557544 A CN202011557544 A CN 202011557544A CN 112735501 B CN112735501 B CN 112735501B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
The application relates to a data interaction method and device, a main board and equipment with the main board, wherein the method comprises the following steps: the main chip firstly calls a first address of the external memory which is stored in advance, then sends the first address to the memory connected with the bus through the bus so as to establish data connection between the external memory and the main chip, if the main chip receives a first response signal fed back by the external memory, the connection of the external memory is normal, and the bus can transmit data.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a data interaction method and apparatus, a motherboard, and a device with the motherboard.
Background
The charged erasable programmable read-only memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY, EEPROM) is a memory chip which is not lost after power failure, is generally arranged on a main board, and stores data parameters required by the operation of a main chip on the main board.
In the related art, many devices use a motherboard with an EEPROM and a main chip to control the operation process of the device, but some devices operate under different environments, and need to be based on different data parameters, namely, data stored in the EEPROM.
Disclosure of Invention
In order to solve the problems of complex operation and easy equipment damage caused by changing data required by the operation of a main chip by disassembling equipment to replace EEPROM in the related art, the application provides a data interaction method and device, a main board and equipment with the main board.
According to a first aspect of the present application, there is provided a data interaction method comprising:
calling a first address of a pre-stored external memory;
The first address is sent to an external memory connected with the bus through the bus so as to establish data connection between the external memory and a main chip;
And if a first response signal fed back by the external memory is received, reading all data stored in the external memory through the bus.
In an alternative embodiment, after the first address is sent to an external memory connected to the bus via the bus, the method further includes:
if the first response signal is not received, calling a second address of a prestored main board memory;
transmitting the second address to a main board memory connected with the bus through the bus so as to establish data connection between the main board memory and a main chip;
and if a second response signal fed back by the main board memory is received, reading all data stored in the main board memory through the bus.
In an optional embodiment, after the receiving the first response signal fed back by the external memory and reading all the data stored in the external memory through the bus, the method further includes:
checking all the read data according to a first preset checking mode to obtain a first checking result;
and if the first verification result is that the verification fails, displaying a fault mark.
In an optional embodiment, after the receiving the first response signal fed back by the external memory and reading all the data stored in the external memory through the bus, the method further includes:
if the writing program is read to be stored in the main chip, a prestored second address is sent to a main board memory connected with the bus through the bus so as to establish data connection between the main board memory and the main chip, wherein the second address is the address of the main board memory;
And if a third response signal fed back by the main board memory is received, executing the writing program, and writing all data read from the external memory into the main board memory.
In an optional embodiment, if the third response signal fed back by the main board memory is received, the writing program is executed, and all the data read from the external memory are written into the main board memory, including repeatedly executing the following steps:
All the data read from the external memory are rewritten into the main board memory;
checking the updated data in the main board memory according to a second preset checking mode to obtain a second checking result;
And stopping the repeated execution until the second checking result is that the checking is failed and the writing times meet the preset condition, or the second checking result is that the checking is successful.
According to a second aspect of the present application there is provided a data interaction device, the device comprising:
The first calling module is used for calling a first address of the external memory which is stored in advance;
the first sending module is used for sending the first address to an external memory connected with the bus through the bus so as to establish data connection between the external memory and the main chip;
And the first reading module is used for reading all data stored in the external memory through the bus if a first response signal fed back by the external memory is received.
In an alternative embodiment, the apparatus further comprises:
The second calling module is used for calling a second address of the prestored main board memory if the first response signal is not received;
the second sending module is used for sending the second address to a main board memory connected with the bus through the bus so as to establish data connection between the main board memory and a main chip;
and the second reading module is used for reading all data stored in the main board memory through the bus if a second response signal fed back by the main board memory is received.
In an alternative embodiment, the apparatus further comprises:
The verification module is used for verifying all the read data according to a first preset verification mode to obtain a first verification result;
and the display module is used for displaying a fault mark if the first verification result is verification failure.
In an alternative embodiment, the apparatus further comprises:
the third sending module is used for sending a prestored second address to a main board memory connected with the bus through the bus if the writing program is stored in the main chip, wherein the memory comprises an external memory and a main board memory so as to establish data connection between the main board memory and the main chip, and the second address is the address of the main board memory;
And the writing module is used for executing the writing program if receiving a third response signal fed back by the main board memory, and writing all data read from the external memory into the main board memory.
In an alternative embodiment, the writing module includes the following units that are repeatedly executed in sequence:
the writing unit is used for writing the first data into the main board memory;
the verification unit is used for verifying the updated data in the main board memory according to a second preset verification mode to obtain a second verification result;
And the repetition condition judgment unit is used for stopping the repeated execution action until the second verification result is verification failure and the writing times meet the preset condition or the second verification result is verification success.
According to a third aspect of the present application, there is provided a motherboard including a main chip, a motherboard memory, and a bus, the main chip and the motherboard memory being hooked on the bus;
The main board also comprises an external terminal, one end of the external terminal is used for being hung on the bus, and the other end of the external terminal is used for being hung on an external memory;
The main chip is provided with a data interaction program, so that the data interaction program is executed when the main chip runs, and the data interaction method of the first aspect of the application is realized.
According to a fourth aspect of the present application, there is provided a device with a motherboard, comprising a device housing and the motherboard of the third aspect of the present application;
the mainboard is arranged in the equipment shell, an opening is formed in the equipment shell, and the external terminal is fixed at the opening so as to be connected with an external memory.
The technical scheme provided by the application can comprise the following beneficial effects: in the technical scheme of the application, when data are interacted,
The main chip firstly calls a first address of the external memory stored in advance, then sends the first address to the external memory connected with the bus through the bus to establish data connection between the external memory and the main chip, if the main chip receives a first response signal fed back by the external memory, the external memory is indicated to be normally connected, and the bus can transmit data.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a flow chart of a method of data interaction according to an embodiment of the present application;
FIG. 2 is a schematic diagram of pins of an AT24C32 provided by an embodiment of the application;
FIG. 3 is a schematic diagram of a process of reading second data by a master chip according to an embodiment of the present application;
FIG. 4 is a flow chart of writing first data into a main board memory according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a specific flow for writing first data into a main board memory according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a data interaction device according to another embodiment of the present application;
Fig. 7 is a schematic structural diagram of a motherboard according to another embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
Referring to fig. 1, fig. 1 is a flow chart of a data interaction method according to an embodiment of the application.
As shown in fig. 1, the data interaction method provided in this embodiment may include:
step S101, a first address of a pre-stored external memory is called.
It should be noted that, in this embodiment, the address of the memory is generally determined by the high-low level provided to the address bit pins of the memory during the connection, for example, the type of the memory of the AT24C32 is exemplified, and the pins of the type of the memory can be referred to fig. 2, and fig. 2 is a schematic diagram of the pins of the AT24C32 according to an embodiment of the present application.
As shown in fig. 2, the address bits of the AT24C32 are the first pin A0, the second pin A1 and the third pin A2, and in the bus, the number of bits of the address needs 8 bits, so in this embodiment, the upper four bits in the address may be predefined, the first three bits of the lower four bits may be A2, A1 and A0 in sequence, and the last bit is the read/write bit. The positioning of other pins of AT24C32 may refer to a chip manual of the chip, and will not be described herein.
In a specific example, if in the hard wiring, A2, A1, A0 of the main board memory are all grounded, then the address of the main board memory is fixed bit 1, fixed bit 2, fixed bit 3, fixed bit 4, 0, and read/write, specifically, in this example, the read operation is set to 1, the write operation is set to 0, and fixed bit 1, fixed bit 2, fixed bit 3, and fixed bit 4 are sequentially set to 1, 0,1, and 0, then if the main chip is to read the data of the main board memory, then the address sent by the main chip to the bus is 10100001, and conversely, if the main chip is to write the data to the main board memory, the address sent by the main chip to the bus is 10100000.
In this embodiment, at least the main board memory and the external memory are connected to each other in a hanging manner on the bus, and based on the characteristics of the bus, the addresses of the main board memory and the external memory are required to be different, so that the wiring of the address bit pins of the main board memory and the external memory are required to be different, and the wiring of the address bit pins of the main board memory and the external memory is fixed during production, so that the status bits of the address bit pins of the main board memory and the external memory, that is, the high-low level status of the address pins, can be stored in the main chip in advance. The high and low levels refer to a high level concept and a low level concept in digital electronic technology, the high level is stored as 1 in the chip, and the low level is stored as 0 in the chip.
Based on the characteristics of the bus, in this step, the primary chip sends a first address to the bus, where the first address needs to include a read or write instruction that needs to be executed by the primary chip, which refers to the last bit in the specific example above, so that the primary chip first obtains the status bit of the address bit pin of the external memory, and then generates the first address based on the operation that needs to be performed on the external memory. Since the present application needs to read data from the external memory, the read operation needs to be written into the first address in this step.
In addition, the external memory in the step refers to a memory connected through an external terminal on the main board, and when the method is required to be executed, the external memory is only required to be connected to the external terminal.
Step S102, the first address is sent to an external memory connected with the bus through the bus to establish data connection between the external memory and the main chip.
In this step, the bus may be, but not limited to, an integrated circuit bus (Inter-INTEGRATED CIRCUIT, IIC), for example, after the IIC bus sends the first address to the IIC bus, the IIC bus establishes a data transmission channel between each memory hung on the bus and the main chip, including the bus between the external memory and the main chip, then the IIC bus transmits a data bit during each clock pulse, if the upper 7-bit address is all received by the external memory and determines that the address bit pins match with the upper 7-bit address pins, after receiving the 8 th bit, a response signal is fed back to the main chip, that is, the first response signal in step S103, and the non-matching memory, such as the main board memory, remains silent, and no longer receives the data of the main chip, at this time, a data connection between the external memory and the main chip is established.
Step S103, if a first response signal fed back by the external memory is received, all data stored in the external memory are read through the bus.
In this step, after the main chip receives the first response signal fed back by the external memory, it indicates that a data connection capable of normally performing data transmission has been established between the main chip and the external memory, and based on the read instruction in the first address received by the external memory in the foregoing step, the main memory may read all the data stored in the external memory, where all the data stored in the external memory refers to the data required for the operation of the main chip.
It should be noted that, the reading operation may be performed according to divided data blocks, for example, dividing the data according to the type of the data, and since there may be a plurality of data needed when the main chip is running, for example, temperature data, latitude and longitude data, etc., the dividing may be performed according to different types of data, that is, data representing different meanings.
Specifically, when the main chip reads a data block, a response signal is returned to the external memory, and a counter "+1" preset in the main chip is used for reading the next data block. Since the data required for the operation of the main chip of one device is fixed, the number of data blocks is fixed, and thus, when the count value in the counter reaches a preset value, that is, the number of data blocks preset, the reading operation is stopped.
In addition, after all the data stored in the external memory are read, the read data can be checked, for example, the read data can be checked according to a first preset checking mode to obtain a first checking result, and if the first checking result is that the checking is failed, a fault mark can be displayed. In a specific example, each data block includes a check bit, where the value of the check bit is a value obtained by processing other data except the check bit in the data block through a preset check algorithm, so that after the data is read, the same check algorithm can be used to process the read data except the check bit to obtain another value, and then the other value is compared with the value of the check bit in the data block, if the value is the same, it indicates that the reading is successful, if the value is different, the reading fails, a fault mark is displayed at this time to characterize the reading fault, and prompt is performed. Of course, the reading may be repeated until the verification is successful.
According to the technical scheme, when data interaction is performed, a main chip firstly calls a first address of a pre-stored external memory, then the first address is sent to the external memory connected with a bus through the bus to establish data connection between the external memory and the main chip, if the main chip receives a first response signal fed back by the external memory, the external memory is indicated to be normally connected, and the bus can transmit data, at the moment, all data stored in the external memory are read through the bus, so that all data stored in the external memory can be directly read through the bus for the operation of the main chip, the replacement of the main board memory is avoided, the equipment is not required to be disassembled, the operation is simpler, and the equipment is not damaged.
Of course, in this embodiment, there is a case that the main chip does not receive the first response signal, in order to ensure that the main chip operates normally, the data stored in the main board memory may be temporarily used, but it needs to be noted that, the data in the main board memory may not conform to the environment where the main chip is located, for example, the latitude and longitude data, the data stored in the main board memory may be a default latitude and longitude, and the environment where the main chip is located is not the latitude and longitude.
Referring to fig. 3, fig. 3 is a schematic flow chart of a main chip reading data in a main board memory according to an embodiment of the application.
As shown in fig. 3, the process of the master chip reading the data of the motherboard register may include:
Step S301, if the first response signal is not received, invoking a second address of the pre-stored motherboard memory.
It should be noted that, the failure to receive the first response signal may be due to the fact that the external memory is not accessed or the external memory is accessed by mistake. The specific way of calling the second address in this step may refer to the content of calling the first address in step S101, which is not described herein.
Step S302, a second address is sent to a main board memory connected with the bus through the bus to establish data connection between the main board memory and the main chip.
The specific manner in this step is similar to that in step S102, and reference may be made thereto, and details thereof will not be repeated here.
Step S303, if a second response signal fed back by the main board memory is received, all data stored in the main board memory are read through the bus.
The specific manner in this step is similar to that in step S103, and reference may be made thereto, and details thereof will not be repeated here.
Because the default stored programs in the main chip may be different, some may not consider the data stored in the external memory to be burned into the main board memory, and some may contain related programs for burning the data stored in the external memory into the main board memory, so that the main chip can directly operate according to the acquired data stored in the external memory for the device which does not include the data program burned into the external memory, while keeping the external memory normally connected to the bus; for the case of the related program which burns the data stored in the external memory into the main board memory, the data stored in the external memory can be written into the main board memory according to the program, and then the external memory is taken down, so that the external memory can be recycled.
Referring to fig. 4, fig. 4 is a schematic flow chart of writing first data into a main board memory according to an embodiment of the application.
As shown in fig. 4, after step S103, the process of writing the first data into the main board memory may include:
Step S401, if the write program is stored in the main chip, the second address, which is the address of the main board memory, is sent to the main board memory connected to the bus through the bus to establish the data connection between the main board memory and the main chip.
The specific manner in this step is similar to that in step S102, and reference may be made thereto, and details thereof will not be repeated here.
Step S402, if a third response signal fed back by the main board memory is received, a writing program is executed, and all data read from the external memory are written into the main board memory.
In order to ensure that all data read from the external memory written into the main board memory is correct, a verification may also be performed, and then the complete writing process in step S402 may refer to fig. 5, and fig. 5 is a schematic diagram of a specific flow for writing all data read from the external memory into the main board memory according to an embodiment of the present application.
As shown in fig. 5, the specific process of writing all data read from the external memory into the main board memory may include repeatedly performing the following steps:
Step S501, all data read from the external memory is overwritten into the main board memory.
It should be noted that, the writing process and the reading process are all performed according to the data block, so the specific content of this step may refer to the content described in step S103, and will not be described herein.
Step S502, checking the updated data in the main board memory according to a second preset checking mode to obtain a second checking result;
The specific verification process may be that all data currently stored in the main board memory are read first, then the second address is sent to a memory connected with the bus through the bus, the memory includes an external memory and a main board memory, so as to establish data connection between the main board memory and the main chip, and if a fourth response signal fed back by the main board memory is received, the data written in the main board memory are read.
The second verification manner in this step may be the same as the first verification manner described above, or may be different from the first verification manner, and in the same case, reference may be made to the verification process of the read data in step S103 in the foregoing embodiment, which is not repeated here.
Step S503, stopping repeating the execution of the operation until the second verification result is verification failure and the writing times meet the preset condition, or the second verification result is verification success.
In this step, two conditions for stopping the repeated execution are included, one is that the check result is that the check fails and the data of the preset storage bit meets the preset conditions, and the other is that the check result is that the check succeeds.
For the second, a successful verification indicates a successful write, and no re-write is needed after a successful write.
For the first, in order to avoid the occurrence of the dead cycle of the repeated writing, the embodiment increases the verification of the value in the preset storage bit, for example, the writing action is performed 3 times, and the preset condition is 3 or more, so that the value of the preset storage bit satisfies the preset condition at this time, and the writing can be stopped without the verification success at this time.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a data interaction device according to another embodiment of the application.
As shown in fig. 6, the data interaction device provided in this embodiment may include:
a first calling module 601, configured to call a first address of a pre-stored external memory;
The first sending module 602 is configured to send, through a bus, a first address to an external memory connected to the bus, so as to establish a data connection between the external memory and the main chip;
the first reading module 603 is configured to read all data stored in the external memory through the bus if a first response signal fed back by the external memory is received.
In an alternative embodiment, the apparatus further comprises:
the second calling module is used for calling a second address of the prestored main board memory if the first response signal is not received;
the second sending module is used for sending a second address to a main board memory connected with the bus through the bus so as to establish data connection between the main board memory and the main chip;
And the second reading module is used for reading all data stored in the main board memory through the bus if a second response signal fed back by the main board memory is received.
In an alternative embodiment, the apparatus further comprises:
The verification module is used for verifying all the read data according to a first preset verification mode to obtain a first verification result;
and the display module is used for displaying a fault mark if the first verification result is verification failure.
In an alternative embodiment, the apparatus further comprises:
The third sending module is used for sending a prestored second address to a main board memory connected with the bus through the bus if the writing program is stored in the main chip, wherein the memory comprises an external memory and the main board memory so as to establish data connection between the main board memory and the main chip, and the second address is the address of the main board memory;
And the writing module is used for executing a writing program if receiving a third response signal fed back by the main board memory and writing all data read from the external memory into the main board memory.
In an alternative embodiment, the writing module includes the following elements that are repeatedly executed in sequence:
The writing unit is used for overwriting all data read from the external memory into the main board memory;
The verification unit is used for verifying the updated data in the main board memory according to a second preset verification mode to obtain a second verification result;
And the repetition condition judgment unit is used for stopping repeating the execution action until the second verification result is that the verification fails and the writing times meet the preset condition or the second verification result is that the verification is successful.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a motherboard according to another embodiment of the present application.
As shown in fig. 7, the motherboard provided in this embodiment may include a main chip 701, a motherboard memory 702, and a bus, where the main chip and the motherboard memory are attached to the bus;
the main board also comprises an external terminal 703, one end of the external terminal is used for being hung on the bus, and the other end is used for being hung on an external memory 704;
The main chip is provided with a data interaction program, so that the data interaction program is executed when the main chip runs, and the data interaction method provided by the embodiment of the right is realized.
It should be noted that the external terminal is a device with a connection terminal, and the external terminal may have two ends, and one end is used to connect to the bus, and taking the IIC bus as an example, the SCL hard wire and the SDA hard wire in fig. 7 are.
The external connection terminals in fig. 7 have 4 connection terminals, wherein two connection terminals are connected to the SCL hard wire and the SDA hard wire, and the other two connection terminals are connected to the power supply, and one connection terminal is grounded, so that the working power supply, the high level and the low level can be provided for the external connection memory.
In a specific example, the external terminal may be a pin, for example, a female terminal, and the hard wire of the external memory may be connected to a male terminal, so that when the external memory needs to be accessed, only the male terminal needs to be inserted into the female terminal.
In addition, the application also provides equipment with the main board in the embodiment, which comprises an equipment shell and the main board provided by the embodiment; the mainboard sets up in the inside of equipment shell, is provided with the opening on the equipment shell, and external terminal fixes in the opening part to connect external memory conveniently.
It should be noted that, the device with the motherboard provided in this embodiment may be an air conditioner, an air purifier, a fresh air unit, and other devices.
The specific manner in which the various modules perform the operations in the apparatus of the above embodiments have been described in detail in connection with the embodiments of the method, and will not be described in detail herein.
It is to be understood that the same or similar parts in the above embodiments may be referred to each other, and that in some embodiments, the same or similar parts in other embodiments may be referred to.
It should be noted that in the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present application, unless otherwise indicated, the meaning of "plurality" means at least two.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (8)
1. A method of data interaction, comprising:
calling a first address of a pre-stored external memory;
The first address is sent to an external memory connected with the bus through the bus so as to establish data connection between the external memory and a main chip;
If a first response signal fed back by the external memory is received, reading all data stored in the external memory through the bus;
checking all the read data according to a first preset checking mode to obtain a first checking result;
if the first verification result is that verification fails, displaying a fault mark;
if the first response signal is not received, calling a second address of a prestored main board memory;
transmitting the second address to a main board memory connected with the bus through the bus so as to establish data connection between the main board memory and a main chip;
and if a second response signal fed back by the main board memory is received, reading all data stored in the main board memory through the bus.
2. The method according to claim 1, wherein after receiving the first response signal fed back by the external memory and reading all data stored in the external memory through the bus, the method further comprises:
if the writing program is read to be stored in the main chip, a prestored second address is sent to a main board memory connected with the bus through the bus so as to establish data connection between the main board memory and the main chip, wherein the second address is the address of the main board memory;
And if a third response signal fed back by the main board memory is received, executing the writing program, and writing all data read from the external memory into the main board memory.
3. The data interaction method according to claim 2, wherein if the third response signal fed back from the main board memory is received, executing the writing program, and writing all the data read from the external memory into the main board memory, includes repeatedly executing the following steps:
All the data read from the external memory are rewritten into the main board memory;
checking the updated data in the main board memory according to a second preset checking mode to obtain a second checking result;
And stopping the repeated execution until the second checking result is that the checking is failed and the writing times meet the preset condition, or the second checking result is that the checking is successful.
4. A data interaction device, the device comprising:
The first calling module is used for calling a first address of the external memory which is stored in advance;
the first sending module is used for sending the first address to an external memory connected with the bus through the bus so as to establish data connection between the external memory and the main chip;
the first reading module is used for reading all data stored in the external memory through the bus if a first response signal fed back by the external memory is received;
The verification module is used for verifying all the read data according to a first preset verification mode to obtain a first verification result;
The display module is used for displaying a fault mark if the first verification result is verification failure;
The second calling module is used for calling a second address of the prestored main board memory if the first response signal is not received;
the second sending module is used for sending the second address to a main board memory connected with the bus through the bus so as to establish data connection between the main board memory and a main chip;
and the second reading module is used for reading all data stored in the main board memory through the bus if a second response signal fed back by the main board memory is received.
5. The data interaction device of claim 4, wherein the device further comprises:
the third sending module is used for sending a prestored second address to a main board memory connected with the bus through the bus if the writing program is stored in the main chip, so as to establish data connection between the main board memory and the main chip, wherein the second address is the address of the main board memory;
And the writing module is used for executing the writing program if receiving a third response signal fed back by the main board memory, and writing all data read from the external memory into the main board memory.
6. The data interaction device of claim 5, wherein the writing module comprises the following elements, which are repeatedly executed in sequence:
The writing unit is used for overwriting all the data read from the external memory into the main board memory;
the verification unit is used for verifying the updated data in the main board memory according to a second preset verification mode to obtain a second verification result;
And the repetition condition judgment unit is used for stopping the repeated execution action until the second verification result is verification failure and the writing times meet the preset condition or the second verification result is verification success.
7. The main board is characterized by comprising a main chip, a main board memory and a bus, wherein the main chip and the main board memory are hung on the bus;
The main board also comprises an external terminal, one end of the external terminal is used for being hung on the bus, and the other end of the external terminal is used for being hung on an external memory;
the main chip is provided with a data interaction program, so that the data interaction program is executed when the main chip runs, and the data interaction method of any one of claims 1 to 3 is realized.
8. A device with a motherboard, comprising a device housing and the motherboard of claim 7;
the mainboard is arranged in the equipment shell, an opening is formed in the equipment shell, and the external terminal is fixed at the opening so as to be connected with an external memory.
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