CN112740633B - Method and circuit for reducing crest factor for cable television amplifier - Google Patents

Abstract

A Crest Factor Reduction (CFR) system includes a digital ramp filter coupled to an input of the CFR system. In some embodiments, the digital tilt filter is configured to receive the system input signal and generate a digital tilt filter output signal at a digital tilt filter output. In some examples, the CFR system further includes a CFR module coupled to the digital tilt filter output, wherein the CFR module is configured to receive the digital tilt filter output signal and perform CFR processing on the digital tilt filter output signal to generate a CFR module output signal at the CFR module output. Additionally, the CFR system may further include a digital tilt equalizer coupled to the CFR module output, wherein the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

Description

Method and circuit for reducing crest factor for cable television amplifier

Technical Field

Examples of the present disclosure relate generally to integrated circuits ("ICs"), and more particularly, to embodiments related to crest factor reduction for cable television (CATV) amplifiers.

Background Art

To meet the demand for higher data rates for Internet, telephone and video services, the cable industry is deploying new high data rate and broadband remote PHY nodes based on the new Data Over Cable Service Interface Specification (DOCSIS) 3.1 standard. DOCSIS 3.1 supports 4096 quadrature amplitude modulation (QAM) and uses orthogonal frequency division multiplexing (OFDM). As a result, the transmission signal quality requirements of DOCSIS 3.1 are higher than those of the current standard DOCSIS 3.0. Due to the more complex functions associated with DOCSIS 3.1, cable television (CATV) amplifiers may operate in a nonlinear region. The nonlinear effects of CATV amplifiers will greatly reduce the quality of the transmitted signal. In addition, the new components that provide high data rates and the more complex functions of DOCSIS 3.1 will also consume power themselves. However, since the power supply to each node (e.g., each remote PHY node) is fixed, the power consumption of other components (e.g., CATV amplifiers) should be reduced. Therefore, while it is desirable to provide the advanced performance of DOCSIS 3.1, it is challenging to simultaneously provide improved transmit signal quality and reduce power consumption of other components (eg, CATV amplifiers).

Therefore, there is a need for improved methods and circuits for reducing the crest factor of CATV amplifiers.

Summary of the invention

In some embodiments according to the present disclosure, a crest factor reduction (CFR) system includes a digital tilt filter coupled to an input of the CFR system. In some embodiments, the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at a digital tilt filter output. In some examples, the CFR system also includes a CFR module coupled to the output of the digital tilt filter, wherein the CFR module is configured to receive the digital tilt filter output signal and perform CFR processing on the digital tilt filter output signal to generate a CFR module output signal at the CFR module output. In addition, the CFR system may include a digital tilt equalizer coupled to the output of the CFR module, wherein the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

In some embodiments, the CFR system further comprises a digital predistortion (DPD) module coupled to an output of the CFR module, wherein the DPD module is configured to receive the CFR module output signal and perform DPD processing on the CFR module output signal to generate a DPD module output signal at the DPD module output. In some cases, a digital tilt equalizer is coupled to the DPD module output, and the digital tilt equalizer is configured to receive the DPD module output signal and generate a system output signal.

In some embodiments, the system input signal has a first peak-to-average power ratio (PAPR), and the CFR module output signal has a second PAPR that is less than the first PAPR.

In some embodiments, the CFR system further comprises a first linear data path coupled to an input of the CFR system and connected in parallel with the CFR module and the DPD module to generate a first time-delayed signal. In some examples, the CFR system further comprises a first combiner configured to combine the digital tilt equalizer output signal and the first time-delayed signal to generate a system output signal.

In some embodiments, the CFR system further comprises a second linear data path coupled to the input of the CFR system and connected in parallel with the CFR module to generate a second time-delayed signal. For example, the second combiner is configured to combine the CFR module output signal and the second time-delayed signal to generate a first output signal, and the third combiner is configured to combine the first output signal and the DPD module output signal to generate a system output signal.

In some embodiments, the CFR system further comprises a nonlinear data path coupled to an output of the CFR module, wherein the nonlinear data path comprises a plurality of parallel data path cells each coupled to the output of the CFR module, wherein each of the plurality of parallel data path cells is configured to add a different inverse nonlinear component corresponding to a nonlinear component of the amplifier to the CFR module output signal, and wherein the combiner is configured to combine the output of each of the plurality of parallel data path cells to generate a DPD module output signal.

In some embodiments, a digital-to-analog converter (DAC) is configured to receive a system output signal and generate a DAC output signal, wherein the analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal, and wherein the digital tilt filter is configured to model the analog tilt filter.

In some embodiments, the digital shelving equalizer is configured to model the inverse of an analog shelving filter.

In some embodiments, the CFR system further comprises a single sideband Hilbert filter, wherein the single sideband Hilbert filter input is configured to receive the DPD module output signal, and the single sideband Hilbert filter output is coupled to the digital tilt equalizer input.

In some embodiments, the CFR system further comprises an adaptation engine configured to receive feedback data from the amplifier output, wherein based on the feedback data, the adaptation engine is configured to update a configuration of the CFR module.

In some embodiments according to the present disclosure, a digital front end (DFE) system is configured to perform crest factor reduction (CFR) processing, and the DFE system includes a digital up converter (DUC) configured to receive and convert a baseband data input signal to generate a composite signal. In various embodiments, the DFE system also includes a CFR system including a digital shelving filter, a CFR module, and a digital shelving equalizer, wherein the digital shelving filter is configured to receive the composite signal and generate a digital shelving filter output signal, wherein the CFR module is configured to receive the digital shelving filter output signal and perform CFR processing on the digital shelving filter output signal to generate a CFR module output signal; wherein the digital shelving equalizer is configured to receive the CFR module output signal and generate a CFR system output signal, and wherein the CFR system output signal is coupled to an amplifier. In some examples, the DFE system also includes an adaptation engine configured to receive feedback data from an output of the amplifier, wherein based on the feedback data, the adaptation engine is configured to update a configuration of the CFR system.

In some embodiments, the CFR processing is configured to reduce a peak-to-average power ratio (PAPR) of the digital shelving filter output signal.

In some embodiments, the CFR system further comprises a digital predistortion (DPD) module comprising a nonlinear data path coupled to an output of the CFR module, wherein the nonlinear data path comprises a plurality of parallel data path cells, each of the parallel data path cells being coupled to the output of the CFR module, wherein each of the plurality of parallel data path cells is configured to model a different inverse nonlinear component corresponding to a nonlinear component of the amplifier, wherein a combiner is configured to combine an output of each of the plurality of parallel data path cells to generate a DPD module output signal, and wherein a digital tilt equalizer is configured to receive the DPD module output signal and generate a CFR system output signal.

In some embodiments, a digital-to-analog converter (DAC) is configured to receive a CFR system output signal and generate a DAC output signal, wherein the analog shelving filter is configured to receive the DAC output signal and generate an analog shelving filter output signal, and wherein the digital shelving filter is configured to model the analog shelving filter.

In some embodiments, the digital shelving equalizer is configured to model the inverse of an analog shelving filter.

In some embodiments according to the present disclosure, a method includes receiving an input signal at a digital tilt filter of a crest factor reduction (CFR) system and generating a digital tilt filter output signal at a digital tilt filter output terminal. In various examples, the method also includes performing CFR processing on the digital tilt filter output signal at a CFR module of the CFR system to generate a CFR module output signal, wherein the CFR processing is configured to reduce a peak-to-average power ratio (PAPR) of the digital tilt filter output signal. In some examples, the method also includes receiving the CFR module output signal at a digital tilt equalizer of the CFR system and generating a system output signal. In some embodiments, the method also includes providing the system output signal to an amplifier.

In some embodiments, the method further comprises updating a configuration of the CFR system in response to feedback data received from an output of the amplifier.

In some embodiments, the method further comprises performing DPD processing on the CFR module output signal at a digital predistortion (DPD) module of the CFR system to generate a DPD module output signal. In some examples, the method further comprises receiving the DPD module output signal at a digital tilt equalizer of the CFR system and generating a system output signal.

In some embodiments, the DPD module further comprises a nonlinear data path coupled to an output of the CFR module, wherein the nonlinear data path comprises a plurality of parallel data path cells, each data path cell being coupled to the output of the CFR module, wherein each of the plurality of parallel data path cells is configured to model a different inverse nonlinear component corresponding to the nonlinear component of the amplifier, and wherein a combiner is configured to combine the output of each of the plurality of parallel data path cells to generate the DPD module output signal.

In some embodiments, the method further includes reducing power consumption of the amplifier in response to providing the system output signal to the amplifier while operating the amplifier in a non-linear region.

In some embodiments according to the present disclosure, a digital predistortion (DPD) system includes an input terminal configured to receive a DPD input signal. In some embodiments, the DPD system also includes a nonlinear data path coupled to the input terminal, wherein the nonlinear data path includes a plurality of parallel data path units each coupled to the input terminal, wherein each of the plurality of parallel data path units is configured to add a different inverse nonlinear component corresponding to a nonlinear component of an amplifier to the DPD input signal, and wherein a first combiner is configured to combine the output of each of the plurality of parallel data path units to generate a first predistortion signal. In some embodiments, the DPD system also includes a linear data path coupled to the input terminal in parallel with the nonlinear data path to generate a second predistortion signal, and includes a second combiner configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.

In some embodiments, the plurality of parallel data path units include a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

In some embodiments, the baseband DPD data path is configured to add an inverse nonlinear baseband component to the DPD input signal.

In some embodiments, the video bandwidth DPD data path is configured to add an inverse non-linear video bandwidth component to the DPD input signal.

In some embodiments, the second harmonic DPD data path is configured to add an inverse second harmonic component to the DPD input signal.

In some embodiments, the third harmonic DPD data path is configured to add an inverse third harmonic component to the DPD input signal.

In some embodiments, the DPD system further includes a digital shelving filter configured to model an analog shelving filter, wherein a digital shelving filter input is coupled to the input and a digital shelving filter output is coupled to the nonlinear data path.

In some embodiments, the DPD system further comprises a digital tilt equalizer configured to model an inverse of an analog tilt filter, wherein the digital tilt equalizer input is configured to receive a first predistortion signal, and the second combiner is configured to combine the digital tilt equalizer output to the second predistortion signal to generate a DPD output signal.

In some embodiments, the DPD system further comprises a single sideband Hilbert filter, wherein the single sideband Hilbert filter input is configured to receive the first predistortion signal, and the single sideband Hilbert filter output is coupled to the digital tilt equalizer input.

In some embodiments, the DPD output signal is coupled to an amplifier input to generate an amplified output signal, and the DPD output signal is configured to compensate for a plurality of nonlinear components of the amplifier.

In some embodiments according to the present disclosure, a digital front end (DFE) system configured to perform digital predistortion (DPD) processing includes a digital upconverter (DUC) configured to receive and convert a baseband data input signal to generate a composite signal. In some embodiments, the DFE system also includes a DPD system configured to receive the composite signal at a DPD input and perform DPD processing on the composite signal, wherein the DPD input is coupled to a plurality of parallel data path units, wherein at least one of the plurality of parallel data path units is configured to add an inverse harmonic component corresponding to a nonlinear harmonic component of an amplifier to the composite signal, wherein a combiner is configured to combine an output of each of the plurality of data path units to generate a DPD output signal, and wherein the DPD output signal is coupled to the amplifier. In some embodiments, the DPD output signal is configured to compensate for the nonlinear harmonic component of the amplifier.

In some embodiments, the plurality of parallel data path units include a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

In some embodiments, the DUC is configured to perform an interpolation process on the baseband data input signal to generate an interpolated signal, and the DUC is configured to perform a mixing process on the interpolated signal to generate a composite signal.

In some embodiments, the DPD system further comprises a digital shelving filter configured to model the analog shelving filter, wherein the digital shelving filter input is configured to receive the composite signal, and wherein the digital shelving filter output is coupled to the plurality of parallel data path units.

In some embodiments, the DPD system further comprises a digital tilt equalizer configured to model an inverse of an analog tilt filter, wherein an input of the digital tilt equalizer is configured to receive a combined output of each of a plurality of data path units, and wherein another combiner is configured to combine the digital tilt equalizer outputs into a linear DPD signal to generate a DPD output signal.

In some embodiments according to the present disclosure, a method includes receiving a DPD input signal at an input of a digital predistortion (DPD) system. In some embodiments, the method also includes receiving the DPD input signal at a nonlinear data path coupled to the input of the DPD system, wherein the nonlinear data path includes a plurality of parallel data path units, wherein each parallel data path unit is coupled to the input. In some embodiments, the method also includes adding an inverse nonlinear component corresponding to a nonlinear component of an amplifier to the DPD input signal by each of the plurality of parallel data path units. In some embodiments, the method also includes combining the output of each of the plurality of parallel data path units by a first combiner to generate a first predistortion signal. In some embodiments, the method also includes receiving the DPD input signal at a linear data path coupled to the input in parallel with the nonlinear data path to generate a second predistortion signal. In some embodiments, the method also includes combining the first predistortion signal and the second predistortion signal by a second combiner to generate a DPD output signal.

In some embodiments, the plurality of parallel data path units include a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

In some embodiments, the method further includes: adding an inverse nonlinear baseband component to the DPD input signal via a baseband DPD data path; adding an inverse nonlinear video bandwidth component to the DPD input signal via a video bandwidth DPD data path; adding an inverse second harmonic component to the DPD input signal via a second harmonic DPD data path; and adding an inverse third harmonic component to the DPD input signal via a third harmonic DPD data path.

In some embodiments, the method further includes providing the DPD output signal to an amplifier input to generate an amplified output signal, wherein the DPD output signal is configured to compensate for a plurality of nonlinear components of the amplifier.

In some embodiments, the method further includes reducing power consumption of the amplifier in response to providing the DPD output signal to the amplifier while operating the amplifier in a non-linear region.

Other aspects and features will become apparent from a review of the following detailed description and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an exemplary architecture for an IC according to some embodiments of the present disclosure.

FIG. 2 is a schematic diagram of an exemplary cable network according to some embodiments.

3 is a schematic diagram of an exemplary digital front end (DFE) system according to some embodiments.

4A provides a diagram of a digital predistortion (DPD) - crest factor reduction (CFR) system according to some embodiments.

FIG. 4B provides an example of a DPD module according to some embodiments.

5A and 5B provide an exemplary DPD-CFR input spectrum and a DPD-CFR output spectrum, respectively, according to some embodiments.

6A provides an exemplary graph showing the normalized magnitude of an analog shelving filter output sampled over time and illustrating the effect of performing CFR processing, in accordance with some embodiments.

6B shows the power spectrum at the output of the analog shelving filter after performing CFR processing according to some embodiments.

7A, 7B, and 7C provide exemplary graphs showing normalized amplitude of CATV amplifier output sampled over time and illustrating the effect of performing CFR processing, in accordance with some embodiments.

8A illustrates a cumulative distribution function (CCDF) plot of a single carrier, showing the effect of performing CFR processing, according to some embodiments.

FIG. 8B shows a power spectrum corresponding to the data of FIG. 8A after CFR processing has been performed according to some embodiments.

9A and 9B provide graphs of CATV amplifier transfer functions, showing amplitude to amplitude distortion (AM/AM), and illustrating the effects of performing either or both DPD and CFR processing, according to some embodiments.

10A and 10B provide graphs of DPD output stability performance, illustrating the effect of performing CFR processing, according to some embodiments.

11 provides a table including modulation error ratio (MER) data for a CATV amplifier, showing the effect of applying the correction provided by the DPD-CFR system to the MER data, according to some embodiments.

12 is a flow chart illustrating a method of performing crest factor reduction processing and digital pre-distortion processing in a DPD-CFR system according to some embodiments.

13, 14, 15, and 16 illustrate equations including graphical representations, according to some embodiments, where the equations provide derivations for each of the non-linear data path elements of FIG. 4. FIG.

17 illustrates the power spectrum of a single carrier, showing the non-linear effects of CATV amplifiers, according to some embodiments.

18 illustrates a power spectrum showing the result of applying a baseband DPD correction to the power spectrum of FIG. 17 , according to some embodiments.

19 illustrates a power spectrum showing the result of applying a second harmonic DPD correction to the power spectrum of FIG. 17 , according to some embodiments.

20 illustrates a power spectrum showing the result of applying a third harmonic DPD correction to the power spectrum of FIG. 17 , according to some embodiments.

21 illustrates a power spectrum showing the results of applying both baseband DPD correction and video bandwidth DPD correction simultaneously according to some embodiments.

22 illustrates a power spectrum showing adjacent channel power ratio (ACPR) correction resulting from application of corrections provided by a DPD system in accordance with some embodiments.

23 provides a table including modulation error ratio (MER) data for a CATV amplifier, showing the effect of applying corrections provided by a DPD system to the MER data, according to some embodiments.

FIG. 24 is a flow chart showing a method for performing digital pre-distortion processing in a DPD system according to some embodiments.

DETAILED DESCRIPTION

Various embodiments are described below with reference to the accompanying drawings, in which exemplary embodiments are shown. However, the claimed invention may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Throughout the text, the same reference numerals represent the same units. Therefore, similar units will no longer be described in detail with respect to each of the accompanying drawings. It should also be noted that the accompanying drawings are intended only to help describe the embodiments. They are not intended to be an exhaustive description of the claimed invention or to limit the scope of the claimed invention. In addition, the illustrated embodiments do not necessarily have all the aspects or advantages shown. The aspects or advantages described in conjunction with a particular embodiment are not necessarily limited to the embodiment, and even if not shown or explicitly described as such, may be practiced in any other embodiment. These features, functions and advantages may be implemented independently in various embodiments, or may be combined in other embodiments.

Before describing exemplary embodiments that are schematically illustrated in several figures, a general introduction is provided to provide a further understanding.

As described above, the cable industry is deploying new high data rate and broadband remote PHY nodes based on the DOCSIS 3.1 standard to meet the demand for higher data rates for Internet, telephone and video services. DOCSIS 3.1 supports 4096 (4K) quadrature amplitude modulation (QAM) and uses orthogonal frequency division multiplexing (OFDM). As a result, the transmission signal quality requirements of DOCSIS 3.1 are higher than those of the current standard DOCSIS 3.0. Due to the more complex functions associated with DOCSIS 3.1, cable television (CATV) amplifiers may operate in a nonlinear region. The nonlinear effects of CATV amplifiers will greatly reduce the quality of the transmitted signal. In addition, the new components that provide high data rates and more complex functions of DOCSIS 3.1 themselves also consume power. However, since the power supply power to each node (e.g., each remote PHY node) is fixed, the power consumption of other components (e.g., CATV amplifiers) should be reduced. Therefore, although it is expected to provide the advanced performance of DOCSIS3.1, it is challenging to simultaneously provide improved transmission signal quality and reduce the power consumption of other components (e.g., CATV amplifiers).

In at least some prior art, a shelving equalizer (shelving filter) with a deep attenuation of up to 22 dB on the 1.2 GHz cable spectrum is implemented in the analog transmission path to compensate for the loss of the coaxial cable (e.g., from the CATV amplifier to the cable modem). However, compared with the current DOCSIS 3.0 standard, the DOCSIS3.1 waveform using 4K QAM OFDM modulation shows a higher peak-to-average power ratio (PAPR). In this way, for the same RMS power output of the CATV amplifier in DOCSIS 3.0, the peak of the DOCSIS 3.1 waveform will be located in the nonlinear region of the CATV amplifier. Therefore, the quality of the transmitted signal will decrease. Digital pre-distortion (DPD) can be used to improve the signal quality of the CATV amplifier, for example, by making the CATV operate in a more efficient area. DPD has been used in wireless communication technology, in which the signal bandwidth of the wireless communication technology is much narrower than the signal bandwidth used for wired communication technology. In addition, in wireless communication, the harmonics of the nonlinear effects of the wireless components will not fall into the signal bandwidth. In this way, the DPD used for wireless communication only needs to model the nonlinear components projected around the baseband frequency. However, for cable applications, the harmonics of the nonlinear effects of the CATV amplifier signal will fall into the signal bandwidth. Therefore, the DPD implementation for cable applications should model the harmonic components of the nonlinear effects of the CATV amplifier. In addition, the shelving equalizer with deep attenuation cannot be implemented in the digital domain, and the implementation of the digital shelving equalizer will reduce the transmission waveform quality of the low-frequency carrier due to the limited digital resolution of the digital-to-analog converter (DAC).

In addition, as mentioned above, the DOCSIS3.1 waveform using 4K QAM OFDM modulation exhibits a higher PAPR compared to the current DOCSIS 3.0 standard. Some effects of high PAPR include in-band distortion and out-of-band distortion (e.g., including increased adjacent channel leakage ratio (ACLR)). Crest factor reduction (CFR) can be used to reduce the PAPR of a signal by clipping the signal and allowing additional gain at the output of the CFR. Clipping is performed by intentionally limiting the signal so that the amplitude is limited to a maximum value within the desired range. By using CFR, an amplifier (e.g., a CATV amplifier) can be made to operate near its 1dB compression point, thereby improving the efficiency of the CATV amplifier; in addition, when used in conjunction with DPD, CFR can significantly improve the stability of DPD (e.g., avoiding DPD divergence) and further improve the efficiency of the CATV amplifier. For integrated circuit (IC) solutions, it has been found that the CFR and DPD data paths implemented in a digital front end (DFE) chip can provide solutions for high PAPR of DOCSIS3.1 waveforms, DPD stability, and efficiency of CATV amplifiers, as well as be used to model the harmonic components of CATV amplifier nonlinear effects and deep attenuation on the transmit spectrum in CATV amplifiers. Therefore, embodiments of the present disclosure provide improved transmit signal quality, increased CATV amplifier efficiency, and reduced CATV amplifier power consumption.

With the above general understanding in mind, various embodiments of methods and circuits for providing CFR for CATV amplifiers are generally described below. Because one or more of the above embodiments are illustrated using a specific type of IC, a detailed description of such an IC is provided below. However, it should be understood that other types of ICs may benefit from one or more embodiments described herein.

A programmable logic device ("PLD") is a well-known integrated circuit that can be programmed to perform a specified logic function. One type of PLD, a field programmable gate array ("FPGA"), typically includes an array of programmable tiles. These programmable tiles may include, for example, input/output blocks ("IOBs"), configurable logic blocks ("CLBs"), application specific random access memory blocks ("BRAMs"), multipliers, digital signal processing blocks ("DSPs"), processors, clock managers, delay locked loops ("DLLs"), etc. As used herein, "includes" and "comprising" mean including without limitation.

Each programmable slice typically includes programmable interconnects and programmable logic. The programmable interconnects typically include many interconnect lines of different lengths interconnected by programmable interconnect points ("PIPs"). Programmable logic uses programmable cells to implement user-designed logic, which may include, for example, function generators, registers, arithmetic logic, etc.

The programmable interconnect and programmable logic can usually be programmed by loading a stream of configuration data into internal configuration memory cells, which define how the programmable cells are configured. The configuration data can be read from a memory (e.g., from an external PROM) or written to the FPGA by an external device. The collective state of the individual memory cells then determines the functionality of the FPGA.

Another type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD contains two or more "functional blocks" that are connected together and to input/output ("I/O") resources through an interconnect switch matrix. Each functional block of a CPLD includes a two-level AND/OR structure similar to that used in programmable logic array ("PLA") and programmable array logic ("PAL") devices. In a CPLD, configuration data is typically stored on-chip in nonvolatile memory. In some CPLDs, configuration data is stored on-chip in nonvolatile memory and then downloaded to volatile memory as part of the initial configuration (programming) sequence.

Typically, for each of these programmable logic devices ("PLDs"), the functionality of the device is controlled for this purpose by configuration data provided to the device. The configuration data may be stored in volatile memory (e.g., static memory cells common in FPGAs and some CPLDs), non-volatile memory (e.g., FLASH memory in some CPLDs), or any other type of memory cell.

Other PLDs are programmed by applying a processing layer, such as a metal layer, that interconnects the various elements on the device in a programmable manner. These PLDs are referred to as mask programmable devices. PLDs may also be implemented in other ways (e.g., using fuse or anti-fuse technology). The terms "PLD" and "programmable logic device" include, but are not limited to, these exemplary devices, as well as devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch structure that programmably interconnects the hard-coded transistor logic.

As described above, advanced FPGAs can include several different types of programmable logic blocks in an array. For example, FIG. 1 shows an exemplary FPGA architecture 100. FPGA architecture 100 includes a large number of different programmable slices, including multi-gigabit transceivers ("MGTs") 101, configurable logic blocks ("CLBs") 102, random access memory blocks ("BRAMs") 103, input/output blocks ("IOBs") 104, configuration and clock logic ("CONFIG/CLOCKS") 105, digital signal processing blocks ("DSPs") 106, dedicated input/output blocks ("I/Os") 107 (e.g., configuration ports and clock ports), and other programmable logic 108, such as digital clock managers, analog-to-digital converters, system monitoring logic, etc. Some FPGAs also include dedicated processor blocks ("PROCs") 110. In some embodiments, FPGA architecture 100 includes an RF data converter subsystem that includes multiple radio frequency analog-to-digital converters (RF-ADCs) and multiple radio frequency digital-to-analog converters (RF-DACs). In various examples, the RF-ADC and RF-DAC can be configured individually for real data, or can be configured in pairs for real and imaginary I/Q data.In at least some examples, FPGA architecture 100 can implement an RFSoC device.

In some FPGAs, each programmable slice may include at least one programmable interconnect cell ("INT") 111 having connections to input and output terminals 120 of programmable logic cells within the same slice, as shown in the example included at the top of FIG. Each programmable interconnect cell 111 may also include connections to interconnect segments 122 of adjacent programmable interconnect cells in the same slice or other slices. Each programmable interconnect cell 111 may also include connections to interconnect segments 124 of general routing resources between logic blocks (not shown). General routing resources may include routing channels between logic blocks (not shown) and switch blocks (not shown) for connecting interconnect segments, wherein the logic blocks include interconnect segments (e.g., interconnect segments 124). Interconnect segments of general routing resources (e.g., interconnect segments 124) may span one or more logic blocks. Programmable interconnect cells 111, together with general routing resources, implement a programmable interconnect structure ("programmable interconnect") for the FPGA shown.

In an exemplary embodiment, CLB 102 may include configurable logic elements (“CLEs”) 112 that may be programmed to implement user logic, and a single programmable interconnect cell (“INT”) 111. BRAM 103 may include a BRAM logic cell (“BRL”) 113 in addition to one or more programmable interconnect cells. Typically, the number of interconnect cells included in a slice depends on the height of the slice. In the illustrated example, the BRAM slice has the same height as the five CLBs, but other numbers (e.g., four) may also be used. In addition to an appropriate number of programmable interconnect cells, DSP slice 106 may also include a DSP logic cell (“DSPL”) 114. In addition to one instance of programmable interconnect cell 111, IOB 104 may also include, for example, two instances of input/output logic cell (“IOL”) 115. It will be clear to those skilled in the art that, for example, the actual I/O pads that are typically connected to I/O logic cell 115 are generally not limited to the area of input/output logic cell 115.

In the example of Figure 1, an area near the center of the die (shown horizontally) (e.g., formed by areas 105, 107, and 108 shown in Figure 1) can be used for configuration, clock, and other control logic. Column 109 (shown vertically) or other columns extending from this horizontal area can be used to distribute clock and configuration signals across the width of the FPGA.

Some FPGAs utilizing the architecture shown in FIG. 1 include additional logic blocks that disrupt the mostly regular columnar structure that makes up the FPGA. The additional logic blocks may be programmable blocks and/or dedicated logic. For example, PROC 110 spans several columns of CLBs and BRAMs. PROC 110 may include a variety of components that may range from a single microprocessor to a complete programmable processing system including a microprocessor, memory controller, peripherals, etc.

In one aspect, PROC 110 is implemented as a dedicated circuit, e.g., as a hardwired processor that is manufactured as part of a die implementing the programmable circuitry of an IC. PROC 110 may represent a variety of different processor types and/or systems ranging in complexity from a single processor (e.g., a single core capable of executing program code) to an entire processor system having one or more cores, modules, cooperating processors, interfaces, etc.

On the other hand, PROC 110 is omitted from architecture 100 and may be replaced with one or more other variations of the described programmable blocks. In addition, such blocks may be used to form a "soft processor" in that individual blocks of programmable circuitry may be used to form a processor that executes program code, just as PROC 110 does.

The phrase "programmable circuitry" may refer to programmable circuit elements within an IC, such as the various programmable or configurable circuit blocks or slices described herein, and interconnect circuitry that selectively couples the various circuit blocks, slices, and/or elements according to configuration data loaded into the IC. For example, portions shown in FIG. 1 such as CLB 102 and BRAM 103 that are external to PROC 110 may be considered programmable circuitry of the IC.

In some embodiments, the functionality and connectivity of the programmable circuits are not established until the configuration data is loaded into the IC. A set of configuration data can be used to program the programmable circuits of an IC (e.g., an FPGA). In some cases, the configuration data is referred to as a "configuration bitstream". Typically, the programmable circuit will not work or function without first loading the configuration bitstream into the IC. The configuration bitstream effectively implements or instantiates a specific circuit design within the programmable circuit. The circuit design specifies, for example, the functional aspects of the programmable circuit blocks and the physical connections between the various programmable circuit blocks.

In some embodiments, "hardwired" or "hardened" circuits, i.e., circuits that are not programmable, are manufactured as part of an IC. Unlike programmable circuits, hardwired circuits or circuit blocks are not implemented after the IC is manufactured by loading a configuration bitstream. Hardwired circuits are generally considered to have, for example, dedicated circuit blocks and interconnects that operate without first loading a configuration bitstream into the IC (e.g., PROC 110).

In some cases, a hardwired circuit may have one or more operating modes that may be set or selected based on register settings or values stored in one or more memory cells within the IC. For example, the operating mode may be set by loading a configuration bitstream into the IC. Despite this capability, a hardwired circuit is not considered a programmable circuit because when a hardwired circuit is manufactured as part of an IC, the hardwired circuit is operable and has a specific function.

FIG. 1 is intended to illustrate an exemplary architecture that can be used to implement an IC that includes programmable circuits (e.g., programmable structures). For example, the number of logic blocks in a row, the relative widths of the rows, the number and order of the rows, the types of logic blocks contained in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementation methods included at the top of FIG. 1 are merely exemplary. For example, in an actual IC, no matter where the CLBs appear, more than one adjacent CLB row is typically included to facilitate efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the IC. In addition, the FPGA of FIG. 1 shows an example of a programmable IC that can employ the example of the interconnect circuit described herein. The interconnect circuit described herein can be used in other types of programmable ICs, such as CPLDs or any type of programmable IC having a programmable interconnect structure for selectively coupling logic cells.

It should be noted that the IC that can implement the method and circuit for CFR of CATV amplifier is not limited to the exemplary IC shown in FIG. 1 , and ICs having other configurations or other types of ICs can also implement the method and circuit for CFR of CATV amplifier.

Referring now to FIG. 2 , a cable network 200 is shown showing a signal path starting from a data fiber (e.g., which may include an optical fiber), passing through a remote node and arriving at an end-user location (e.g., at a premises). The cable network 200 may be part of a hybrid fiber-coaxial network, where the data fiber travels from a central headend to the remote node and the coaxial cable travels from the remote node to the end-user. In some examples, the remote node includes a remote PHY node based on the DOCSIS 3.1 standard. In some embodiments, the remote PHY node may include a baseband and digital front end (DFE) chip 202, a digital-to-analog converter (DAC) 204, a driver 206 (e.g., which may include an amplifier), an analog tilt filter 208, a power divider 210, and a CATV amplifier 212. In various examples, the baseband and DFE chip 202 may be implemented as a single chip, or as separate chips including a baseband processor chip and a separate DFE chip. In some embodiments, for example, depending on the input to the DAC 204, the DAC 204 may be implemented as an RF DAC or an IF DAC. In addition, in some embodiments, the baseband and DFE chip 202 and the DAC 204 can be implemented as a single chip (e.g., in an RFSoC device). In addition, one or more components of the remote PHY node can be implemented in a programmable logic device such as the programmable logic device of FIG. 1. As shown in FIG. 2, the data fiber is connected as an input to the baseband and DFE chip 202, and the output of the baseband and DFE chip 202 is connected as an input to the DAC 204. The power spectrum 214 (no slope) provides an example of the shape of the signal at the output of the baseband and DFE chip 202. The output of the DAC 204 is connected as an input to the driver 206, and the output of the driver 206 is connected as an input to the analog tilt filter 208. For cable applications, the analog tilt filter 208 can be used to change the gain on the signal power spectrum. In other words, the analog tilt filter 208 is used to add a slope in the signal power level on the power spectrum. The power spectrum 216 shows the slope (e.g., a positive slope in this example) in the signal at the output of the analog tilt filter 208 compared to the power spectrum 214.

In some embodiments, the output of the analog tilt filter 208 is connected to a power divider 210 as an input. As shown in Figure 2, the power divider 210 includes a 1×4 power divider with a single input and four outputs. However, in some embodiments, the power divider 210 may include a 1×2 power divider with a single input and two outputs, a cascade of 1×2 power dividers (e.g., to produce four outputs), or another type of power divider. In this example, each of the four outputs of the power divider 210 is connected to a CATV amplifier 212 as an input. Then, the output of each CATV amplifier 212 is coupled to a coaxial cable, which is further coupled to a cable modem at an end-user location (e.g., in a house). In at least some embodiments, the cable network 200 implements a "node + 0" architecture, which means that there is no additional CATV amplifier (except the CATV amplifier 212 at the remote PHY node) along the coaxial cable path between the remote PHY node and the end-user location. 2 also shows a power spectrum 218 showing the coaxial cable loss spectrum (e.g., with a negative slope), a power spectrum 219 showing the output signal of the CATV amplifier 212, and a power spectrum 220 showing the power of the signal reaching the end user location (no slope). As previously described, the analog shelving filter 208 is used to compensate for coaxial cable losses (e.g., from the CATV amplifier 212 to the cable modem at the end user location).

In at least some existing cable networks, CATV amplifiers operate in a linear region. This means that the nonlinearity at the output of the CATV amplifier is low enough that no other signal processing is required, and the signal at the output of the CATV amplifier can be directly sent to the cable modem at the end-user location via a coaxial cable for demodulation and information transmission. However, with the transition to more complex functions and the emergence of additional power consumption components associated with DOCSIS 3.1, and because the power supply to each node (e.g., each remote PHY node) is fixed, it is desirable to reduce the power consumption of other components such as CATV amplifiers. Currently, the efficiency of CATV amplifiers is about 2-3%, so, for example, a CATV amplifier with 20 watts of input power will output an output power of about one-half watt. For four CATV amplifiers (e.g., as shown in Figure 2), an input power of 100 watts will output an output power of about 2 watts. Therefore, it is highly desirable to make CATV amplifiers more efficient.

At least one option being explored to make CATV amplifiers more efficient is to operate the CATV amplifiers in a more nonlinear region. However, doing so means that, as provided in accordance with embodiments of the present disclosure, the signal at the output of the CATV amplifier may not be directly sent to the end-user location on the coaxial cable without some additional digital signal processing. For example, the embodiments disclosed herein add functionality within the baseband and DFE chip 202, as discussed in more detail below, so that even if the CATV amplifier operates in a nonlinear region, the baseband and DFE chip 202 are able to invert or change the signal so that the signal at the output of the CATV amplifier is still linear and can be conveniently demodulated by the cable modem at the end-user location. In other words, if the CATV amplifier has a nonlinearity "x", the functionality within the baseband and DFE chip 202 is configured to add an inverse nonlinearity of "1/x", which will be offset by the nonlinearity "x" of the cable TV amplifier. In this way, the signal at the output of the CATV amplifier is clean and linear. Typically, the process of adding nonlinearity in advance (e.g., such as adding an inverse nonlinearity at the baseband and DFE chip 202) is referred to as pre-distortion or pre-distortion. In the context of the baseband and DFE chip 202, the pre-distortion may be referred to as digital pre-distortion (DPD) because the distortion is added digitally. According to various embodiments, the DPD process is performed with knowledge of the type of nonlinearity "x" that a CATV amplifier (e.g., such as CATV amplifier 212) has, so that the DPD process can add the appropriate inverse nonlinearity "1/x". Therefore, according to embodiments of the present disclosure, the DPD process is the first function added within the baseband and DFE chip 202.

In addition, the second function added in the baseband and DFE chip 202 may include CFR processing. As described above, CFR processing can be used to reduce the PAPR of the signal by clipping the signal and allowing additional gain at the CFR output. By adopting CFR, the CATV amplifier can be operated closer to its 1dB compression point, thereby improving the efficiency of the CATV amplifier. In addition, when combined with DPD processing, CFR processing can be used to significantly improve DPD stability (e.g., avoid DPD divergence) and further improve the efficiency of the CATV amplifier. In various embodiments, DPD processing and CFR processing are performed with knowledge of the signal chain between the baseband and DFE chip 202 and the CATV amplifier 212, including any effects and/or distortion introduced by each of the DAC 204, the driver 206, and the analog tilt filter 208. In various embodiments, the efficiency of the CATV amplifier is improved and the power consumption is reduced by the DPD processing and CFR processing disclosed herein.

In some embodiments, functions within the baseband and DFE chip 202 (e.g., including DPD processing and CFR processing) can be largely implemented as DFE functions, where the baseband output signal is provided as an input to the DFE chip. As such, referring now to FIG. 3 , a DFE system 300 is shown, which provides a DFE design configured to perform one or more aspects of the present disclosure. In some embodiments, the DFE system 300 includes a digital upconverter (DUC) 302. In various examples, the DUC 302 is used to convert one or more data channels from baseband to a passband signal, where the passband signal includes a modulated carrier at one or more specified radio frequency or intermediate frequency (RF or IF) groups. For example, the DUC 302 achieves this by performing interpolation (e.g., increasing the sampling rate), filtering (e.g., providing spectral shaping and rejection of interpolated images), and mixing (e.g., moving the signal spectrum to a desired carrier frequency). Typically, the sampling rate at the input of the DUC 302 is low (e.g., the symbol rate of a digital communication system), while the sampling rate at the output is much higher (e.g., the input sampling rate to a DAC), which converts the digital samples into an analog waveform for further analog processing and frequency conversion.

As shown in the example of FIG. 3 , a baseband data input is provided to a DUC 302. The baseband data input includes a plurality of different carriers, denoted as s ₁ (n), s ₂ (n), s ₃ (n), s ₄ (n), s ₅ (n), and s ₆ (n). In some embodiments, the sampling rate of the baseband data input is approximately 204.8 MHz, corresponding to an OFDM symbol clock. For example, the DUC 302 generates the plurality of different carriers (e.g., from the baseband data input) by initially performing interpolation of the baseband data input, in this example, to increase the sampling rate by a factor of eight and thereby transition from a first clock domain (e.g., a 204.8 MHz clock domain) to a second clock domain (e.g., a 1638.4 MHz clock domain). After the interpolation process, each of the plurality of different carriers is mixed with a signal from a numerically controlled oscillator (NCO), each NCO having a different frequency, to shift the frequency of each of the plurality of different carriers to a desired carrier frequency. For example, carrier s ₁ (n) is mixed with a first NCO (NCO1) having a first frequency, carrier s ₂ (n) is mixed with a second NCO (NCO2) having a second frequency, carrier s ₃ (n) is mixed with a third NCO (NCO3) having a third frequency, carrier s ₄ (n) is mixed with a fourth NCO (NCO4) having a fourth frequency, carrier s ₅ (n) is mixed with a fifth NCO (NCO5) having a fifth frequency, and carrier s ₆ (n) is mixed with a sixth NCO (NCO6) having a sixth frequency. After the mixing process, each of the multiple different carriers is combined to form a composite signal c (n). Therefore, the composite signal c (n) includes each of the multiple different carriers mixed at different frequencies. In some embodiments, and as a result of the mixing process, the composite signal c (n) may appear substantially the same as the signal shown in FIG. 5A, where each of the multiple different carriers is arranged side by side in frequency. In some cases, after generating the composite signal c(n), another interpolation process may be optionally performed, which in the example of FIG. 3 may be used to increase the sampling rate of the composite signal c(n) by a factor of two, thereby transitioning from the second clock domain (e.g., the 1638.4 MHz clock domain) to the third clock domain (e.g., the 3276.8 MHz clock domain). After signal processing by the DUC 302, the composite signal c(n) is provided as an input to the DPD-CFR system 304, which will be described in more detail below. In some embodiments, the output of the DPD-CFR system 304 may undergo a complex-to-real signal conversion 306, and the output of the complex-to-real signal conversion 306 is provided as an input to a DAC (e.g., which may be the DAC 204 of FIG. 2). In addition, one or more components of the DFE system 300 may be implemented in a programmable logic device such as the programmable logic device of FIG. 1.

As previously discussed, the DPD and CFR processing and therefore the DPD-CFR system 304 functions in the case where the type of nonlinearity "x" that the CATV amplifier has is known and in the case where the signal chain between the baseband and DFE chip 202 and the CATV amplifier 212 is known so that the DPD-CFR system 304 can effectively implement appropriate DPD and CFR processing (e.g., including adding appropriate inverse nonlinearity "1/x" and reducing the PAPR of the signal). For example, the DPD-CFR system 304 can be used to model the CATV amplifier (e.g., including nonlinear effects and signal chains). In this way, the model provided by the DPD-CFR system 304 can be generated and/or updated based on the feedback data 308, where the feedback data 308 can include the output signal of the CATV amplifier (e.g., CATV amplifier 212). In some embodiments, the feedback data 308 is processed by an analog-to-digital converter (ADC) 310 and provided to the DPD/CFR adaptation engine 312 as digital feedback data 311. In various examples, based on the digital feedback data 311, the DPD/CFR adaptation engine 312 updates the DPD-CFR system 304 so that the DPD-CFR system 304 can adapt to the run-time behavior of the CATV amplifier. More specifically, in some embodiments, the DPD/CFR adaptation engine 312 can determine the configuration of filter coefficients or other units within the DPD-CFR system 304, and can generally configure CFR and DPD modules within the DPD-CFR system 304, as discussed below. Therefore, by continuously monitoring and updating the model provided by the DPD-CFR system 304 (e.g., through the feedback data 308 and the DPD/CFR adaptation engine 312), optimal DPD and CFR processing can be achieved. For example, aspects of monitoring and updating the model (e.g., such as the functions of the DPD/CFR adaptation engine 312) can be implemented as software stored in a memory (e.g., within the BRAM 103 or within another on-chip memory location) and executed by one or more on-chip processors (e.g., PROC 110). Note that in some embodiments, the baseband and DFE chip 202, DAC 204, and ADC 310 may be implemented as a single chip (e.g., in an RFSoC device). The examples of monitoring and updating the models provided above are not meant to be limiting in any way, and it will be appreciated that while other approaches are possible, embodiments of the present disclosure are not limited by any of the examples provided.

Referring now to FIG. 4A , there is shown a more detailed view of a DPD-CFR system 304 used to implement various aspects of the present disclosure. As shown, the DPD-CFR system 304 may include a digital shelving filter 402, a CFR module 404, a DPD module 406, a single sideband Hilbert filter 412, and a digital shelving equalizer 414. Note that one or more components of the DPD-CFR system 304 may be implemented in a programmable logic device such as the programmable logic device of FIG. 1 .

Still referring to FIG. 4A , the functionality of the DPD-CFR system 304 is described in more detail. For example, in some embodiments, an input signal x(n), which may include the composite signal c(n) discussed above, is provided to a digital tilt filter 402. In various cases, the digital tilt filter 402 may be used to model the analog tilt filter 208 ( FIG. 2 ). Thus, as an example, the output of the digital tilt filter 402 may be similar to the output of the analog tilt filter 208. In some embodiments, the output of the digital tilt filter 402, labeled is provided as an input to the CFR module 404. In various embodiments, the CFR module 404 may perform CFR processing to reduce the incoming signal (eg, the output of the digital tilt filter 402, ). Although the present embodiment is not limited to any particular CFR technique used by CFR module 404, exemplary CFR techniques may include: adaptive baseband, intermediate frequency (IF) clipping and filtering, peak windowing, or other suitable techniques. After CFR processing, CFR module 404 provides DPD module 406 with a signal labeled As shown in the figure, the output of the digital tilt filter 402 is also provided along the data path 421, where a delay is introduced into the signal (e.g., at block 423). For example, the output of CFR module 404 Further along the data path 427 is provided, and then the combiner 425 is used to combine the output of the CFR module 404 With delayed signal Generate signal

In some embodiments, the DPD module 406 is used to model the inverse baseband, video and harmonic components of the CATV amplifier and add them to the incoming signal. Referring to FIG. 4B , a more detailed view of the DPD module 406 is shown. As shown, the output of the CFR module 404 is provided as an input to a DPD module 406 that includes a nonlinear data path 405. In various embodiments, the nonlinear data path 405 includes a plurality of different parallel data path units, including a video bandwidth DPD data path 408, a baseband DPD data path 409, a second harmonic DPD data path 410, and a third harmonic DPD data path 411. In general, the nonlinear data path 405 is used to model the inverse nonlinear behavior of the CATV amplifier and add it to the input signal. More specifically, each different parallel data path unit of the nonlinear data path 405 is used to model a different aspect of the inverse nonlinear behavior of the CATV amplifier and add it to the input signal (e.g., the output of the CFR module 404). ). For example, the video bandwidth DPD datapath 408 can model and add an inverse nonlinear video bandwidth component, the baseband DPD datapath 409 can model and add an inverse nonlinear baseband component, the second harmonic DPD datapath 410 can model and add an inverse second harmonic component, and the third harmonic DPD datapath 411 can model and add an inverse third harmonic component. As shown, the output of each of the video bandwidth DPD datapath 408, the baseband DPD datapath 409, the second harmonic DPD datapath 410, and the third harmonic DPD datapath 411 are combined to provide a composite signal x'(n) that models the baseband, video, and harmonic components of the CATV amplifier.

Returning to FIG. 4A , the output of the nonlinear data path 405 (eg, the composite signal x′(n)) and the signal are combined to produce a signal x"(n). Thereafter, the signal x"(n) is provided as an input to a single sideband Hilbert filter 412, which may be used to further modulate the signal x'(n), and the output of the single sideband Hilbert filter 412 is provided as an input to a digital tilt equalizer 414. As an example, the digital tilt equalizer 414 may be used to model the inverse of the analog tilt filter 208 (FIG. 2) and added to the incoming signal. Thus, as an example, the output of the digital tilt equalizer 414 may not be affected by the analog tilt filter 208 (e.g., or its effects may be eliminated). As shown in FIG. 4A, in some embodiments, the input signal x(n) is also transmitted along path 416, where path 416 is a linear data path. In some examples, the data path 416 may introduce only a time delay in the input signal x(n) (e.g., at block 417). In addition, the input signal x(n) transmitted along the data path 416 bypasses the digital tilt filter 402, the CFR module 404, the DPD module 406, the single sideband Hilbert filter 412, and the digital tilt equalizer 414. In this way, the quality of the signal modulation of the input signal x(n) transmitted along the data path 416 will remain unaffected by the other elements of the DPD-CFR system 304. In addition, as shown in Figure 4A, the output of the digital tilt equalizer 414 and the time delayed input signal x(n) 419 are combined by the combiner 431 to provide an output signal z(n). Referring to Figures 2, 3 and 4A, the output z(n) of the DPD-CFR system 304 can be further processed by the RF DAC 204 and the analog tilt filter 208 to produce a signal y(n). For example, the signal y(n) can be calculated as:

Where ATF = analog shelving filter, DTE = digital shelving equalizer, the symbol ‘*’ is used to represent the mathematical convolution operation, and DTE*ATF = 1 (uniform transfer function).

Referring to FIG. 5A , an exemplary input spectrum 502 is provided. In some embodiments, the input signal x(n) ( FIG. 4A ) may include the input spectrum 502. As described above, the input spectrum 502 may include each of a plurality of different carriers mixed at different frequencies (e.g., by the DUC 302 ), as previously described, wherein each of the plurality of different carriers is arranged side by side at a full bandwidth frequency of about 66 MHz to about 1218 MHz. Referring to FIG. 5B , an exemplary output spectrum 504 is provided. In some embodiments, the output signal z(n) ( FIG. 4A ) may include the output spectrum 504. As shown in FIG. 5B , the output spectrum 504 includes one or more nonlinear components 506 that have been added to the signal by the DPD-CFR system 304. As a result of the processing performed by the DPD-CFR system 304, CATV amplifier efficiency and signal quality are improved, and power consumption is reduced.

Now with reference to Figures 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, 10B and 11, a plurality of data are shown in the figure, and the plurality of data shown indicate at least some benefits and advantages of various embodiments of the present disclosure. First with reference to Figure 6A, a curve 602 is shown therein, which shows the normalized amplitude of the tilt filter output (e.g., analog tilt filter 208) sampled over time. The graph 602 includes a first data set 604 that does not perform CFR processing. In this way, the first data set 604 exhibits a large peak value (e.g., greater than about 0.78), which may result in more nonlinearity in the CATV amplifier. The graph 602 also includes a second data set 606 that performs CFR processing, which shows a reduced peak amplitude (e.g., less than about 0.78). Therefore, the reduced peak value provided by the CFR processing improves the efficiency of the CATV amplifier. In addition, the CFR processing can be performed without sacrificing the modulation error rate (MER) performance. 6B provides a graph 608 showing a power spectrum 610 (e.g., at the output of the analog shelving filter 208) on which CFR processing has been performed, illustrating the benefit of reduced peak amplitude provided by the CFR processing. It should be noted that the data shown in FIGS. 6A and 6B include simulated data, where the analog shelving filter 208 has been replaced with a digital model for simulation purposes.

Referring to Figures 7A, 7B, and 7C, curves 702, 708, 714 are shown therein, which show the normalized amplitude of the amplifier output (e.g., CATV amplifier 212) sampled over time. In general, the data of the curves 702, 708, 714 provide verification of the effectiveness of the CFR process and may include a snapshot of feedback data (e.g., such as feedback data 308). As described above, such feedback data may include the output signal of the CATV amplifier, which the DPD/CFR adaptive engine 312 may use to update the model within the DPD-CFR system 304 so that the DPD-CFR system 304 can adapt to the behavior of the CATV amplifier during operation. In some cases, the data of the curves 702, 708, 714 may provide a snapshot of the feedback data at different CATV amplifiers so that the system can be observed and adapted in real time (e.g., via the DPD-CFR system 304) to provide consistency between different CATV amplifiers. Alternatively, in some examples, the data of curves 702, 708, 714 can provide snapshots of feedback data at different time windows at a specific CATV amplifier to observe the performance of a specific CATV amplifier over time. Now referring to FIG. 7A, graph 702 includes a first data set without CFR processing, which includes a peak 704 (e.g., having an amplitude greater than about 0.78), and can indicate more nonlinearities in the CATV amplifier. Graph 702 also includes a second data set 706 in which CFR processing is performed, which shows a reduced peak amplitude (e.g., less than about 0.78). Similarly, curve 708 (FIG. 7B) and curve 714 (FIG. 7C) show peaks 710, 716 of a data set in which CFR processing is not performed, and data sets 712, 718 in which CFR processing is performed. As previously described, the reduced peak provided by CFR processing improves the efficiency of the CATV amplifier.

Now referring to FIG. 8A, there is shown a cumulative distribution function (CCDF) curve 802 of a single carrier at 1122MHz, which shows a first CCDF curve 804 without CFR processing and a second CCDF curve 806 generated due to CFR processing. The CCDF curve is used to display the time that a signal spends at or above a given power level, where the power level is expressed in dB relative to the average signal power (e.g., crest factor). In other words, the CCDF curve is used to display the probability that a signal is equal to or higher than a given power level. Referring to FIG. 8A, the x-axis shows a dB value higher than the average signal power (e.g., crest factor), and the y-axis shows the percentage of time that a signal spends at or above the power level specified by the x-axis. Compared with the first CCDF curve 804 (without CFR), the second CCDF curve 806 (with CFR) presents a crest factor reduction of about 2dB. As a result, it is expected that the CATV amplifier will provide more consistent and more efficient performance. FIG. 8B provides a graph 808 showing a power spectrum 810 on which CFR processing has been performed, corresponding to the second CCDF curve 806 (with CFR), where the crest factor has been reduced by the CFR processing.

With reference to Fig. 9A and 9B, curves 902, 908 of CATV amplifier transfer function are shown, which show amplitude-amplitude distortion (AM/AM), wherein AM/AM distortion is used to measure the gain compression or expansion of the signal. In other words, when the CATV amplifier gain is no longer constant with the input power (e.g., when the output power is no longer linearly related to the input power), the nonlinearity of AM/AM distortion will increase. In this example, graph 902 (Fig. 9A) provides data in which CFR processing is not performed, and graph 908 (Fig. 9B) provides data in which CFR processing is performed. In addition, graph 902 includes a first curve 904 to which DPD processing is not performed and a second curve 906 to which DPD processing is performed. With reference to the first curve 904, it can be seen that a greater input power leads to an increase in compression of the output power (e.g., evidence of an increase in nonlinearity of the CATV amplifier). Using DPD processing (without CFR), the second curve 906 shows that the nonlinearity of the CATV amplifier can be substantially corrected and signal compression can be reduced. The graph 908 also includes a first graph 910 for which DPD processing is not performed and a second graph 912 for which DPD processing is performed. By performing CFR processing and reducing the PAPR (for the data shown in the graph 908), the normalized input power is limited to approximately 0.8. Referring to the first graph 910 (without DPD), the signal compression is relatively small, resulting in greater control and efficiency of the CATV amplifier. In this example, using DPD processing (with CFR), the second graph 912 shows a smaller improvement compared to the first graph 910 because the nonlinearity of the DPD processing is less corrected by limiting the input power (through the CFR processing).

10A and 10B provide exemplary DPD performance (e.g., DPD output stability performance) with and without CFR processing. FIG. 10A includes a graph 1002 that provides data where CFR processing is not performed. FIG. 10B includes a graph 1008 that provides data where CFR processing is performed. In addition, graph 1002 (without CFR) includes a first curve 1004 representing a DPD input signal and a second curve 1006 representing a DPD output signal. In this example, without CFR processing, the DPD output signal (1006) is unstable and begins to diverge, exceeding the DPD output signal range of approximately 2. As described above, greater input power results in increased compression in the output power, making the CATV amplifier more nonlinear. In order to avoid the CATV amplifier from operating in such a high power region, CFR processing can be performed. For example, graph 1008 (with CFR) includes a first curve 1010 representing a DPD input signal and a second curve 1012 representing a DPD output signal. In this example, due to the CFR processing performed, the DPD output signal (1012) is stable and does not diverge. For the data of curve 1008, a CFR of 1.3dB is applied. However, in various embodiments, the amount of CFR applied can be adjusted according to the needs of a specific CATV amplifier or a specific installation/deployment. In addition, although the present disclosure has described the advantages of DPD and CFR, it should be understood that various embodiments can adopt one or both of DPD and CFR processing. However, in at least some examples, by using DPD processing and CFR processing for a given deployment simultaneously, maximum CATV amplifier efficiency can be achieved while also avoiding DPD divergence.

Referring to FIG. 11 , a table including modulation error ratio (MER) data for a CATV amplifier is shown, which shows the effect of applying the correction provided by the DPD-CFR system 304 to the MER data. For example, MER is a metric used to quantify the performance of a digital radio (or digital TV) transmitter or receiver in a communication system using digital modulation (e.g., QAM). For the example of FIG. 11 , the CATV amplifier module under test may operate at V=34V. In order to compare the MER data with the cable industry specification (MER=41dB, 4KQAM, 76.8dbmV/75Ω), the CATV amplifier is tested using six carriers, wherein the first carrier is a 4K QAM signal with a 204MHz carrier frequency, the second carrier is a 4K QAM signal with a 396MHz carrier frequency, the third carrier is a 4K QAM signal with a 588MHz carrier frequency, the fourth carrier is a 4K QAM signal with a 786MHz carrier frequency, the fifth carrier is a 4K QAM signal with a 930MHz carrier frequency, and the sixth carrier is a 4K QAM signal with a 1122MHz carrier frequency. In the first test 1102, none of the tested carriers met the MER=41dB specification when the CATV amplifier was operated at a bias current of 440mA and without DPD or CFR correction. In the second test 1104, the first carrier did not meet the MER=41dB specification when the CATV amplifier was operated at a bias current of 440mA, with DPD correction but without CFR correction. In addition, in the second test 1104, DPD stability was reduced and DPD diverged. In the third test 1106, all tested carriers met the MER=41dB specification and avoided DPD divergence when the CATV amplifier was operated at a bias current of 440mA and DPD and CFR correction were applied. It should also be noted that by running the CATV amplifier at a bias current of 440mA (compared to some applications of running the CATV amplifier at a bias current of 530mA), the power consumption of each amplifier can be reduced by about 3 watts while maintaining MER.

Referring now to FIG. 12 , a method 1200 for performing crest factor reduction processing and digital predistortion processing in a DPD-CFR system is shown in accordance with various embodiments. The method 1200 begins at block 1202, where an input signal is received at an input of a DPD-CFR system, such as the DPD-CFR system 304 of FIG. 4A . As described above, in some embodiments, the input signal may include an input signal x(n) ( FIG. 4A ), which may also include a composite signal c(n) generated by the DUC 302 ( FIG. 3 ). In some examples, the method 1200 proceeds to block 1204, where CFR processing is performed on the input signal at a CFR module of the DPD-CFR system to generate a first output signal. For example, the CFR processing may be performed by the CFR module 404 ( FIG. 4A ). In various cases, the CFR processing is performed to reduce a peak-to-average power ratio (PAPR) of the input signal. In some embodiments, the input signal includes a signal labeled signal (FIG. 4A), and the first output signal includes a signal labeled signal (FIG. 4A). Method 1200 proceeds to block 1206, where DPD processing is performed on the first output signal at the DPD module of the DPD-CFR system to generate a DPD-CFR output signal. In some embodiments, the DPD module includes a nonlinear data path coupled to the CFR module output. In addition, the nonlinear data path of the DPD module may include the nonlinear data path 406 of FIG. 4B. In this way, the nonlinear data path may include a plurality of parallel data path units. In some examples, the plurality of parallel data path units include a video bandwidth DPD data path 404, a baseband DPD data path 406, a second harmonic DPD data path 408, and a third harmonic DPD data path 410. In some examples, each different parallel data path unit may be used to add different aspects of the inverse nonlinear behavior of the CATV amplifier to the input signal. In some embodiments, a combiner combines the output of each of the plurality of parallel data path units to generate a composite signal x'(n) (FIG. 4B), wherein the composite signal x'(n) models the baseband, video, and harmonic components of the CATV amplifier. In various embodiments, method 1200 proceeds to block 1208, where the DPD-CFR output signal is provided to a CATV amplifier (e.g., such as CATV amplifier 212 of FIG. 2 ). According to an embodiment of the present disclosure, the DPD-CFR output signal is configured to reduce the PAPR of the signal and compensate for multiple nonlinear components of the CATV amplifier. Method 1200 may then proceed to block 1210, where the configuration of the DPD-CFR system may be updated using feedback data received from the output of the CATV amplifier (e.g., feedback data 308 of FIG. 3 ). It should be appreciated that additional method steps may be implemented before, during, and after method 1200, and that some of the method steps described above may be replaced or eliminated according to various embodiments of method 1200 without departing from the scope of the present invention.

It should be noted that the various configurations (e.g., the components of the cable network 200, DFE system 300, and DPD-CFR system 304 in FIG. 4B, the number of parallel data path units, and other features and components shown in the drawings) are exemplary only and are not intended to limit the contents specifically recited in the appended claims. Those skilled in the art will understand that other configurations may be used. In addition, although an exemplary cable network 200 is shown, the DPD-CFR system disclosed herein may be used in other communication systems, for example, where the other communication systems deploy amplifiers that exhibit harmful nonlinear behavior.

As described above, the cable industry is deploying new high data rate and broadband remote PHY nodes based on the DOCSIS 3.1 standard to meet the demand for higher data rates for Internet, telephone and video services. DOCSIS 3.1 supports 4096 (4K) quadrature amplitude modulation (QAM) and uses orthogonal frequency division multiplexing (OFDM). As a result, the transmission signal quality requirements of DOCSIS 3.1 are higher than those of the current standard DOCSIS 3.0. Due to the more complex functions associated with DOCSIS 3.1, cable television (CATV) amplifiers may operate in a nonlinear region. The nonlinear effects of CATV amplifiers will greatly reduce the quality of the transmitted signal. In addition, the new components that provide high data rates and more complex functions of DOCSIS 3.1 will also consume power themselves. However, since the power supply power to each node (e.g., each remote PHY node) is fixed, the power consumption of other components (e.g., CATV amplifiers) should be reduced. Therefore, while it is desirable to provide the advanced performance of DOCSIS 3.1, it is challenging to simultaneously provide improved transmit signal quality and reduce power consumption of other components (eg, CATV amplifiers).

In at least some prior art, a shelving equalizer (shelving filter) with a deep attenuation of up to 22 dB on the 1.2 GHz cable spectrum is implemented in the analog transmission path to compensate for the loss of the coaxial cable (e.g., from the CATV amplifier to the cable modem). However, compared with the current DOCSIS 3.0 standard, the DOCSIS3.1 waveform using 4K QAM OFDM modulation shows a higher peak-to-average power ratio (PAPR). In this way, for the same RMS power output of the CATV amplifier in DOCSIS 3.0, the peak of the DOCSIS 3.1 waveform will be located in the nonlinear region of the CATV amplifier. Therefore, the quality of the transmitted signal will decrease. Digital pre-distortion (DPD) can be used to improve the signal quality of the CATV amplifier, for example, by making the CATV operate in a more efficient area. DPD has been used in wireless communication technology, in which the signal bandwidth of the wireless communication technology is much narrower than the signal bandwidth used for wired communication technology. In addition, in wireless communication, the harmonics of the nonlinear effects of the wireless components will not fall into the signal bandwidth. In this way, the DPD used for wireless communication only needs to model the nonlinear components projected around the baseband frequency. However, for cable applications, the harmonics of the nonlinear effects of CATV amplifier signals can fall into the signal bandwidth. Therefore, the DPD implementation scheme for cable applications should be modeled for the harmonic components of the nonlinear effects of CATV amplifiers. In addition, the tilt equalizer with deep attenuation cannot be implemented in the digital domain, and the implementation scheme of the digital tilt equalizer will reduce the transmission waveform quality of the low-frequency carrier because of the limited digital resolution of the digital-to-analog converter (DAC). For integrated circuit (IC) solutions, it has been found that the DPD data path implemented in the digital front end (DFE) chip can provide a solution for modeling the harmonic components of the nonlinear effects of CATV amplifiers and the deep attenuation on the transmission spectrum in the CATV amplifier. Therefore, the embodiments of the present disclosure provide the improved transmission signal quality and reduced power consumption of the CATV amplifier.

In view of the above general understanding, various embodiments of the method and circuit for predistortion of CATV amplifiers are generally described below. Because one or more of the above embodiments are illustrated by using a specific type of IC, a detailed description of such IC is provided below. However, it should be understood that other types of ICs may benefit from one or more embodiments described herein.

A programmable logic device ("PLD") is a well-known integrated circuit that can be programmed to perform a specified logic function. One type of PLD, a field programmable gate array ("FPGA"), typically includes an array of programmable chips. These programmable chips may include, for example, input/output blocks ("IOBs"), configurable logic blocks ("CLBs"), application specific random access memory blocks ("BRAMs"), multipliers, digital signal processing blocks ("DSPs"), processors, clock managers, delay locked loops ("DLLs"), etc. As used herein, "includes" and "comprising" mean including without limitation.

Each programmable slice typically includes programmable interconnects and programmable logic. The programmable interconnects typically include many interconnect lines of different lengths interconnected by programmable interconnect points ("PIPs"). Programmable logic uses programmable cells to implement user-designed logic, which may include, for example, function generators, registers, arithmetic logic, etc.

The programmable interconnect and programmable logic can usually be programmed by loading a stream of configuration data into internal configuration memory cells, which define how the programmable cells are configured. The configuration data can be read from a memory (e.g., from an external PROM) or written to the FPGA by an external device. The collective state of the individual memory cells then determines the functionality of the FPGA.

Another type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD contains two or more "functional blocks" that are connected together and to input/output ("I/O") resources through an interconnect switch matrix. Each functional block of a CPLD includes a two-level AND/OR structure similar to that used in programmable logic array ("PLA") and programmable array logic ("PAL") devices. In a CPLD, configuration data is typically stored on-chip in nonvolatile memory. In some CPLDs, configuration data is stored on-chip in nonvolatile memory and then downloaded to volatile memory as part of the initial configuration (programming) sequence.

Typically, for each of these programmable logic devices ("PLDs"), the functionality of the device is controlled for this purpose by configuration data provided to the device. The configuration data may be stored in volatile memory (e.g., static memory cells common in FPGAs and some CPLDs), non-volatile memory (e.g., FLASH memory in some CPLDs), or any other type of memory cell.

Other PLDs are programmed by applying a processing layer, such as a metal layer, that interconnects the various elements on the device in a programmable manner. These PLDs are referred to as mask programmable devices. PLDs may also be implemented in other ways (e.g., using fuse or anti-fuse technology). The terms "PLD" and "programmable logic device" include, but are not limited to, these exemplary devices, as well as devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch structure that programmably interconnects the hard-coded transistor logic.

As described above, advanced FPGAs can include several different types of programmable logic blocks in an array. For example, FIG. 1 shows an exemplary FPGA architecture 100. FPGA architecture 100 includes a large number of different programmable slices, including multi-gigabit transceivers ("MGTs") 101, configurable logic blocks ("CLBs") 102, random access memory blocks ("BRAMs") 103, input/output blocks ("IOBs") 104, configuration and clock logic ("CONFIG/CLOCKS") 105, digital signal processing blocks ("DSPs") 106, dedicated input/output blocks ("I/Os") 107 (e.g., configuration ports and clock ports), and other programmable logic 108, such as digital clock managers, analog-to-digital converters, system monitoring logic, etc. Some FPGAs also include dedicated processor blocks ("PROCs") 110. In some embodiments, FPGA architecture 100 includes an RF data converter subsystem that includes multiple radio frequency analog-to-digital converters (RF-ADCs) and multiple radio frequency digital-to-analog converters (RF-DACs). In various examples, the RF-ADC and RF-DAC can be configured individually for real data, or can be configured in pairs for real and imaginary I/Q data.In at least some examples, FPGA architecture 100 can implement an RFSoC device.

In some FPGAs, each programmable slice may include at least one programmable interconnect cell ("INT") 111 having connections to input and output terminals 120 of programmable logic cells within the same slice, as shown in the example included at the top of FIG. Each programmable interconnect cell 111 may also include connections to interconnect segments 122 of adjacent programmable interconnect cells in the same slice or other slices. Each programmable interconnect cell 111 may also include connections to interconnect segments 124 of general routing resources between logic blocks (not shown). General routing resources may include routing channels between logic blocks (not shown) and switch blocks (not shown) for connecting interconnect segments, wherein the logic blocks include interconnect segments (e.g., interconnect segments 124). Interconnect segments of general routing resources (e.g., interconnect segments 124) may span one or more logic blocks. Programmable interconnect cells 111, together with general routing resources, implement a programmable interconnect structure ("programmable interconnect") for the FPGA shown.

In an exemplary embodiment, CLB 102 may include configurable logic elements (“CLEs”) 112 that may be programmed to implement user logic, and a single programmable interconnect cell (“INT”) 111. BRAM 103 may include a BRAM logic cell (“BRL”) 113 in addition to one or more programmable interconnect cells. Typically, the number of interconnect cells included in a slice depends on the height of the slice. In the illustrated example, the BRAM slice has the same height as the five CLBs, but other numbers (e.g., four) may also be used. In addition to an appropriate number of programmable interconnect cells, DSP slice 106 may also include a DSP logic cell (“DSPL”) 114. In addition to one instance of programmable interconnect cell 111, IOB 104 may also include, for example, two instances of input/output logic cell (“IOL”) 115. It will be clear to those skilled in the art that, for example, the actual I/O pads that are typically connected to I/O logic cell 115 are generally not limited to the area of input/output logic cell 115.

In the example of Figure 1, an area near the center of the die (shown horizontally) (e.g., formed by areas 105, 107, and 108 shown in Figure 1) can be used for configuration, clock, and other control logic. Column 109 (shown vertically) or other columns extending from this horizontal area can be used to distribute clock and configuration signals across the width of the FPGA.

Some FPGAs utilizing the architecture shown in FIG. 1 include additional logic blocks that disrupt the mostly regular columnar structure that makes up the FPGA. The additional logic blocks may be programmable blocks and/or dedicated logic. For example, PROC 110 spans several columns of CLBs and BRAMs. PROC 110 may include a variety of components that may range from a single microprocessor to a complete programmable processing system including a microprocessor, memory controller, peripherals, etc.

In one aspect, PROC 110 is implemented as a dedicated circuit, e.g., as a hardwired processor that is manufactured as part of a die implementing the programmable circuitry of an IC. PROC 110 may represent a variety of different processor types and/or systems ranging in complexity from a single processor (e.g., a single core capable of executing program code) to an entire processor system having one or more cores, modules, cooperating processors, interfaces, etc.

On the other hand, PROC 110 is omitted from architecture 100 and may be replaced with one or more other variations of the described programmable blocks. In addition, such blocks may be used to form a "soft processor" in that individual blocks of programmable circuitry may be used to form a processor that executes program code, just as PROC 110 does.

The phrase "programmable circuitry" may refer to programmable circuit elements within an IC, such as the various programmable or configurable circuit blocks or slices described herein, and interconnect circuitry that selectively couples the various circuit blocks, slices, and/or elements according to configuration data loaded into the IC. For example, portions shown in FIG. 1 such as CLB 102 and BRAM 103 that are external to PROC 110 may be considered programmable circuitry of the IC.

In some embodiments, the functionality and connectivity of the programmable circuits are not established until the configuration data is loaded into the IC. A set of configuration data can be used to program the programmable circuits of an IC (e.g., an FPGA). In some cases, the configuration data is referred to as a "configuration bitstream". Typically, the programmable circuit will not work or function without first loading the configuration bitstream into the IC. The configuration bitstream effectively implements or instantiates a specific circuit design within the programmable circuit. The circuit design specifies, for example, the functional aspects of the programmable circuit blocks and the physical connections between the various programmable circuit blocks.

In some embodiments, "hardwired" or "hardened" circuits, i.e., circuits that are not programmable, are manufactured as part of an IC. Unlike programmable circuits, hardwired circuits or circuit blocks are not implemented after the IC is manufactured by loading a configuration bitstream. Hardwired circuits are generally considered to have, for example, dedicated circuit blocks and interconnects that operate without first loading a configuration bitstream into the IC (e.g., PROC 110).

In some cases, a hardwired circuit may have one or more operating modes that may be set or selected based on register settings or values stored in one or more memory cells within the IC. For example, the operating mode may be set by loading a configuration bitstream into the IC. Despite this capability, a hardwired circuit is not considered a programmable circuit because when a hardwired circuit is manufactured as part of an IC, it is operational and has a specific function.

As described above, FIG. 1 is intended to illustrate an exemplary architecture that can be used to implement an IC that includes programmable circuits (e.g., programmable structures). For example, the number of logic blocks in a row, the relative widths of the rows, the number and order of the rows, the types of logic blocks contained in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementation methods included at the top of FIG. 1 are merely exemplary. For example, in an actual IC, no matter where the CLBs appear, more than one adjacent CLB row is typically included to facilitate efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the IC. In addition, the FPGA of FIG. 1 shows an example of a programmable IC that can employ the example of the interconnect circuit described herein. The interconnect circuit described herein can be used in other types of programmable ICs, such as CPLDs or any type of programmable IC having a programmable interconnect structure for selectively coupling logic cells.

It should be noted that the IC that can implement the method and circuit for CFR of CATV amplifier is not limited to the exemplary IC shown in FIG. 1 , and ICs having other configurations or other types of ICs can also implement the method and circuit for CFR of CATV amplifier.

Referring now to FIG. 2 , a cable network 200 is shown showing a signal path starting from a data fiber (e.g., which may include an optical fiber), passing through a remote node and arriving at an end-user location (e.g., at a premises). The cable network 200 may be part of a hybrid fiber-coaxial network, where the data fiber travels from a central headend to the remote node and the coaxial cable travels from the remote node to the end-user. In some examples, the remote node includes a remote PHY node based on the DOCSIS 3.1 standard. In some embodiments, the remote PHY node may include a baseband and digital front end (DFE) chip 202, a digital-to-analog converter (DAC) 204, a driver 206 (e.g., which may include an amplifier), an analog tilt filter 208, a power divider 210, and a CATV amplifier 212. In various examples, the baseband and DFE chip 202 may be implemented as a single chip, or as separate chips including a baseband processor chip and a separate DFE chip. In some embodiments, for example, depending on the input to the DAC 204, the DAC 204 may be implemented as an RF DAC or an IF DAC. In addition, in some embodiments, the baseband and DFE chip 202 and the DAC 204 can be implemented as a single chip (e.g., in an RFSoC device). In addition, one or more components of the remote PHY node can be implemented in a programmable logic device such as the programmable logic device of FIG. 1. As shown in FIG. 2, the data fiber is connected as an input to the baseband and DFE chip 202, and the output of the baseband and DFE chip 202 is connected as an input to the DAC 204. The power spectrum 214 (no slope) provides an example of the shape of the signal at the output of the baseband and DFE chip 202. The output of the DAC 204 is connected as an input to the driver 206, and the output of the driver 206 is connected as an input to the analog tilt filter 208. For cable applications, the analog tilt filter 208 can be used to change the gain on the signal power spectrum. In other words, the analog tilt filter 208 is used to add a slope in the signal power level on the power spectrum. The power spectrum 216 shows the slope (e.g., a positive slope in this example) in the signal at the output of the analog tilt filter 208 compared to the power spectrum 214.

In some embodiments, the output of the analog tilt filter 208 is connected to a power divider 210 as an input. As shown in Figure 2, the power divider 210 includes a 1×4 power divider with a single input and four outputs. However, in some embodiments, the power divider 210 may include a 1×2 power divider with a single input and two outputs, a cascade of 1×2 power dividers (e.g., to produce four outputs), or another type of power divider. In this example, each of the four outputs of the power divider 210 is connected to a CATV amplifier 212 as an input. Then, the output of each CATV amplifier 212 is coupled to a coaxial cable, which is further coupled to a cable modem at an end-user location (e.g., in a house). In at least some embodiments, the cable network 200 implements a "node + 0" architecture, which means that there is no additional CATV amplifier (except the CATV amplifier 212 at the remote PHY node) along the coaxial cable path between the remote PHY node and the end-user location. 2 also shows a power spectrum 218 showing the coaxial cable loss spectrum (e.g., with a negative slope), a power spectrum 219 showing the output signal of the CATV amplifier 212, and a power spectrum 220 showing the power of the signal reaching the end user location (no slope). As previously described, the analog shelving filter 208 is used to compensate for coaxial cable losses (e.g., from the CATV amplifier 212 to the cable modem at the end user location).

In at least some existing cable networks, CATV amplifiers operate in a linear region. This means that the nonlinearity at the output of the CATV amplifier is low enough that no other signal processing is required, and the signal at the output of the CATV amplifier can be directly sent to the cable modem at the end-user location via a coaxial cable for demodulation and information transmission. However, with the transition to more complex functions and the emergence of additional power consumption components associated with DOCSIS 3.1, and because the power supply to each node (e.g., each remote PHY node) is fixed, it is desirable to reduce the power consumption of other components such as CATV amplifiers. Currently, the efficiency of CATV amplifiers is about 2-3%, so, for example, a CATV amplifier with 20 watts of input power will output an output power of about one-half watt. For four CATV amplifiers (e.g., as shown in Figure 2), an input power of 100 watts will output an output power of about 2 watts. Therefore, it is highly desirable to make CATV amplifiers more efficient.

At least one option being explored to make CATV amplifiers more efficient is to operate the CATV amplifiers in a more nonlinear region. However, doing so means that, as provided in accordance with embodiments of the present disclosure, the signal at the output of the CATV amplifier may not be directly sent to the end-user location on the coaxial cable without some additional digital signal processing. For example, the embodiments disclosed herein add functionality within the baseband and DFE chip 202, as discussed in more detail below, so that even if the CATV amplifier operates in a nonlinear region, the baseband and DFE chip 202 are able to invert or change the signal so that the signal at the output of the CATV amplifier is still linear and can be conveniently demodulated by the cable modem at the end-user location. In other words, if the CATV amplifier has a nonlinearity "x", the functionality within the baseband and DFE chip 202 is configured to add an inverse nonlinearity of "1/x", which will be offset by the nonlinearity "x" of the cable TV amplifier. In this way, the signal at the output of the CATV amplifier is clean and linear. Typically, the process of adding nonlinearity in advance (e.g., such as adding an inverse nonlinearity at the baseband and DFE chip 202) is referred to as pre-distortion or pre-distortion. In the context of the baseband and DFE chip 202, the pre-distortion may be referred to as digital pre-distortion (DPD) because the distortion is added digitally. According to various embodiments, the DPD process is performed with knowledge of the type of nonlinearity "x" that a CATV amplifier (e.g., such as CATV amplifier 212) has, so that the DPD process can add the appropriate inverse nonlinearity "1/x". In addition, the DPD process is performed with knowledge of the signal chain between the baseband and DFE chip 202 and the CATV amplifier 212, including any effects and/or distortion introduced by each of the DAC 204, the driver 206, and the analog shelving filter 208. In various embodiments, CATV amplifier efficiency is improved and power consumption is reduced through the DPD process disclosed herein.

In some embodiments, functions within the baseband and DFE chip 202 (configured to add inverse nonlinearity) can be largely implemented as DFE functions, where the baseband output signal is provided as an input to the DFE chip. As such, reference is now made to FIG. 3 , which shows a DFE system 300 that provides a DFE design configured to perform one or more aspects of the present disclosure. In some embodiments, the DFE system 300 includes a digital upconverter (DUC) 302. In various examples, the DUC 302 is used to convert one or more data channels from baseband to a passband signal, where the passband signal includes a modulated carrier at one or more specified radio frequency or intermediate frequency (RF or IF) groups. For example, the DUC 302 achieves this by performing interpolation (e.g., increasing the sampling rate), filtering (e.g., providing spectral shaping and rejection of interpolated images), and mixing (e.g., moving the signal spectrum to a desired carrier frequency). Typically, the sampling rate at the input of the DUC 302 is low (e.g., the symbol rate of a digital communication system), while the samples at the output are much higher (e.g., the input sampling rate to the DAC), which converts the digital samples to an analog waveform for further analog processing and frequency conversion.

As shown in the example of FIG. 3 , a baseband data input is provided to a DUC 302. The baseband data input includes a plurality of different carriers, denoted as s ₁ (n), s ₂ (n), s ₃ (n), s ₄ (n), s ₅ (n), and s ₆ (n). In some embodiments, the sampling rate of the baseband data input is approximately 204.8 MHz, corresponding to an OFDM symbol clock. For example, the DUC 302 generates the plurality of different carriers (e.g., from the baseband data input) by initially performing interpolation of the baseband data input, in this example, to increase the sampling rate by a factor of eight and thereby transition from a first clock domain (e.g., a 204.8 MHz clock domain) to a second clock domain (e.g., a 1638.4 MHz clock domain). After the interpolation process, each of the plurality of different carriers is mixed with a signal from a numerically controlled oscillator (NCO), each NCO having a different frequency, to shift the frequency of each of the plurality of different carriers to a desired carrier frequency. For example, carrier s ₁ (n) is mixed with a first NCO (NCO1) having a first frequency, carrier s ₂ (n) is mixed with a second NCO (NCO2) having a second frequency, carrier s ₃ (n) is mixed with a third NCO (NCO3) having a third frequency, carrier s ₄ (n) is mixed with a fourth NCO (NCO4) having a fourth frequency, carrier s ₅ (n) is mixed with a fifth NCO (NCO5) having a fifth frequency, and carrier s ₆ (n) is mixed with a sixth NCO (NCO6) having a sixth frequency. After the mixing process, each of the multiple different carriers is combined to form a composite signal c (n). Therefore, the composite signal c (n) includes each of the multiple different carriers mixed at different frequencies. In some embodiments, and as a result of the mixing process, the composite signal c (n) may appear substantially the same as the signal shown in FIG. 5A, where each of the multiple different carriers is arranged side by side in frequency. In some cases, after generating the composite signal c(n), another interpolation process may be optionally performed, which in the example of FIG. 3 may be used to increase the sampling rate of the composite signal c(n) by a factor of two, thereby transitioning from the second clock domain (e.g., the 1638.4 MHz clock domain) to the third clock domain (e.g., the 3276.8 MHz clock domain). After signal processing by the DUC 302, the composite signal c(n) is provided as an input to the DPD-CFR system 304, which will be described in more detail below. In some embodiments, the output of the DPD-CFR system 304 may undergo a complex-to-real signal conversion 306, and the output of the complex-to-real signal conversion 306 is provided as an input to a DAC (e.g., which may be the DAC 204 of FIG. 2). In addition, one or more components of the DFE system 300 may be implemented in a programmable logic device such as the programmable logic device of FIG. 1.

As previously discussed, DPD and therefore DPD system 304 functions in the knowledge of the type of nonlinearity "x" that the CATV amplifier has and in the knowledge of the signal chain between the baseband and DFE chip 202 and the CATV amplifier 212, so that the DPD system 304 can effectively implement appropriate DPD processing (e.g., including adding the appropriate inverse nonlinearity "1/x"). For example, the DPD system 304 can be used to model the CATV amplifier (e.g., including nonlinear effects and signal chains). In this way, the model provided by the DPD system 304 can be generated and/or updated based on feedback data 308, where the feedback data 308 can include the output signal of the CATV amplifier (e.g., CATV amplifier 212). In some embodiments, the feedback data 308 is processed by an analog-to-digital converter (ADC) 310 and provided to the DPD adaptation engine 312 as digital feedback data 311. In various examples, based on the digital feedback data 311, the DPD adaptation engine 312 updates the DPD system 304 so that the DPD system 304 can adapt to the run-time behavior of the CATV amplifier. More specifically, in some embodiments, the DPD adaptation engine 312 may determine the configuration of filter coefficients or other units within the DPD system 304, and may generally configure the DPD module within the DPD system 304, as discussed below. Thus, by continuously monitoring and updating the model provided by the DPD system 304 (e.g., via feedback data 308 and the DPD adaptation engine 312), optimal DPD processing may be achieved. By way of example, aspects of monitoring and updating the model (e.g., such as the functionality of the DPD adaptation engine 312) may be implemented as software stored in a memory (e.g., within a BRAM 103 or within another on-chip memory location) and executed by one or more on-chip processors (e.g., PROC 110). Note that in some embodiments, the baseband and DFE chip 202, DAC 204, and ADC 310 may be implemented as a single chip (e.g., in an RFSoC device). The examples of monitoring and updating the models provided above are not meant to be limiting in any way, and it will be appreciated that, although other approaches are possible, embodiments of the present disclosure are not limited by any of the examples provided.

Referring now to FIG. 4A , a more detailed view of the DPD system 304 described above for implementing various aspects of the present disclosure is shown. As described above, the DPD system 304 can be used to model the nonlinear effects of a CATV amplifier. In this way, a model provided by the DPD system 304 can be generated and/or updated based on feedback data (e.g., such as feedback data 308), wherein the feedback data may include an output signal of the CATV amplifier processed by an ADC (e.g., such as ADC 310), and the feedback data may be provided to a DPD adaptation engine 312 so that the DPD system 304 can adapt to the nonlinear behavior of the CATV amplifier. Therefore, the DPD system 304 model of the nonlinear effects of the CATV amplifier can be used to implement various features of the DPD system 304 (e.g., digital tilt filter 402, nonlinear data path 405, single sideband Hilbert filter 412, and digital tilt equalizer 414). Note that one or more components of the DPD system 304 can be implemented in a programmable logic device such as the programmable logic device of FIG. 1 .

Still referring to FIG. 4A , the functionality of the DPD system 304 is described in more detail. For example, in some embodiments, an input signal x(n), which may include the composite signal c(n) discussed above, is provided to a digital tilt filter 402. In various cases, the digital tilt filter 402 may be used to model the analog tilt filter 208 ( FIG. 2 ). Thus, as an example, the output of the digital tilt filter 402 may be similar to the output of the analog tilt filter 208. In some embodiments, the output of the digital tilt filter 402 is provided as an input to a nonlinear data path 405, which includes a plurality of different parallel data path units, including a video bandwidth DPD data path 404, a baseband DPD data path 406, a second harmonic DPD data path 408, and a third harmonic DPD data path 410. In general, the nonlinear data path 405 is used to model the inverse nonlinear behavior of the CATV amplifier and add it to the input signal. More specifically, each different parallel data path unit of the nonlinear data path 405 is used to model a different aspect of the inverse nonlinear behavior of the CATV amplifier and add it to the input signal (e.g., the output of the digital shelving filter 402). For example, the video bandwidth DPD data path 404 can model and add an inverse nonlinear video bandwidth component, the baseband DPD data path 406 can model and add an inverse nonlinear baseband component, the second harmonic DPD data path 408 can model and add an inverse nonlinear second harmonic component, and the third harmonic DPD data path 410 can model and add an inverse third harmonic component. As shown, the output of each of the video bandwidth DPD data path 404, the baseband DPD data path 406, the second harmonic DPD data path, and the third harmonic DPD data path 410 are then combined to provide a composite signal x'(n) that models the baseband, video, and harmonic components of the CATV amplifier.

In some embodiments, the output of the nonlinear data path 405 (e.g., the composite signal x'(n)) is provided as an input to a single sideband Hilbert filter 412, which can be used to further modulate the composite signal x'(n), and the output of the single sideband Hilbert filter 412 is provided as an input to a digital tilt equalizer 414. For example, the digital tilt equalizer 414 can be used to model the inverse of the analog tilt filter 208 (Figure 2) and add it to the input signal. Thus, for example, the output of the digital tilt equalizer 414 may not be affected by the analog tilt filter 208 (e.g., or the effect may be eliminated). As shown in Figure 4, in some embodiments, the DPD input signal x(n) is also transmitted along a path 416, where the path 416 is a linear data path. In some examples, the data path 416 may introduce only a time delay (e.g., at block 417) in the DPD input signal x(n). In addition, the DPD input signal x(n) transmitted along the data path 416 bypasses the digital shelving filter 402, the nonlinear data path 405, the single sideband Hilbert filter 412, and the digital shelving equalizer 414. Thus, the quality of the signal modulation of the DPD input signal x(n) transmitted along the data path 416 remains unaffected by the other elements of the DPD system 304. In addition, as shown in FIG4 , the output of the digital shelving equalizer 414 and the delayed DPD input signal x(n) 419 are combined to provide the DPD output signal y(n).

Referring to FIG. 5A , an exemplary DPD input spectrum 502 is provided. In some embodiments, the DPD input signal x(n) ( FIG. 4 ) may include the DPD input spectrum 502. As described above, the DPD input spectrum 502 may include each of a plurality of different carriers mixed at different frequencies (e.g., by the DUC 302), as previously described, wherein each of the plurality of different carriers is arranged side by side over a full bandwidth frequency of about 66 MHz to about 1218 MHz. Referring to FIG. 5B , an exemplary DPD output spectrum 504 is provided. In some embodiments, the DPD output signal y(n) ( FIG. 4A ) may include the DPD output spectrum 504. Referring to FIG. 5B , the DPD output spectrum 504 includes one or more nonlinear components 506 that have been added to the signal by the DPD system 304. As described in more detail below, and as a result of the processing performed by the DPD system 304, CATV amplifier efficiency and signal quality are improved and power consumption is reduced.

Referring now to FIGS. 13-16 , equations including graphical representations are shown showing how each of the different parallel data path elements of the nonlinear data path 405 ( FIG. 4A ) are derived, for example, as a function of the DPD input signal x(n) ( FIG. 4A ). For example, FIG. 13 provides an equation for deriving an inverse nonlinear baseband component corresponding to the baseband DPD data path 406, which is represented as:

FIG. 14 provides an equation for deriving the inverse non-linear video bandwidth component corresponding to the video bandwidth DPD data path 404, which is expressed as:

FIG. 15 provides an equation for deriving the inverse second harmonic component corresponding to the second harmonic DPD data path 408, which is expressed as:

FIG. 16 provides an equation for deriving the inverse third harmonic component corresponding to the third harmonic DPD data path 410, which is expressed as:

Now, with reference to FIGS. 17-23, a plurality of data indicating at least some benefits and advantages of various embodiments of the present disclosure are shown. First, with reference to FIG. 17, a power spectrum 1700 of a single carrier is shown, which shows the nonlinear effects of a CATV amplifier. The power spectrum 1700 and the power spectrum of FIGS. 18-22 are generated by a spectrum analyzer using a resolution bandwidth of 100kHz and a video bandwidth of 1MHz. In this example, the carrier frequency of the single carrier is equal to 254MHz, the CATV amplifier operates at V=34V, its bias current=320mA, and the CATV amplifier output=76dbmV. In some embodiments, the waveform shown for the power spectrum 1700 is a 4K QAM DOCSIS 3.1 waveform. As shown in FIG. 17, the power spectrum 1700 also includes a nonlinear baseband component 1704, a nonlinear video bandwidth component 1706, a second harmonic component 1708, and a third harmonic component 1710. As described above, the power spectrum 1700 is for a single carrier. However, as previously described, it is considered that multiple different carriers are arranged side by side in frequency. In this case, the nonlinear components of the power spectrum 1700 (eg, the nonlinear baseband component 1704, the nonlinear video bandwidth component 1706, the second harmonic component 1708, and the third harmonic component 1710) will certainly affect and deteriorate the power spectra of adjacent carriers.

Referring now to FIG. 18 , there is shown a power spectrum 1700 (including the nonlinear effects of the CATV amplifier) and a power spectrum 1800 superimposed on the power spectrum 1700, showing the result of applying the baseband DPD correction. In other words, the power spectrum 1800 shows the beneficial effect of adding the inverse nonlinear baseband component through the baseband DPD data path 406 (e.g., at the output of the CATV amplifier). Specifically, as shown in FIG. 18 , and as a result of applying the baseband DPD correction, the nonlinear baseband component 1704 of the power spectrum 1700 has been corrected (removed), as shown in component 1802 of the power spectrum 1800. In the example of FIG. 18 , as shown by arrow 1804, the baseband DPD correction brings about an improvement of about 10 dB in the power spectrum 1800.

FIG. 19 shows power spectrum 1700 (including the nonlinear effects of the CATV amplifier) and power spectrum 1900 superimposed on power spectrum 1700, showing the result of applying the second harmonic DPD correction. In other words, power spectrum 1900 shows the beneficial effect of adding the inverse second harmonic component through second harmonic DPD data path 408 (e.g., at the output of the CATV amplifier). Specifically, as shown in FIG. 19, and as a result of applying the second harmonic correction, the second harmonic component 1708 of power spectrum 1700 has been corrected (removed), as shown in component 1902 of power spectrum 1900. As shown in the example of FIG. 19, the second harmonic DPD correction can bring about an improvement of about 5dB in power spectrum 1900.

Referring to FIG. 20 , there is shown a power spectrum 1700 (including the nonlinear effects of the CATV amplifier) and a power spectrum 2000 superimposed on the power spectrum 1700, showing the result of applying the third harmonic DPD correction. In other words, the power spectrum 2000 shows the beneficial effect of adding the inverse third harmonic component through the third harmonic DPD data path 410 (e.g., at the output of the CATV amplifier). Specifically, as shown in FIG. 20 , and as a result of applying the third harmonic correction, the third harmonic component 1710 of the power spectrum 1700 has been corrected (removed), as shown in component 2002 of the power spectrum 2000. As shown in the example of FIG. 20 , the third harmonic DPD correction brings about an improvement of about 5 dB in the power spectrum 2000.

Referring to FIG. 21 , a power spectrum 2100 of two carriers 2103, 2105 is shown, which illustrates the nonlinear effects of the CATV amplifier. FIG. 21 also includes a power spectrum 2102 superimposed on the power spectrum 2100, illustrating the result of applying baseband DPD correction, and a power spectrum 2104 superimposed on the power spectra 2100 and 2102, illustrating the result of applying baseband DPD correction and video bandwidth DPD correction. In other words, the power spectrum 2102 illustrates the beneficial effect of adding an inverse nonlinear baseband component through the baseband DPD data path 406 (e.g., at the output of the CATV amplifier). Similarly, the power spectrum 2104 illustrates the beneficial effect of adding an inverse nonlinear baseband component through the baseband DPD data path 406 and adding an inverse nonlinear video bandwidth component through the video bandwidth DPD data path 404 (e.g., at the output of the CATV amplifier). As a result of applying baseband DPD correction alone (power spectrum 2102), the power spectrum 2102 illustrates the correction (e.g., as indicated by arrow 2112) compared to the power spectrum 2100. Moreover, as a result of applying the baseband DPD correction and the video bandwidth DPD correction (power spectrum 2104), the power spectrum 2104 shows the correction (e.g., as shown by arrows 2106 and 2110) compared to the power spectrum 2100. Specifically, the improvement shown by the power spectrum 2104 in the area shown by arrow 2110 is particularly significant compared to the area shown by arrow 2108 (e.g., before applying the baseband DPD correction and the video bandwidth DPD correction). This is because the carrier 2105 has a higher power, resulting in a higher level of nonlinearity. As such, the carrier 2105 will benefit more from the correction provided by the DPD system 304.

FIG. 22 shows a power spectrum 2200 including six different carriers arranged side by side at full bandwidth frequencies of about 66 MHz to about 1218 MHz. In some embodiments, the waveform shown for the power spectrum 2200 is a 4K QAM DOCSIS 3.1 waveform. In some examples, the power spectrum 2200 may be at the output of the analog tilt filter 208 (FIG. 2). FIG. 22 also shows an adjacent channel power ratio (ACPR) correction 2202 generated due to the application of the correction provided by the DPD system 304. For purposes of this disclosure, ACPR may be described as the ratio of power in an adjacent channel to the power of a main channel, and an ACPR value is desired to be as low as possible. Therefore, the ACPR correction 2202 shown in FIG. 22 is advantageous.

Referring to FIG. 23 , a table including modulation error ratio (MER) data for a CATV amplifier is shown, which shows the effect of applying the correction provided by the DPD system 304 to the MER data. For example, MER is a metric used to quantify the performance of a digital radio (or digital TV) transmitter or receiver in a communication system using digital modulation (e.g., QAM). For the example of FIG. 23 , the CATV amplifier module under test can operate under the condition of V=34V. The MER data is compared with the cable industry specification (MER=41dB, 4KQAM, 76.8dbmV/75Ω). The CATV amplifier is tested using six carriers, wherein the first carrier is a 4K QAM signal with a carrier frequency of 204MHz, the second carrier is a 4K QAM signal with a carrier frequency of 396MHz, the third carrier is a 4K QAM signal with a carrier frequency of 588MHz, the fourth carrier is a 4K QAM signal with a carrier frequency of 786MHz, the fifth carrier is a 4K QAM signal with a carrier frequency of 930MHz, and the sixth carrier is a 4K QAM signal with a carrier frequency of 1122MHz. In the first test 2302, the sixth carrier does not meet the MER=41 dB specification when the CATV amplifier is operated at a bias current of 530 mA and without DPD correction. However, with DPD correction applied (e.g., by the DPD system 304), all carriers meet the MER specification. In the second test 2304, the CATV amplifier is operated at a bias current of 440 mA (about 3 watts less per amplifier compared to the bias current of 530 mA), and without DPD correction, all tested carriers do not meet the MER=41 dB specification. However, with DPD correction applied (e.g., by the DPD system 304), all carriers meet the MER specification.

Referring now to FIG. 24 , a method 2400 for performing digital predistortion processing in a DPD system is shown in accordance with various embodiments. The method 2400 begins at block 2402 where a DPD input signal is received at an input of a DPD system, such as the DPD system 304 of FIG. 4 . As described above, in some embodiments, the DPD input signal may include a DPD input signal x(n) ( FIG. 4 ), which may also include a composite signal c(n) generated by the DUC 302 ( FIG. 3 ). In some examples, the method 2400 proceeds to block 2404 where a nonlinear data path coupled to the input of the DPD system is provided. For example, the nonlinear data path may include the nonlinear data path 405 of FIG. 4A . As such, the nonlinear data path may include a plurality of parallel data path units. In some examples, the plurality of parallel data path units include a video bandwidth DPD data path 404, a baseband DPD data path 406, a second harmonic DPD data path 408, and a third harmonic DPD data path 410. In some embodiments, the method 2400 proceeds to block 2406, where each different parallel data path unit can be used to add different aspects of the inverse nonlinear behavior of the CATV amplifier to the input signal. In some examples, the method 2400 then proceeds to block 2408, where a first combiner combines the output of each of the plurality of parallel data path units to generate a first predistortion signal. In some cases, the first predistortion signal may include a composite signal x'(n) (FIG. 4A) that models baseband, video, and harmonic components of the CATV amplifier. In some embodiments, the method 2400 proceeds to block 2410, where a linear data path coupled to the input terminal is provided in parallel with the nonlinear data path, and wherein the linear data path generates a second predistortion signal. In some embodiments, the second predistortion signal may include a time delayed DPD input signal x(n) 419 (FIG. 4A). The method then proceeds to block 2412, where a second combiner combines the first predistortion signal and the second predistortion signal to generate a DPD output signal. In some embodiments, the DPD output signal may include a DPD output signal y(n) (FIG. 4A). In various embodiments, the method proceeds to block 2414, where the DPD output signal is provided to a CATV amplifier (e.g., CATV amplifier 212 of FIG. 2). According to an embodiment of the present disclosure, the DPD output signal is configured to compensate for multiple nonlinear components of the CATV amplifier. It will be appreciated that additional method steps may be implemented before, during, and after method 2400, and some of the method steps described above may be replaced or eliminated according to various embodiments of method 2400 without departing from the scope of the present disclosure.

It should be noted that the various configurations (e.g., the components of the cable network 200, the DFE system 300, and the DPD system 304, the number of parallel data path units in FIG. 4A, and other features and components shown in the figures) are merely exemplary and are not intended to limit the contents specifically recited in the appended claims. Those skilled in the art will understand that other configurations can be used. Moreover, although an exemplary cable network 200 is shown, the DPD system disclosed herein can be used in other communication systems, for example, where other communication systems deploy amplifiers that exhibit harmful nonlinear behavior.

The present invention may be represented by, but not limited to, one or more of the following embodiments.

Example 1: A crest factor reduction (CFR) system comprises: a digital tilt filter coupled to an input of a CFR system, wherein the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at an output of the digital tilt filter; a CFR module coupled to an output of the digital tilt filter, wherein the CFR module is configured to receive the digital tilt filter output signal and perform CFR processing on the digital tilt filter output signal to generate a CFR module output signal at an output of the CFR module; and a digital tilt equalizer coupled to an output of the CFR module, wherein the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

Example 2: The CFR system of Example 1 further includes: a digital predistortion (DPD) module coupled to an output end of a CFR module, wherein the DPD module is configured to receive a CFR module output signal and perform DPD processing on the CFR module output signal to generate a DPD module output signal at the DPD module output end; wherein a digital tilt equalizer is coupled to the DPD module output end, and wherein the digital tilt equalizer is configured to receive the DPD module output signal and generate a system output signal.

Example 3: The CFR system of Example 1, wherein the system input signal has a first peak-to-average power ratio (PAPR), and wherein the CFR module output signal has a second PAPR that is less than the first PAPR.

Example 4: The CFR system of Example 2 also includes: a first linear data path coupled to the input of the CFR system and connected in parallel with the CFR module and the DPD module to generate a first delayed signal; and a first combiner configured to combine the digital tilt equalizer output signal and the first delayed signal to generate a system output signal.

Example 5: The CFR system of Example 4 also includes: a second linear data path coupled to the input end of the CFR system and connected in parallel with the CFR module to generate a second delayed signal; a second combiner configured to combine the CFR module output signal and the second delayed signal to generate a first output signal; and a third combiner for combining the first output signal and the DPD module output signal to generate a system output signal.

Example 6: The CFR system of Example 2, wherein the DPD module further comprises: a nonlinear data path coupled to an output of the CFR module, wherein the nonlinear data path comprises a plurality of parallel data path units, each of the plurality of parallel data path units being coupled to the CFR module output and configured to add a different inverse nonlinear component corresponding to a nonlinear component of the amplifier to the CFR module output signal, and wherein the combiner is configured to combine the output of each of the plurality of parallel data path units to generate a DPD module output signal.

Example 7: The CFR system of Example 1, wherein the digital-to-analog converter (DAC) is configured to receive a system output signal and generate a DAC output signal, wherein the analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal, and wherein the digital tilt filter is configured to model the analog tilt filter.

Example 8: The CFR system of Example 7, wherein the digital shelving equalizer is configured to model the inverse of an analog shelving filter.

Example 9: The CFR system of Example 2, further comprising a single sideband Hilbert filter, wherein the single sideband Hilbert filter input is configured to receive the DPD module output signal, and wherein the single sideband Hilbert filter output is coupled to the digital tilt equalizer input.

Example 10: The CFR system of Example 1, further comprising an adaptation engine configured to receive feedback data from the amplifier output, wherein the adaptation engine is configured to update a configuration of the CFR module based on the feedback data.

Example 11: A digital front end (DFE) system configured to perform crest factor reduction (CFR) processing, the DFE system comprising: a digital up converter (DUC) configured to receive and convert a baseband data input signal to generate a composite signal; a CFR system comprising a digital tilt filter, a CFR module, and a digital tilt equalizer, wherein the digital tilt filter is configured to receive the composite signal and generate a digital tilt filter output signal, the CFR module is configured to receive the digital tilt filter output signal and perform CFR processing on the digital tilt filter output signal to generate a CFR module output signal, the digital tilt equalizer is configured to receive the CFR module output signal and generate a CFR system output signal, and the CFR system output signal is coupled to an amplifier; and an adaptation engine configured to receive feedback data from an output of the amplifier, wherein the adaptation engine is configured to update the configuration of the CFR system based on the feedback data.

Example 12: The DFE system of Example 11, wherein the CFR processing is configured to reduce a peak-to-average power ratio (PAPR) of the digital shelving filter output signal.

Example 13: The DFE system of Example 11, wherein the CFR system further comprises: a digital predistortion (DPD) module comprising a nonlinear data path coupled to an output of the CFR module, wherein the nonlinear data path comprises a plurality of parallel data path units, each parallel data path unit being coupled to the output of the CFR module and configured to model a different inverse nonlinear component corresponding to a nonlinear component of the amplifier, wherein a combiner is configured to combine an output of each of the plurality of parallel data path units to generate a DPD module output signal, and wherein a digital tilt equalizer is configured to receive the DPD module output signal and generate a CFR system output signal.

Example 14: The DFE system of Example 11, wherein the digital-to-analog converter (DAC) is configured to receive the CFR system output signal and generate a DAC output signal, wherein the analog shelving filter is configured to receive the DAC output signal and generate an analog shelving filter output signal, and wherein the digital shelving filter is configured to model the analog shelving filter.

Example 15: The DFE system of Example 14, wherein the digital shelving equalizer is configured to model the inverse of an analog shelving filter.

Example 16: A method comprising: receiving an input signal at a digital tilt filter of a crest factor reduction (CFR) system and generating a digital tilt filter output signal at an output end of the digital tilt filter; performing CFR processing on the digital tilt filter output signal at a CFR module of the CFR system to generate a CFR module output signal, wherein the CFR processing is configured to reduce a peak-to-average power ratio (PAPR) of the digital tilt filter output signal; receiving the CFR module output signal at a digital tilt equalizer of the CFR system and generating a system output signal; and providing the system output signal to an amplifier.

Example 17: The method of Example 16, further comprising updating a configuration of the CFR system in response to feedback data received from an output of the amplifier.

Example 18: The method of Example 16 also includes: performing DPD processing on the CFR module output signal at a digital predistortion (DPD) module of the CFR system to generate a DPD module output signal; and receiving the DPD module output signal at a digital tilt equalizer of the CFR system and generating a system output signal.

Example 19: The method of Example 18, wherein the DPD module further comprises: a nonlinear data path coupled to an output of the CFR module, wherein the nonlinear data path comprises a plurality of parallel data path units, each parallel data path unit being coupled to the output of the CFR module and configured to model a different inverse nonlinear component corresponding to a nonlinear component of the amplifier, and wherein the combiner is configured to combine the output of each parallel data path unit of the plurality of parallel data path units to generate a DPD module output signal.

Example 20: The method of Example 16, further comprising: reducing power consumption of the amplifier in response to providing the system output signal to the amplifier while operating the amplifier in a nonlinear region.

Example 21: A digital predistortion (DPD) system comprising: an input terminal configured to receive a DPD input signal; and a nonlinear data path coupled to the input terminal, wherein the nonlinear data path includes a plurality of parallel data path units, each of which is coupled to the input terminal, wherein each of the plurality of parallel data path units is configured to add a different inverse nonlinear component corresponding to a nonlinear component of an amplifier to the DPD input signal, and wherein a first combiner is configured to combine the output of each of the plurality of parallel data path units to generate a first predistortion signal; a linear data path coupled to the input terminal in parallel with the nonlinear data path to generate a second predistortion signal; and a second combiner configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.

Example 22: The DPD system of Example 21, wherein the plurality of parallel data path units include a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

Example 23: The DPD system of Example 22, wherein the baseband DPD data path is configured to add an inverse nonlinear baseband component to the DPD input signal.

Example 24: The DPD system of Example 22, wherein the video bandwidth DPD data path is configured to add an inverse non-linear video bandwidth component to the DPD input signal.

Example 25: The DPD system of Example 22, wherein the second harmonic DPD data path is configured to add an inverse second harmonic component to the DPD input signal.

Example 26: The DPD system of Example 22, wherein the third harmonic DPD data path is configured to add an inverse third harmonic component to the DPD input signal.

Example 27: The DPD system of Example 21 further includes a digital tilt filter configured to model an analog tilt filter, wherein the digital tilt filter input is coupled to the input, and wherein the digital tilt filter output is coupled to the nonlinear data path.

Example 28: The DPD system of Example 21 further includes a digital tilt equalizer configured to model the inverse of an analog tilt filter, wherein the digital tilt equalizer input is configured to receive a first predistortion signal, and wherein the second combiner is configured to combine the digital tilt equalizer output to the second predistortion signal to generate a DPD output signal.

Example 29: The DPD system of Example 28, further comprising a single sideband Hilbert filter, wherein the single sideband Hilbert filter input is configured to receive the first predistortion signal, and wherein the single sideband Hilbert filter output is coupled to the digital tilt equalizer input.

Example 30: The DPD system of Example 21, wherein the DPD output signal is coupled to an amplifier input to generate an amplified output signal, and wherein the DPD output signal is configured to compensate for a plurality of nonlinear components of the amplifier.

Example 31: A digital front end (DFE) system configured to perform digital predistortion (DPD) processing, the DFE system comprising: a digital up converter (DUC) configured to receive and convert a baseband data input signal to generate a composite signal; and a DPD system configured to receive the composite signal at a DPD input and perform DPD processing on the composite signal, wherein the DPD input is coupled to a plurality of parallel data path units, wherein at least one of the plurality of parallel data path units is configured to add an inverse harmonic component corresponding to a nonlinear harmonic component of an amplifier to the composite signal, wherein a combiner is configured to combine the output of each of the plurality of data path units to generate a DPD output signal, wherein the DPD output signal is coupled to the amplifier; wherein the DPD output signal is configured to compensate for the nonlinear harmonic component of the amplifier.

Example 32: The DFE system of Example 30, wherein the plurality of parallel data path units include a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

Example 33: The DFE system of Example 31, wherein the DUC is configured to perform interpolation processing on the baseband data input signal to generate an interpolated signal, and wherein the DUC is configured to perform mixing processing on the interpolated signal to generate a composite signal.

Example 34: The DFE system of Example 31, wherein the DPD system further comprises a digital shelving filter configured to model an analog shelving filter, wherein an input of the digital shelving filter is configured to receive a composite signal, and wherein an output of the digital shelving filter is coupled to a plurality of parallel data path units.

Example 35: The DFE system of Example 31, wherein the DPD system further comprises a digital tilt equalizer configured to model an inverse model of an analog tilt filter, wherein an input of the digital tilt equalizer is configured to receive a combined output of each of a plurality of data path units, and wherein another combiner is configured to combine the digital tilt equalizer outputs to a linear DPD signal to generate a DPD output signal.

Example 36: A method comprising: receiving a digital predistortion (DPD) input signal at an input of a DPD system; receiving the DPD input signal on a nonlinear data path coupled to the input end of the DPD system, wherein the nonlinear data path includes a plurality of parallel data path units, each parallel data path unit coupled to the input end; adding an inverse nonlinear component corresponding to a nonlinear component of an amplifier to the DPD input signal through each parallel data path unit of the plurality of parallel data path units; combining the output of each parallel data path unit in the plurality of parallel data path units by a first combiner to generate a first predistortion signal; receiving the DPD input signal at a linear data path coupled to the input end in parallel with the nonlinear data path to generate a second predistortion signal; combining the first predistortion signal and the second predistortion signal by a second combiner to generate a DPD output signal.

Example 37: The method of Example 36, wherein the plurality of parallel data path units include a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

Example 38: The method of Example 37 also includes: adding an inverse nonlinear baseband component to the DPD input signal through a baseband DPD data path; adding an inverse nonlinear video bandwidth component to the DPD input signal through a video bandwidth DPD data path; adding an inverse second harmonic component to the DPD input signal through a second harmonic DPD data path; and adding an inverse third harmonic component to the DPD input signal through a third harmonic DPD data path.

Example 39: The method of Example 36, further comprising: providing the DPD output signal to an amplifier input to generate an amplified output signal, wherein the DPD output signal is configured to compensate for multiple nonlinear components of the amplifier.

Example 40: The method of Example 36, further comprising: reducing power consumption of the amplifier in response to providing the DPD output signal to the amplifier while operating the amplifier in a nonlinear region.

Although specific embodiments have been shown and described, it should be understood that the claimed invention is not intended to be limited to the preferred embodiments, and it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the claimed invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive. The claimed invention is intended to cover alternatives, modifications, and equivalents.

Claims (14)

1. A crest factor reduction CFR system, wherein said CFR system comprises:

A digital tilt filter coupled to an input of the CFR system, wherein the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at a digital tilt filter output;

a CFR module coupled to the digital tilted filter output, wherein the CFR module is configured to receive the digital tilted filter output signal and CFR process the digital tilted filter output signal to generate a CFR module output signal at a CFR module output; and

A digital tilt equalizer coupled to the CFR module output, wherein the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal;

a first linear data path coupled to an input of the CFR system and in parallel with the CFR module and DPD module to generate a first delay signal;

A first combiner configured to combine a digital tilt equalizer output signal and the first delay signal to generate the system output signal;

a second linear data path coupled to an input of the CFR module and in parallel with the CFR module to generate a second time-delayed signal; and

A second combiner configured to combine the CFR module output signal and the second time-delayed signal to generate a first output signal.

2. The CFR system of claim 1 further comprising:

A digital predistortion DPD module coupled to the CFR module output, wherein the DPD module is configured to receive the CFR module output signal and perform DPD processing on the CFR module output signal to generate a DPD module output signal at a DPD module output;

wherein the digital tilt equalizer is coupled to the DPD module output and the digital tilt equalizer is configured to receive the DPD module output signal and generate the system output signal.

3. The CFR system of claim 1, wherein the system input signal has a first peak-to-average power ratio, PAPR, and the CFR module output signal has a second PAPR that is less than the first PAPR.

4. The CFR system of claim 1 further comprising:

A third combiner configured to combine the first output signal and the DPD module output signal to generate the system output signal.

5. The CFR system of claim 2 wherein the DPD module further comprises:

A nonlinear data path coupled to the CFR module output, wherein the nonlinear data path comprises a plurality of parallel data path units, each of the parallel data path units coupled to the CFR module output, each of the plurality of parallel data path units configured to add a different inverse nonlinear component corresponding to the nonlinear component of the amplifier to the CFR module output signal, and wherein a combiner is configured to combine the outputs of each of the plurality of parallel data path units to generate the DPD module output signal.

6. The CFR system of claim 1 wherein a digital-to-analog converter, DAC, is configured to receive the system output signal and generate a DAC output signal, wherein an analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal, and wherein the digital tilt filter is configured to model the analog tilt filter.

7. The CFR system of claim 6 wherein the digital tilt equalizer is configured to model an inverse of the analog tilt filter.

8. The CFR system of claim 2 further comprising:

A single sideband hilbert filter having a single sideband hilbert filter input configured to receive the DPD module output signal, the single sideband hilbert filter output coupled to the digital tilt equalizer input.

9. The CFR system of claim 1 further comprising:

an adaptation engine configured to receive feedback data from an amplifier output, wherein the adaptation engine is configured to update a configuration of the CFR module based on the feedback data.

10. A digital front end DFE system configured to perform crest factor reduction, CFR, processing, the DFE system comprising:

A digital up-converter DUC configured to receive and convert the baseband data input signal to generate a composite signal;

A CFR system including a digital tilt filter, a CFR module, and a digital tilt equalizer, wherein the digital tilt filter is configured to receive a composite signal and generate a digital tilt filter output signal, the CFR module is configured to receive the digital tilt filter output signal and perform CFR processing on the digital tilt filter output signal to generate a CFR module output signal, the digital tilt equalizer is configured to receive the CFR module output signal and generate a CFR system output signal, the CFR system output signal coupled to an amplifier; and

An adaptation engine configured to receive feedback data from an output of an amplifier, wherein the adaptation engine is configured to update a configuration of the CFR system based on the feedback data, the CFR system further comprising:

a first linear data path coupled to an input of the CFR system and in parallel with the CFR module and DPD module to generate a first delay signal;

A first combiner configured to combine a digital tilt equalizer output signal and the first delay signal,

To generate the system output signal;

a second linear data path coupled to an input of the CFR module and connected in parallel with the CFR module,

To generate a second time-delayed signal; and

A second combiner configured to combine the CFR module output signal and the second time-delayed signal to generate a first output signal.

11. The DFE system of claim 10, wherein the CFR process is configured to reduce a peak-to-average power ratio, PAPR, of the digital ramp filter output signal.

12. The DFE system of claim 10, wherein the CFR system further comprises:

A digitally predistorted DPD module comprising a nonlinear data path coupled to a CFR module output, wherein the nonlinear data path comprises a plurality of parallel data path units, each of the parallel data path units coupled to the CFR module output, each of the plurality of parallel data path units configured to model a different inverse nonlinear component corresponding to a nonlinear component of an amplifier, a combiner configured to combine the outputs of each of the plurality of parallel data path units to generate a DPD module output signal, the digital tilt equalizer configured to receive the DPD module output signal and to generate the CFR system output signal.

13. The DFE system of claim 10, wherein a digital-to-analog converter, DAC, is configured to receive the CFR system output signal and generate a DAC output signal, wherein an analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal, and wherein the digital tilt filter is configured to model the analog tilt filter.

14. The DFE system of claim 13, wherein the digital tilt equalizer is configured to model an inverse of the analog tilt filter.