CN112751632A - Device and method for realizing test aiming at 5G NR uplink time slot interference - Google Patents
Device and method for realizing test aiming at 5G NR uplink time slot interference Download PDFInfo
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Abstract
本发明涉及一种实现针对5G NR上行时隙干扰进行测试的装置，包括前置放大器、预选滤波器单元、增益控制单元、第一混频单元、第二混频单元、数模转换单元、FPGA控制单元和测量显示单元。本发明还涉及一种实现针对5G NR上行时隙干扰进行测试处理的方法。采用了该实现针对5G NR上行时隙干扰进行测试的装置及其方法，通过多级预选滤波有效抑制镜像和杂散；通过快速控制射频通道增益，实现不同大小及不同动态范围信号的快速捕捉；通过FPGA并行分析，实现对5G NR上行时隙干扰信号在时域、频域的实时分析，此方法有效提高了有效信号和干扰信号分离定位能力，为运营商在5G建设和运营维护过程中，提供有效的测试保障手段。
The present invention relates to a device for testing 5G NR uplink time slot interference. Control unit and measurement display unit. The present invention also relates to a method for implementing test processing for 5G NR uplink time slot interference. By adopting the device and method for testing 5G NR uplink time slot interference, images and spurs are effectively suppressed through multi-stage pre-selection filtering; rapid capture of signals of different sizes and different dynamic ranges is achieved by rapidly controlling the RF channel gain; Through FPGA parallel analysis, real-time analysis of 5G NR uplink time slot interference signals in the time domain and frequency domain is realized. This method effectively improves the separation and positioning capability of effective signals and interference signals, and provides operators with 5G construction, operation and maintenance. Provide effective test guarantee means.
Description
Technical Field
The invention relates to the field of mobile communication, in particular to the field of network optimization, and specifically relates to a device and a method for testing 5G NR uplink time slot interference.
Background
5G is a brand new mobile communication technology, a plurality of versions of the current 3GPP R15 protocol standard have been released, mobile operators can face a plurality of complex problems in the process of accelerating the 5G network construction speed, in the process of initial and later operation of network construction, in the process of merging 5G and 2/3/4G networks, especially the problem of 5G uplink time slot interference, which is a problem that the mobile operators must face and have to solve, and the problem affects the user access and the data throughput, so that a meter capable of searching and positioning the 5G uplink time slot interference is developed, and the meter has a very important meaning for the whole 5G.
The traditional solution is to search and locate the uplink timeslot interference by a spectrometer, and because the traditional spectrometer is limited in scanning speed and analysis bandwidth and cannot synchronize with a base station, the initial position of a radio frame cannot be determined, and the problem of uplink interference measurement cannot be solved well, therefore, it is very urgent to develop a device which can locate the initial position of the radio frame and can analyze the 5G uplink timeslot interference without synchronizing with the base station.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a device and a method for testing the 5G NR uplink time slot interference, which have the advantages of high efficiency, high accuracy and wide application range.
In order to achieve the above object, the apparatus and method for implementing a test for 5G NR uplink timeslot interference of the present invention are as follows:
the device for realizing the test aiming at the 5G NR uplink time slot interference is mainly characterized by comprising a preamplifier, a preselection filter unit, a gain control unit, a first frequency mixing unit, a second frequency mixing unit, a digital-to-analog conversion unit, an FPGA control unit and a measurement display unit, wherein the input end of the preselection filter unit is connected with the output end of a receiving antenna through the preamplifier, the output end of the preselection filter unit is connected with the input end of the gain control unit, and the output end of the gain control unit is connected with the input end of the first frequency mixing unit; the output end of the first frequency mixing unit is connected with the input end of the second frequency mixing unit, the output end of the second frequency mixing unit is connected with the input end of the digital-to-analog conversion unit, the output end of the digital-to-analog conversion unit is connected with the input end of the FPGA control unit, and the output end of the FPGA control unit is connected with the input end of the measurement display unit.
Preferably, the preselection filter unit comprises 12 sets of multistage low-pass high-pass filtering sets, and is used for ensuring the out-of-band rejection capability of the filter, and has sufficient rejection degree for images and spurs, and the frequency coverage range is 10MHz to 8000 MHz.
Preferably, the gain control unit includes two alternative switches, a first amplifier and an adjustable attenuator, and the first amplifier and the adjustable attenuator are respectively connected between the two alternative switches and are used for detecting signals of different sizes.
Preferably, the first frequency mixing unit includes a first mixer, a second amplifier and a filter, and the mixer, the second amplifier and the filter are connected in sequence to mix and output the first intermediate frequency.
Preferably, the second frequency mixing unit includes a second mixer, a third amplifier and a band-pass filter, and the second mixer, the third amplifier and the band-pass filter are connected in sequence to mix and output the second intermediate frequency.
Preferably, the digital-to-analog conversion unit includes a wideband demodulator, a fourth amplifier, a low-pass filter, and a digital-to-analog converter, the fourth amplifier, the low-pass filter, and the digital-to-analog converter are connected in sequence, an output end of the wideband demodulator respectively outputs an I signal and a Q signal to the fourth amplifier, the wideband demodulator converts an intermediate frequency signal into a zero-frequency analog IQ link signal, transmits the zero-frequency analog IQ link signal to the digital-to-analog converter, and converts the zero-frequency analog IQ link signal into a digital IQ link signal for analysis.
Preferably, the FPGA control unit is configured to perform IQ data parallel processing and perform 5G NR uplink timeslot interference signal analysis.
Preferably, the preamplifier is used for fixed gain amplification, and the amplification gain is 20 dB.
The method for realizing the test processing aiming at the 5G NR uplink time slot interference based on the device is mainly characterized by comprising the following steps:
(1) configuring a sampling rate, capturing 10 milliseconds of data of a 5G signal wireless frame, and performing time-frequency domain analysis;
(2) performing sliding correlation by adopting the extracted IQ two-path data and point data locally generated by a main synchronous signal, acquiring a maximum correlation value, and determining the initial position of a broadcast synchronous resource block;
(3) correlating the demodulation reference signal data with the demodulation reference signal data of a local broadcast channel, determining a time slot number and a symbol number, and determining a wireless frame starting position;
(4) recombining data according to the initial position of the wireless frame;
(5) accumulating the square sum of the recombined data, performing root mean square detection, and displaying data of a designated symbol, a designated time slot or a designated subframe on a measurement display interface according to the requirements of a user;
(6) and according to the user requirements, extracting the time domain data of the designated symbol, performing FFT (fast Fourier transform) to obtain the frequency domain data of the corresponding symbol, and displaying the frequency spectrum data on a measurement display unit.
Preferably, the step (3) specifically includes the following steps:
(3.1) extracting time domain data of a symbol 1 and a symbol 3 of the current broadcast synchronous resource block according to the initial position of the broadcast synchronous resource block, respectively performing inverse Fourier transform, and converting the time domain data into a frequency domain;
and (3.2) extracting demodulation reference signal data of the frequency domain broadcast channel, correlating the demodulation reference signal data with demodulation reference signal data of a local broadcast channel, determining a time slot number and a symbol number, and determining the starting position of a wireless frame.
By adopting the device and the method for testing the 5G NR uplink time slot interference, the images and the spurs are effectively inhibited through multi-stage pre-selection filtering; the gain of a radio frequency channel is rapidly controlled, so that signals with different sizes and different dynamic ranges are rapidly captured; by FPGA parallel analysis, the real-time analysis of the 5G NR uplink time slot interference signal in time domain and frequency domain is realized, the method effectively improves the separation and positioning capability of effective signal and interference signal, and provides effective test guarantee means for operators in the 5G construction and operation maintenance process.
Drawings
Fig. 1 is a schematic block diagram of an apparatus for implementing a test for 5G NR uplink timeslot interference according to the present invention.
Fig. 2 is a schematic block diagram of the apparatus pre-selection filtering for implementing the test for 5G NR uplink timeslot interference according to the present invention.
Fig. 3 is a schematic block diagram of the device gain control for implementing the test for 5G NR uplink timeslot interference according to the present invention.
Fig. 4 is a schematic block diagram of a first mixing unit of the apparatus for implementing a test for 5G NR uplink timeslot interference according to the present invention.
Fig. 5 is a schematic block diagram of a second mixing unit of the apparatus for implementing a test for 5G NR uplink timeslot interference according to the present invention.
Fig. 6 is a schematic block diagram of an analog-to-digital conversion unit of a device for implementing a test for 5G NR uplink timeslot interference according to the present invention.
Fig. 7 is a schematic block diagram of an FPGA control unit of the apparatus for implementing a test for 5G NR uplink timeslot interference according to the present invention.
Fig. 8 is a measurement result display diagram of an apparatus for implementing a test for 5G NR uplink timeslot interference according to the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.
The device for realizing the test aiming at the 5G NR uplink time slot interference comprises a preamplifier, a preselection filter unit, a gain control unit, a first frequency mixing unit, a second frequency mixing unit, a digital-to-analog conversion unit, an FPGA control unit and a measurement display unit, wherein the input end of the preselection filter unit is connected with the output end of a receiving antenna through the preamplifier, the output end of the preselection filter unit is connected with the input end of the gain control unit, and the output end of the gain control unit is connected with the input end of the first frequency mixing unit; the output end of the first frequency mixing unit is connected with the input end of the second frequency mixing unit, the output end of the second frequency mixing unit is connected with the input end of the digital-to-analog conversion unit, the output end of the digital-to-analog conversion unit is connected with the input end of the FPGA control unit, and the output end of the FPGA control unit is connected with the input end of the measurement display unit.
As a preferred embodiment of the invention, the preselection filter unit comprises 12 sets of multistage low-pass high-pass filtering sets, is used for ensuring the out-of-band rejection capability of the filter, and has enough rejection degree for images and stray waves, and the frequency coverage range is 10MHz-8000 MHz.
As a preferred embodiment of the present invention, the gain control unit includes two alternative switches, a first amplifier and an adjustable attenuator, and the first amplifier and the adjustable attenuator are respectively connected between the two alternative switches and are used for detecting signals with different sizes.
As a preferred embodiment of the present invention, the first mixing unit includes a first mixer, a second amplifier, and a filter, and the mixer, the second amplifier, and the filter are connected in sequence to mix and output the first intermediate frequency.
In a preferred embodiment of the present invention, the second mixing unit includes a second mixer, a third amplifier, and a band-pass filter, and the second mixer, the third amplifier, and the band-pass filter are connected in sequence to mix and output the second intermediate frequency.
As a preferred embodiment of the present invention, the digital-to-analog conversion unit includes a wideband demodulator, a fourth amplifier, a low-pass filter, and a digital-to-analog converter, the fourth amplifier, the low-pass filter, and the digital-to-analog converter are sequentially connected, an output end of the wideband demodulator respectively outputs an I signal and a Q signal to the fourth amplifier, and the wideband demodulator converts an intermediate frequency signal into an analog IQ link signal of zero frequency, transmits the analog IQ link signal to the digital-to-analog converter, and converts the analog IQ link signal into a digital IQ link signal for analysis.
As a preferred embodiment of the present invention, the FPGA control unit is configured to perform IQ data parallel processing and perform 5G NR uplink timeslot interference signal analysis.
In a preferred embodiment of the present invention, the preamplifier is used for fixed gain amplification, and the amplification gain is 20 dB.
The method for realizing the test processing aiming at the 5G NR uplink time slot interference based on the device comprises the following steps:
(1) configuring a sampling rate, capturing 10 milliseconds of data of a 5G signal wireless frame, and performing time-frequency domain analysis;
(2) performing sliding correlation by adopting the extracted IQ two-path data and point data locally generated by a main synchronous signal, acquiring a maximum correlation value, and determining the initial position of a broadcast synchronous resource block;
(3) correlating the demodulation reference signal data with the demodulation reference signal data of a local broadcast channel, determining a time slot number and a symbol number, and determining a wireless frame starting position;
(3.1) extracting time domain data of a symbol 1 and a symbol 3 of the current broadcast synchronous resource block according to the initial position of the broadcast synchronous resource block, respectively performing inverse Fourier transform, and converting the time domain data into a frequency domain;
(3.2) extracting demodulation reference signal data of a frequency domain broadcast channel, correlating the demodulation reference signal data with demodulation reference signal data of a local broadcast channel, determining a time slot number and a symbol number, and determining a wireless frame starting position;
(4) recombining data according to the initial position of the wireless frame;
(5) accumulating the square sum of the recombined data, performing root mean square detection, and displaying data of a designated symbol, a designated time slot or a designated subframe on a measurement display interface according to the requirements of a user;
(6) and according to the user requirements, extracting the time domain data of the designated symbol, performing FFT (fast Fourier transform) to obtain the frequency domain data of the corresponding symbol, and displaying the frequency spectrum data on a measurement display unit.
In the specific implementation manner of the present invention, the digital IQ signal sampled by an ADC (digital-to-analog converter) is obtained by controlling the channel link configuration frequency and gain such as the preselection filter, the gain, the two-stage mixing, and the like, and the digital IQ signal is subjected to time domain and frequency domain processing in the unit controlled by the FPGA, so that the time domain and frequency domain processing and display can be performed on different symbols, time slots, and subframes, thereby helping to search for the uplink time slot interference of the 5G NR. The invention effectively inhibits images and stray through multi-stage preselection filtering; the gain of a radio frequency channel is rapidly controlled, so that signals with different sizes and different dynamic ranges are rapidly captured; by FPGA parallel analysis, the real-time analysis of the 5G NR uplink time slot interference signal in time domain and frequency domain is realized, the method effectively improves the separation and positioning capability of effective signal and interference signal, and provides effective test guarantee means for operators in the 5G construction and operation maintenance process.
As shown in fig. 1, a 5G NR uplink timeslot interference testing apparatus is characterized in that: the output end of the receiving antenna is connected with the input end of the preselection filter unit through a preamplifier; the output end of the preselection filter unit is connected with the input end of the gain control unit; the output end of the gain control unit is connected with the input end of the first frequency mixing unit and outputs a first intermediate frequency of 2.547 GHz; the output end of the first frequency mixing unit is connected with the input end of the second frequency mixing unit, and a second intermediate frequency of 220MHz is output; the output end of the second frequency mixing unit is connected with the input end of the digital-to-analog conversion unit; the output end of the digital-to-analog conversion unit is connected with the input end of an FPGA (field programmable gate array) control unit; the output end of the FPGA (field programmable gate array) control unit is connected with the input end of the measurement display unit;
the pre-amplifier is a fixed gain amplifier, and the amplification gain of the pre-amplifier is 20dB, so that the aim is to achieve small signal detection capability.
As shown in fig. 2, the preselection filtering unit includes 12 sets of multi-stage low-pass high-pass filter sets, the frequency coverage is from 10MHz to 8000MHz, the multi-stage low-pass high-pass filter sets are used for ensuring the out-of-band rejection capability of the filter in order to ensure sufficient rejection degree for images and spurs. The 12 groups of filters are divided into 2890-3660 MHz, 2060-2910 MHz, 1090-2080 MHz, 10-710 MHz, 690-1100 MHz, 3640-4210 MHz, 5390-6010 MHz, 4690-5410 MHz, 4190-4710 MHz, 5990-6610 MHz, 6590-7210 MHz and 7190-8010 MHz.
As shown in fig. 3, the gain control unit includes two alternative switches, a 20dB amplifier and a 30dB adjustable attenuator, so as to detect signals with different sizes.
As shown in fig. 4, the first mixing unit includes a mixer, an amplifier and a filter, and the final mixed output has a first intermediate frequency of 2.547GHz, and a stage of amplification and filtering is added because the signal output by the mixing unit will cause signal attenuation and spurious generation.
As shown in fig. 5, the second mixing unit includes a mixer, an amplifier and a band pass filter, and the final mixed output second intermediate frequency is 220MHz, the purpose of designing the second intermediate frequency to be 220MHz is to reduce the design difficulty of the band pass filter, because the signal output by the mixing brings signal attenuation, a first-stage amplification is added to ensure signal gain.
As shown in fig. 6, the digital-to-analog conversion unit includes a wideband demodulator, an amplifier, a low-pass filter, and an ADC (digital-to-analog converter), where the wideband demodulator converts a 220MHz intermediate frequency signal into a zero frequency analog IQ link signal, and sends the zero frequency analog IQ link signal to the ADC (digital-to-analog converter), and converts the zero frequency analog IQ link signal into digital IQ for analysis, where the ADC sampling clock frequency is 122.88MHz, which meets the requirement of 5G NR signal analysis.
As shown in fig. 7, the FPGA control unit is used for IQ data parallel processing and 5G NR uplink timeslot interference signal analysis.
Fig. 8 is a diagram showing the reporting of the measurement result and the display of the measurement parameters in the upper computer.
A5G NR uplink time slot interference test method is characterized in that:
(1) configuring a sampling rate of 122.88bps, capturing 10 milliseconds data of a wireless frame of a 5G signal for time-frequency domain analysis, wherein the two paths of data are I respectively0，I1，I2…INAnd Q0，Q1，Q2…QNWherein N is 1228799.
(2) By using extracted IQ two-path data I0，I1，I2…INAnd Q0，Q1，Q2…QNPerforming sliding correlation with 4096 point data locally generated by PSS (Primary synchronization Signal), acquiring maximum correlation value, and determining starting position P of SSB (broadcast synchronization resource Block)0。
(3) Starting position P according to SSB (broadcast synchronization resource Block)0In the extracted IQ two-path data I0，I1，I2…INAnd Q0，Q1，Q2…QNExtracting time domain data of a current SSB symbol 1 and a current SSB symbol 3, respectively carrying out inverse Fourier transform, converting the time domain data into a frequency domain, extracting frequency domain DMRS-PBCH (demodulation reference signal of a broadcast channel) data, correlating the data with local DMRS-PBCH (demodulation reference signal of the broadcast channel) data, and determining a time slot number and a symbol number so as to determine a radio frame starting position P1。
(4) According to the wireless frame starting position P1The data is recombined from the beginning of the radio frame to obtain data II0，II1，II2…IINAnd QQ0，QQ1，QQ2…QQNWherein N is 1228799.
(5) Handle II0，II1，II2…IINAnd QQ0，QQ1，QQ2…QQNAnd directly carrying out square sum accumulation, carrying out root mean square detection, and displaying data of a designated symbol, a designated time slot or a designated subframe on a measurement display interface according to the requirements of a user.
(6) According to the user's requirements, in II0，II1，II2…IINAnd QQ0，QQ1，QQ2…QQNThe time domain data of the designated symbol is extracted, FFT conversion is carried out to obtain the frequency domain data of the corresponding symbol, and the frequency spectrum data is displayed on a measurement display unit. The FFT transformation formula is: the FFT transformation formula is:
wherein k is 0, 1, …, N-1.
By adopting the device and the method for testing the 5G NR uplink time slot interference, the images and the spurs are effectively inhibited through multi-stage pre-selection filtering; the gain of a radio frequency channel is rapidly controlled, so that signals with different sizes and different dynamic ranges are rapidly captured; by FPGA parallel analysis, the real-time analysis of the 5G NR uplink time slot interference signal in time domain and frequency domain is realized, the method effectively improves the separation and positioning capability of effective signal and interference signal, and provides effective test guarantee means for operators in the 5G construction and operation maintenance process.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
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