CN112799874A

CN112799874A - Memory control method, memory storage device, and memory control circuit unit

Info

Publication number: CN112799874A
Application number: CN202110201669.7A
Authority: CN
Inventors: 林玉祥; 周伯桥; 杨政哲
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2021-02-23
Filing date: 2021-02-23
Publication date: 2021-05-14
Anticipated expiration: 2041-02-23
Also published as: CN112799874B

Abstract

The present invention provides a memory control method, a memory storage device and a memory control circuit unit. The method includes: performing a single-page encoding operation on the first data stored in the first type of entity unit to generate local parity data; The second data in at least two of which perform a global encoding operation to generate global parity data; in response to the failure of the single-page decoding operation on the first data, the first type of entity unit, the second type of entity unit and the third reading the second data in the at least two of the entity-like units; and performing a global decoding operation on the second data according to the global parity data. Therefore, the ability to correct errors in the data can be improved.

Description

Memory control method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory control technology, and more particularly, to a memory control method, a memory storage device, and a memory control circuit unit.

Background

Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.

Generally, to ensure the correctness of data, the data is encoded and then stored in the rewritable nonvolatile memory module. When reading data, the data is decoded to attempt to correct errors therein. If the errors in the data are corrected, the corrected data is transmitted back to the host system. However, as the size of the rewritable nonvolatile memory module is smaller, errors in the read data are more difficult to correct.

Disclosure of Invention

Exemplary embodiments of the present invention provide a memory control method, a memory storage device and a memory control circuit unit, which can improve the correction capability for errors in data.

An exemplary embodiment of the present invention provides a memory control method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units. The plurality of entity units comprise a first type entity unit, a second type entity unit and a third type entity unit. The memory control method includes: performing, by an encoding circuit, a single-page encoding operation on first data stored in the first type of physical unit to generate local parity data; performing, by the encoding circuit, a global encoding operation on second data stored in at least two of the first type of physical unit, the second type of physical unit, and the third type of physical unit to generate global parity data, wherein the second data includes the first data; performing, by a decoding circuit, a single page decoding operation on the first data according to the local parity data; reading the second data from the at least two of the first type of physical unit, the second type of physical unit, and the third type of physical unit in response to the single page decoding operation failing; and performing, by the decoding circuit, a global decoding operation on the second data according to the global parity data to correct errors in the first data.

In an exemplary embodiment of the present invention, the decoding circuit performs the single-page decoding operation and the global decoding operation using a probability solution algorithm.

In an exemplary embodiment of the invention, the memory control method further includes: after generating the local parity data, storing the local parity data in the first type of entity unit; and in response to the single page decode operation failing, reading the local parity data from the first type of physical unit and applying the local parity data in the global decode operation.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity units. The plurality of entity units comprise a first type entity unit, a second type entity unit and a third type entity unit. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for performing a single-page encoding operation on first data stored in the first type of physical unit to generate local parity data. The memory control circuit unit is also used for performing global coding operation on second data stored in at least two of the first type of physical unit, the second type of physical unit and the third type of physical unit to generate global parity data, wherein the second data comprises the first data. The memory control circuitry unit is also to perform a single page decode operation on the first data according to the local parity data. In response to the single page decode operation failing, the memory control circuitry unit is also to read the second data from the at least two of the first type of physical units, the second type of physical units, and the third type of physical units. The memory control circuit unit is further configured to perform a global decoding operation on the second data according to the global parity data to correct errors in the first data.

In an exemplary embodiment of the present invention, the memory control circuit unit performs the single page decoding operation and the global decoding operation using a probability solution algorithm.

In an example embodiment of the present invention, after the local parity data is generated, the memory control circuit unit is further configured to store the local parity data in the first type of physical unit. In response to the single page decode operation failing, the memory control circuitry unit is also to read the local parity data from the first type of physical unit and apply the local parity data in the global decode operation.

An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units. The plurality of entity units comprise a first type entity unit, a second type entity unit and a third type entity unit. The memory control circuit unit comprises a host interface, a memory interface, an error checking circuit and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuit is coupled to the host interface, the memory interface, and the error checking circuit. The error checking circuit is configured to perform a single-page encoding operation on first data stored in the first type of physical unit to generate local parity data. The error checking circuit is further configured to perform a global encoding operation on second data stored in at least two of the first type of physical unit, the second type of physical unit, and the third type of physical unit to generate global parity data, wherein the second data includes the first data. The error checking circuit is further to perform a single page decoding operation on the first data according to the local parity data. In response to the single page decode operation failing, the memory management circuitry is to read the second data from the at least two of the first class of physical units, the second class of physical units, and the third class of physical units. The error checking circuit is further configured to perform a global decoding operation on the second data according to the global parity data to correct errors in the first data.

In an exemplary embodiment of the present invention, the error checking circuit performs the single page decoding operation and the global decoding operation using a probability solution algorithm.

In an exemplary embodiment of the invention, the first type of physical unit belongs to one of a lower physical programming unit, a middle physical programming unit and an upper physical programming unit. The second type of physical unit belongs to another one of the lower physical programming unit, the middle physical programming unit and the upper physical programming unit. The third type of physical unit belongs to another one of the lower physical programming unit, the middle physical programming unit and the upper physical programming unit.

In an exemplary embodiment of the invention, the lower physical program cell is for storing the least significant bits of the first memory cells, the middle physical program cell is for storing the middle significant bits of the first memory cells, and the upper physical program cell is for storing the most significant bits of the first memory cells.

In an exemplary embodiment of the present invention, the at least two of the first type of physical cells, the second type of physical cells and the third type of physical cells include the upper physical program cell and the middle physical program cell and do not include the lower physical program cell.

In an exemplary embodiment of the present invention, the at least two of the first type of physical cells, the second type of physical cells and the third type of physical cells include the upper physical programming unit, the middle physical programming unit and the lower physical programming unit.

In an example embodiment of the present invention, after the local parity data is generated, the memory management circuit is further configured to store the local parity data in the first type of physical unit. In response to the single page decode operation failing, the memory management circuitry is also to read the local parity data from the first type of physical unit and apply the local parity data in the global decode operation.

Based on the above, the entity units in the rewritable nonvolatile memory module may include a first type entity unit, a second type entity unit, and a third type entity unit. When encoding data, the encoding circuit may perform a single-page encoding operation on first data stored in the first type of physical unit to generate local parity data. In addition, the encoding circuit may also perform a global encoding operation on second data stored in at least two of the first type of physical unit, the second type of physical unit, and the third type of physical unit to generate global parity data, wherein the second data includes the first data. In decoding data, a decoding circuit may perform a single page decoding operation on the first data according to the local parity data. In response to a failure of the single page decoding operation, the second data may be read from the at least two of the first type of physical unit, the second type of physical unit, and the third type of physical unit. Then, the decoding circuit may perform a global decoding operation on the second data according to the global parity data to correct errors in the first data. Therefore, the error correction capability of the data stored in the rewritable nonvolatile memory module can be improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;

FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

FIG. 7 is a diagram illustrating threshold voltage distributions of memory cells in accordance with an exemplary embodiment of the present invention;

FIG. 8 is a diagram illustrating an encoding operation according to an exemplary embodiment of the present invention;

FIG. 9A is a diagram illustrating an encoding operation according to an exemplary embodiment of the present invention;

FIG. 9B is a diagram illustrating a parity check matrix according to an exemplary embodiment of the present invention;

FIG. 10 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention;

FIG. 11 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention;

FIG. 12 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all connected to a system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 over the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 by wire or wirelessly through the data transmission interface 114. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, Near Field Communication (NFC) memory storage, wireless fidelity (WiFi) memory storage, Bluetooth (Bluetooth) memory storage, or Bluetooth low energy memory storage (e.g., iBeacon) based memory storage based on various wireless Communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of the host system and the memory storage device according to an exemplary embodiment of the invention. Referring to fig. 3, in an exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, a tablet computer, or the like, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, an embedded storage device 34, or the like. The embedded memory device 34 includes various types of embedded memory devices such as an embedded multimedia Card (eMMC) 341 and/or an embedded Multi-Chip Package (eMCP) memory device 342, which directly connects the memory module to the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402. In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Memory (Flash) interface standard, the CP interface standard, the CF interface standard, the Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), a Quad Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable non-volatile memory module 406 has multiple memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same wordline or the same wordline plane may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line or the same word line plane can be at least classified into a lower physical program cell and an upper physical program cell. Generally, the writing speed of the lower physical program cell may be greater than that of the upper physical program cell, and/or the reliability of the lower physical program cell may be higher than that of the upper physical program cell.

In an exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundancy bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit region includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other exemplary embodiments, the data bit region may include 8, 16 or more or less physical fans, and the size of each physical fan may be larger or smaller. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, a physical erase unit is a physical block (block).

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, and an error checking circuit 508.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.

In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another example embodiment, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is connected to the memory management circuitry 502. The memory management circuitry 502 may communicate with the host system 11 through a host interface 504. The host interface 504 is used for receiving and recognizing commands and data transmitted from the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 502 through the host interface 504. In addition, the memory management circuitry 502 may transfer data to the host system 11 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

The memory interface 506 is connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

An error checking circuit 508 is coupled to the memory management circuit 502 and is configured to perform error checking operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking circuit 508 generates an Error Correction Code (ECC) and/or an Error Detection Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error detection code corresponding to the data is simultaneously read, and the error check circuit 508 performs an error check operation on the read data according to the error correction code and/or the error detection code.

In an exemplary embodiment, the memory control circuit unit 404 further includes a power management circuit 512 and a buffer memory 510. The power management circuit 512 is connected to the memory management circuit 502 and is used to control the power of the memory storage device 10. The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.

In an example embodiment, the rewritable non-volatile memory module 406 of fig. 4 is also referred to as a flash memory module, the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module, and/or the memory management circuit 502 of fig. 5 is also referred to as a flash memory management circuit.

FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 6, the memory management circuit 502 logically groups the physical units 610(0) -610 (B) of the rewritable nonvolatile memory module 406 into the storage area 601 and the replacement area 602. The physical units 610(0) - (610 a) in the storage area 601 are used for storing data, and the physical units 610(a +1) - (610B) in the replacement area 602 are used for replacing damaged physical units in the storage area 601. For example, if the data read from a physical unit contains too many errors to be corrected, the physical unit is considered as a damaged physical unit. It is noted that if there are no physical erase units available in the replacement area 602, the memory management circuit 502 may declare the entire memory storage device 10 to be in a write protect (write protect) state, and no more data can be written.

In the present exemplary embodiment, each physical unit refers to a physical programming unit. However, in another exemplary embodiment, a physical unit may also refer to a physical address, a physical erase unit, or be composed of a plurality of consecutive or non-consecutive physical addresses. The memory management circuitry 502 configures the logic units 612(0) - (612 (C) to map the physical units 610(0) - (610A) in the memory area 601. In the present exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic cell may also refer to a logic program cell, a logic erase cell or be composed of a plurality of continuous or discontinuous logic addresses. In addition, each of logic cells 612(0) -612 (C) may be mapped to one or more physical cells.

The memory management circuit 502 can record a mapping relationship between logical units and physical units (also referred to as a logical-to-physical address mapping relationship) in at least one logical-to-physical address mapping table. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access operations with respect to the memory storage device 10 according to the logical-to-physical address mapping table.

FIG. 7 is a diagram illustrating threshold voltage distributions of memory cells according to an exemplary embodiment of the invention. Referring to fig. 7, taking TLC NAND flash memory module as an example, one memory cell in the rewritable nonvolatile memory module 406 can store 3 bits. For example, 3 bits that a memory cell can store include Least Significant Bit (LSB), middle significant bit (CSB), and Most Significant Bit (MSB). Taking fig. 7 as an example, assuming that the threshold voltage distribution of the programmed memory cells includes states 701-708 (or states Er-G), the 3 bits (i.e., LSB, CSB, and MSB) stored in the memory cells with threshold voltages belonging to states 701-708 (or states Er-G) are "000", "001", "010", "011", "100", "101", "110", and "111", respectively.

It is noted that, in various exemplary embodiments, the bit combinations corresponding to each state may be different, depending on the practical requirements. For example, in one exemplary embodiment, the 3 bits (i.e., LSB, CSB, and MSB) stored in the memory cells with threshold voltages respectively belonging to states 701-708 (or states Er-G) can be "111", "110", "101", "100", "011", "010", "001", and "000". In addition, if a memory cell can store other numbers of bits (e.g., 1, 2, or 4 bits), the total number of states included in the threshold voltage distribution of the memory cell may also vary, depending on the implementation requirements.

In an exemplary embodiment, if a physical cell is used to store the LSB of a plurality of memory cells, the physical cell is also referred to as a bottom-entity programming cell. In an exemplary embodiment, if a physical cell is a CSB for storing a plurality of memory cells, the physical cell is also referred to as a middle entity program cell. In an exemplary embodiment, if a physical cell is used to store the MSB of a plurality of memory cells, the physical cell is also referred to as a top physical program cell.

In an example embodiment, the error checking circuit 508 may include an encoding circuit and a decoding circuit. The encoding circuit may be configured to encode data. For example, the encoding circuit may encode the data using at least one of a low density parity check code (LDPC) or turbo code (turbo code) encoding algorithm. The decoding circuit may be used to decode the data. For example, the decoding circuit may also use at least one of the decoding algorithms, such as LDPC or turbo codes, to decode the data.

It should be noted that the aforementioned coding and decoding algorithms such as LDPC or turbo code all belong to probability solution algorithms, and are not guaranteed solution algorithms. For example, common guaranteed solution algorithms may include Exclusive-OR (XOR) and Reed-Solomon (RS) code algorithms.

Generally, the probability solution algorithm can determine that one of the error bits is actually "0" or "1" by using the concept of probability among a large number of error bits (e.g., more than 10 error bits). For example, if the value of an error bit has a higher probability of being "1", the error checking circuit 508 can correct the value of the error bit to be "1". On the other hand, if the value of an error bit has a higher probability of being "0", the error checking circuit 508 can correct the value of the error bit to be "0". However, the guaranteed solution algorithm can explicitly determine (i.e. guarantee) that one of the error bits is "0" or "1" in a smaller number of error bits (e.g. 1 to 2 error bits).

In an example embodiment, the error checking circuit 508 may perform an encoding operation (also referred to as a single-page encoding operation) on data (also referred to as first data) stored in the first type of physical unit to generate parity data (also referred to as local parity data). For example, the error checking circuit 508 may perform this single page encoding operation using the probability solution algorithm (e.g., the LDPC algorithm) described above. The generated local parity data can be used to protect the first data and can be stored in a physical unit of the rewritable non-volatile memory module 406. For example, the local parity data may be stored in the same entity unit or another entity unit with the corresponding first data, and the invention is not limited thereto.

In an example embodiment, the error checking circuit 508 may perform another encoding operation (also referred to as a global encoding operation) on data (also referred to as second data) stored in at least two of the first type of physical unit, the second type of physical unit, and the third type of physical unit to generate parity data (also referred to as global parity data). The second data includes the first data. For example, the error checking circuit 508 may perform this global encoding operation using the probability solution algorithm (e.g., LDPC algorithm) described above. The generated global parity data can be used to protect the second data and can be stored in a physical unit of the rewritable nonvolatile memory module 406.

In an exemplary embodiment, the first type of physical unit may belong to one of the lower physical program unit, the middle physical program unit and the upper physical program unit. The second type of physical unit may belong to another one of the lower physical program unit, the middle physical program unit and the upper physical program unit. The third type of physical unit may belong to another one of the lower physical program unit, the middle physical program unit and the upper physical program unit. For example, assuming that the first type of entity unit is the lower entity programming unit, the second type of entity unit and the third type of entity unit can be the middle entity programming unit and the upper entity programming unit, respectively. Alternatively, assuming that the first type of entity unit is a middle entity programming unit, the second type of entity unit and the third type of entity unit can be a lower entity programming unit and an upper entity programming unit, respectively. Alternatively, assuming that the first type entity unit is an upper entity programming unit, the second type entity unit and the third type entity unit can be a middle entity programming unit and a lower entity programming unit, respectively.

In an example embodiment, when the first data is read from the first type of physical unit, the error checking circuit 508 may perform a single decoding operation (also referred to as a single page decoding operation) on the first data according to the local parity data. This single page decoding operation may attempt to correct errors that may be present in the first data. If the single page decoding operation is successful (i.e., the error checking circuit 508 successfully corrects all errors in the first data), the memory management circuit 502 may output the successfully decoded data. For example, the memory management circuit 502 may transmit the successfully decoded first data to the host system 11 in response to a read request from the host system 11. However, if the error checking circuit 508 is unable to successfully correct all errors in the first data, the memory management circuit 502 may determine that the single page decoding operation failed.

In an example embodiment, in response to the single page decode operation failing, the memory management circuitry 502 may read the second data from at least two of the first type of physical unit, the second type of physical unit, and the third type of physical unit. The error checking circuit 508 may perform a decoding operation (also referred to as a global decoding operation) on the second data according to the global parity data to attempt to correct errors in the first data again.

FIG. 8 is a diagram illustrating an encoding operation according to an exemplary embodiment of the present invention. Referring to FIG. 8, it is assumed that the physical units 801 to 803 are used to store data D (1) to D (3), respectively. Data D (1) to D (3) belong to LSB, CSB, and MSB, respectively, of a plurality of memory cells (also referred to as first memory cells). In storing data D (1) -D (3), error checking circuit 508 may perform a single-page encoding operation on data D (1) -D (3), respectively, to generate parity data P (1) -P (3). The parity data P (1) -P (3) are local parity data and are used to protect the data D (1) -D (3), respectively. In addition, parity data P (1) -P (3) can be stored in physical units 801-803, respectively. For example, parity data P (1) -P (3) can be stored in redundant bit regions in physical units 801-803, respectively.

After generating parity data P (1) -P (3), error checking circuit 508 may further perform a global encoding operation on data 810 to generate parity data P (G0). Data 810 may include data D (1) -D (3) and parity data P (1) -P (3). Parity data P (G0) is global parity data and may be used to protect data 810 as well. The parity data P (G0) may be stored in some physical unit.

Thereafter, when reading some data (e.g., the data D (1)) of the data D (1) to D (3), the parity data P (1) can be read simultaneously. The error checking circuit 508 may perform a single page decoding operation on the data D (1) according to the parity data P (1) to attempt to correct errors in the data D (1). If the data D (1) is successfully decoded, the successfully decoded data D (1) may be output. However, if the data D (1) fails to be decoded, the data D (2) and D (3) and the parity data P (2) and P (3) can be read sequentially to obtain the data 810 including the data D (1). Error checking circuitry 508 may decode data 810 based on parity data P (G0) to attempt to correct errors in data D (1) with more information. Similarly, the parity data P (G0) can also be used to correct errors in the data D (2) and/or D (3) when the single page decoding operation of the data D (2) and/or D (3) fails.

It is noted that, in the exemplary embodiment of fig. 8, the data 810 (e.g., data D (1) -D (3)) participating in the global coding are all stored in the same memory cell (i.e., the first memory cell). For example,

physical cells

801, 802, and 803 are all located on the same word line or word line plane. However, in another exemplary embodiment, the data participating in the global coding may also be stored in different memory units.

FIG. 9A is a diagram illustrating an encoding operation according to an exemplary embodiment of the present invention. Referring to FIG. 9A, it is assumed that the physical units 801-803 are used to store data D (1) -D (3), respectively. Data D (1) to D (3) belong to the LSB, CSB, and MSB of the plurality of memory cells (i.e., the first memory cell), respectively. In storing data D (1) -D (3), error checking circuit 508 may perform a single-page encoding operation on data D (1) -D (3), respectively, to generate parity data P (1) -P (3). In addition, the entity units 901 to 903 are used to store data D (i) to D (i +2), respectively. Data D (i) to D (i +2) belong to LSB, CSB, and MSB of the plurality of memory cells (also referred to as second memory cells), respectively. It is noted that the second memory cell does not belong to the first memory cell. For example, physical cells 801-803 may be located on one word line or word line plane, while physical cells 901-903 may be located on another word line or word line plane. When storing data D (i) D (i +2), error checking circuit 508 may perform a single-page encoding operation on data D (i) D (i +2) to generate parity data P (i) P (i +2), respectively.

After parity data P (1) -P (3) and P (i) -P (i +2) are generated, error checking circuit 508 may further perform a global encoding operation on data 910 to generate parity data P (G1). Data 910 may include data D (1) to D (3), D (i) to D (i +2), parity data P (1) to P (3), and P (i) to P (i + 2). The parity data P (G1) may be stored in some physical unit.

Thereafter, when reading a certain data (e.g., data D (1)) among data D (1) to D (3) and D (i) to D (i +2), parity data P (1) can be read simultaneously. The error checking circuit 508 may perform a single page decoding operation on the data D (1) according to the parity data P (1) to attempt to correct errors in the data D (1). If the data D (1) is successfully decoded, the successfully decoded data D (1) may be output. However, if the data D (1) fails to be decoded, the data D (2), D (3), D (i) -D (i +2) and the parity data P (2), P (3), P (i) -P (i +2) can be read successively to obtain the data 910 containing the data D (1). Error checking circuitry 508 may decode data 910 based on parity data P (G1) to attempt to correct errors in data D (1) with more information. Similarly, parity data P (G1) can also be used to correct errors in data D (2), D (3), and D (i) -D (i +2) when a single page decode operation fails for any of data D (2), D (3), and D (i) -D (i + 2).

It is noted that, in an exemplary embodiment, parity data P (1) may participate in a single page decode operation for data D (1) and a global decode operation for data 810 (or 910). For example. In performing the single page decoding operation for the data D (1), the parity data P (1) may be read out from the entity unit 801 and applied to the single page decoding operation for the data D (1). After performing the single page decoding operation for the data D (1), in response to a failure of the single page decoding operation for the data D (1), the parity data P (1) may be read out again from the physical unit 801 and applied to the global decoding operation for 810 (or 910).

It should be noted that, in an exemplary embodiment, the data 810 (or 910) for generating the global parity data P (G0) (or P (G1)) may not include the local parity data P (1) -P (3) (or P (1) -P (3) and P (i) -P (i + 2)). Alternatively, in an exemplary embodiment, the global parity data may be generated only according to the data stored in the specific types of physical units (e.g., the upper physical program unit and the middle physical program unit), and the data stored in some types of physical units (e.g., the lower physical program unit) may be skipped.

In an exemplary embodiment, in the global encoding operation, the error checking circuit 508 may only perform global encoding on the data in the upper and middle physical program blocks (e.g., D (2) and D (3) in fig. 8 or D (2), D (3), D (i +1) and D (i +2) in fig. 9A) (i.e., not perform global encoding on the data in the lower physical program block to generate global parity data (e.g., P (G0) or P (G1)). Generally, the probability that the data stored in the upper and middle physical program cells includes an error bit is higher than the probability that the data stored in the lower physical program cell includes an error bit. Therefore, in an exemplary embodiment, the global encoding is performed only for the data in the upper physical programming unit and the middle physical programming unit, so that the protection capability (or error correction capability) for the data in the upper physical programming unit and the middle physical programming unit can be effectively improved without greatly increasing the encoding/decoding burden.

In an exemplary embodiment, the error checking circuit 508 may perform global encoding on data in the upper, middle and lower physical program blocks (e.g., D (1) -D (3) in FIG. 8 or D (1) -D (3) and D (i) -D (i +2)) in FIG. 9A to generate global parity data (e.g., P (G0) or P (G1)) in a global encoding operation. Thus, although the encoding/decoding burden of the system may be increased, the protection capability (or error correction capability) for all data in the memory unit can be significantly improved.

In an exemplary embodiment, the error checking circuit 508 may use the same parity check matrix H to perform both single-page and global encoding/decoding operations. For example, when performing a single page encode/decode operation, the error checking circuit 508 may encode the single page data using a portion of the submatrices H1(1) -H1 (n) in this parity check matrix H to generate local parity data or perform decoding on the read single page data. Thereafter, when performing global coding/decoding operations, the error checking circuit 508 may encode global data using another part of the submatrix H2 in the parity check matrix H to generate global parity data or perform decoding on the read global data. It should be noted that the global data refers to data containing multiple single pages of data, such as the data 810 in fig. 8 or the data 910 in fig. 9A.

FIG. 9B is a diagram illustrating a parity check matrix according to an exemplary embodiment of the invention. Referring to FIG. 9B, the parity check matrix H may include sub-matrices H1(1) -H1 (n) and H2. In the single-page encoding operation, the submatrices H1(1) -H1 (n) in the parity check matrix H may respectively participate in the encoding of n single-page data to generate n local parity data. In the global encoding operation, the submatrix H2 in the parity check matrix H may participate in the common encoding (i.e., global encoding) of the n single pages of data to generate global parity data. For example, in FIG. 9A, in the single-page encoding operation, a plurality of data bits in a single page data D (i) of the n single pages of data may be multiplied by a sub-matrix H1(i) of the sub-matrices H1(1) -H1 (n) to generate parity data P (i) corresponding to the single page data D (i). In the global encoding operation, the data 910 including the n single pages of data may be multiplied by the submatrix H2 to generate parity data P (G1).

In the single page decoding operation, the submatrices H1(1) -H1 (n) in the parity check matrix H may participate in the decoding of n single page data, respectively. In the global decoding operation, the submatrix H2 of the parity check matrix H may participate in the common decoding (i.e., global decoding) of the n single-page data. Taking fig. 9A as an example, in the single page decoding operation, the sub-matrix H1(i) of the sub-matrices H1(1) -H1 (n) may be multiplied by a plurality of data bits in the single page data d (i) of the n single pages of data. The operation result can be applied to a single page decoding operation. In the global decoding operation, the submatrix H2 may be multiplied by the data 910 including the n single pages of data. The operation result can be applied to the global decoding operation.

In an exemplary embodiment, the encoding/decoding circuit in the error checking circuit 508 may be configured according to the parity check matrix H. Accordingly, the error checking circuit 508 may perform one of the single-page encoding operation, the global encoding operation, the single-page decoding operation, and the global decoding operation of data at different points in time according to the same parity check matrix H and/or using the same encoding/decoding circuit, thereby reducing a circuit configuration space and/or a circuit complexity of the error checking circuit 508.

FIG. 10 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention. Referring to fig. 10, in step S1001, a single-page encoding operation is performed on first data stored in a first type of physical unit by an encoding circuit to generate local parity data. In step S1002, a global encoding operation is performed by the encoding circuit on second data stored in at least two of the first type of physical unit, the second type of physical unit, and the third type of physical unit to generate global parity data, wherein the second data includes the first data. In step S1003, a single page decoding operation is performed on the first data according to the local parity data by a decoding circuit. In step S1004, in response to the single page decoding operation failing, the second data is read from at least two of the first type entity unit, the second type entity unit, and the third type entity unit. In step S1005, a global decoding operation is performed on the second data according to the global parity data by the decoding circuit to correct errors in the first data.

FIG. 11 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention. Referring to fig. 11, in step S1101, data stored in a certain entity unit of the preset entity units is obtained. For example, this data may come from the host system and be stored to the physical unit. In step S1102, a single-page encoding operation is performed on the data by an encoding circuit to generate local parity data. In step S1103, it is determined whether single-page encoding of all data in the plurality of physical units has been completed. If not, steps S1101 and S1102 may be repeatedly performed. If yes, the method indicates that all data in the preset multiple physical units are subjected to single-page coding. Therefore, in step S1104, the data stored in the other physical units to participate in the global coding (i.e., all the data in the predetermined plurality of physical units) can be obtained. In step S1105, a global encoding operation is performed on all data by the encoding circuit to generate global parity data.

FIG. 12 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention. Referring to fig. 12, in step S1201, data is read from a certain entity unit. In step S1202, a single page decoding operation is performed on the data. In step S1203, it is determined whether or not the decoding is successful. If yes, in step S1204, data with a successful decoding may be output. If not, the single-page decoding operation on the data fails. Accordingly, in step S1205, data may be read from other physical units. For example, such data has been encoded together in the past to produce shared global parity data. In step S1206, a global decoding operation may be performed according to the global parity to attempt to correct errors in the data.

In one embodiment, the single page decoding operation for the same data in step S1202 may be repeated several times to continuously attempt to correct errors in the data. In one embodiment, the steps S1205 and S1206 are only performed when the number of single page decoding operations performed on the same data exceeds a predetermined number, so as to further correct errors in the data by using the global decoding operation.

However, the steps in fig. 10 to 12 have been described in detail above, and are not repeated herein. It is to be noted that, the steps in fig. 10 to fig. 12 can be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the methods of fig. 10 to 12 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

In summary, when decoding data, a single page decoding may be performed on the data first. If the data cannot be successfully decoded, global decoding may be further performed on the data to attempt to correct errors in the data using more information. Therefore, the decoding success rate of the data with higher error rate can be effectively improved. In addition, by performing single-page encoding/decoding and global encoding/decoding operations using the same parity check matrix, the circuit configuration space and/or circuit complexity of the encoding/decoding circuit can be effectively reduced.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of entity units, the entity units comprise a first entity unit, a second entity unit and a third entity unit, and the memory control method comprises the following steps:

performing, by an encoding circuit, a single-page encoding operation on first data stored in the first type of physical unit to generate local parity data;

performing, by the encoding circuit, a global encoding operation on second data stored in at least two of the first type of physical unit, the second type of physical unit, and the third type of physical unit to generate global parity data, wherein the second data includes the first data;

performing, by a decoding circuit, a single page decoding operation on the first data according to the local parity data;

reading the second data from the at least two of the first type of physical unit, the second type of physical unit, and the third type of physical unit in response to the single page decoding operation failing; and

performing, by the decoding circuit, a global decoding operation on the second data according to the global parity data to correct errors in the first data.

2. The memory control method of claim 1, wherein the decoding circuit performs the single page decoding operation and the global decoding operation using a probability solution algorithm.

3. The memory control method of claim 1, wherein the first type of physical cells belong to one of a lower physical program cell, a middle physical program cell, and an upper physical program cell,

the second type of physical unit belongs to another one of the lower physical programming unit, the middle physical programming unit and the upper physical programming unit, and

the third type of physical unit belongs to another one of the lower physical programming unit, the middle physical programming unit and the upper physical programming unit.

4. The memory control method of claim 3, wherein the lower physical program cell is for storing the least significant bit of a plurality of first memory cells, the middle physical program cell is for storing the middle significant bit of the plurality of first memory cells, and the upper physical program cell is for storing the most significant bit of the plurality of first memory cells.

5. The memory control method of claim 3, wherein the at least two of the first type of physical cells, the second type of physical cells, and the third type of physical cells include the upper physical program cell and the middle physical program cell and do not include the lower physical program cell.

6. The memory control method of claim 3, wherein the at least two of the first type of physical cells, the second type of physical cells, and the third type of physical cells include the upper physical program cell, the middle physical program cell, and the lower physical program cell.

7. The memory control method of claim 1, further comprising:

after generating the local parity data, storing the local parity data in the first type of entity unit; and

in response to the single page decode operation failing, reading the local parity data from the first type of physical unit and applying the local parity data in the global decode operation.

8. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

the system comprises a rewritable nonvolatile memory module, a first memory module, a second memory module and a third memory module, wherein the rewritable nonvolatile memory module comprises a plurality of entity units, and the entity units comprise a first entity unit, a second entity unit and a third entity unit; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuitry unit is to perform a single page encoding operation on first data stored in the first type of physical unit to generate local parity data,

the memory control circuit unit is further configured to perform a global encoding operation on second data stored in at least two of the first type of physical unit, the second type of physical unit, and the third type of physical unit to generate global parity data, wherein the second data includes the first data,

the memory control circuitry unit is also to perform a single page decode operation on the first data according to the local parity data,

in response to the single page decode operation failing, the memory control circuitry unit is further to read the second data from the at least two of the first type of physical units, the second type of physical units, and the third type of physical units, and

the memory control circuit unit is further configured to perform a global decoding operation on the second data according to the global parity data to correct errors in the first data.

9. The memory storage device of claim 8, wherein the memory control circuitry unit performs the single page decoding operation and the global decoding operation using a probability solution algorithm.

10. The memory storage device of claim 8, wherein the first type of physical cells belong to one of a lower physical program cell, a middle physical program cell, and an upper physical program cell,

11. The memory storage device of claim 10, wherein the lower physical program cell is for storing the least significant bit of a first plurality of memory cells, the middle physical program cell is for storing the middle significant bit of the first plurality of memory cells, and the upper physical program cell is for storing the most significant bit of the first plurality of memory cells.

12. The memory storage device of claim 10, wherein the at least two of the first type of physical cells, the second type of physical cells, and the third type of physical cells include the upper physical program cell and the middle physical program cell and do not include the lower physical program cell.

13. The memory storage device of claim 10, wherein the at least two of the first type of physical cells, the second type of physical cells, and the third type of physical cells include the upper physical program cell, the middle physical program cell, and the lower physical program cell.

14. The memory storage device of claim 8, wherein after generating the local parity data, the memory control circuitry unit is further to store the local parity data in the first type of physical unit, and

in response to the single page decode operation failing, the memory control circuitry unit is also to read the local parity data from the first type of physical unit and apply the local parity data in the global decode operation.

15. A memory control circuit unit, configured to control a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of entity units, the entity units include a first entity unit, a second entity unit, and a third entity unit, and the memory control circuit unit includes:

a host interface for connecting to a host system;

a memory interface for connecting to the rewritable nonvolatile memory module;

an error checking circuit; and

a memory management circuit coupled to the host interface, the memory interface, and the error checking circuit,

wherein the error checking circuit is to perform a single-page encoding operation on first data stored in the first type of physical unit to generate local parity data,

the error checking circuit is further configured to perform a global encoding operation on second data stored in at least two of the first type of physical unit, the second type of physical unit, and the third type of physical unit to generate global parity data, wherein the second data includes the first data,

the error checking circuit is also to perform a single page decoding operation on the first data according to the local parity data,

in response to the single page decode operation failing, the memory management circuitry is to read the second data from the at least two of the first class of physical units, the second class of physical units, and the third class of physical units, and

the error checking circuit is further configured to perform a global decoding operation on the second data according to the global parity data to correct errors in the first data.

16. The memory control circuit unit of claim 15, wherein the error checking circuit performs the single page decoding operation and the global decoding operation using a probability solution algorithm.

17. The memory control circuit unit of claim 15, wherein the first type of physical cells belongs to one of a lower physical programming cell, a middle physical programming cell, and an upper physical programming cell,

18. The memory control circuit unit of claim 17, wherein the lower physical programming unit is for storing the least significant bit of a first plurality of memory cells, the middle physical programming unit is for storing the median significant bit of the first plurality of memory cells, and the upper physical programming unit is for storing the most significant bit of the first plurality of memory cells.

19. The memory control circuitry unit of claim 17, wherein the at least two of the first type of physical cells, the second type of physical cells, and the third type of physical cells include the upper physical programming unit and the middle physical programming unit and do not include the lower physical programming unit.

20. The memory control circuitry unit of claim 17, wherein the at least two of the first type of physical cells, the second type of physical cells, and the third type of physical cells include the upper physical programming unit, the middle physical programming unit, and the lower physical programming unit.

21. The memory control circuitry unit of claim 15, wherein after generating the local parity data, the memory management circuitry is further to store the local parity data in the first type of physical unit, and

in response to the single page decode operation failing, the memory management circuitry is also to read the local parity data from the first type of physical unit and apply the local parity data in the global decode operation.