CN112834914A - A kind of expansion method and device of automatic test equipment test excitation output channel - Google Patents
A kind of expansion method and device of automatic test equipment test excitation output channel Download PDFInfo
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- CN112834914A CN112834914A CN202110030004.4A CN202110030004A CN112834914A CN 112834914 A CN112834914 A CN 112834914A CN 202110030004 A CN202110030004 A CN 202110030004A CN 112834914 A CN112834914 A CN 112834914A
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
本发明公开了一种自动测试设备测试激励输出通道的扩展方法及装置，方法通过高速时序控制器生成N通道测试激励向量，协同控制高速采样输出保持继电器电路组将测试激励单输出通道的测试激励信号扩展为N个通道的测试激励信号，其中N为大于等于2的整数，装置包括：高速时序控制器、测试激励单输出通道、高速采样输出保持继电器电路组，其中高速采样输出保持继电器电路组包括N组高速采样输出保持电路和继电器电路的组合；本发明可以节省测试激励输出通道资源，降低自动测试设备的结构复杂度和成本，并能增加自动测试设备测试激励输出通道的数目。
The invention discloses an expansion method and device for testing excitation output channels of automatic test equipment. The method generates N-channel test excitation vectors through a high-speed sequence controller, and cooperatively controls a high-speed sampling output holding relay circuit group to test excitation single-output channel test excitations. The signal is expanded to test excitation signals of N channels, where N is an integer greater than or equal to 2. The device includes: a high-speed sequence controller, a single output channel for test excitation, and a high-speed sampling and output holding relay circuit group, wherein the high-speed sampling output holding relay circuit group It includes the combination of N groups of high-speed sampling output holding circuits and relay circuits; the invention can save test excitation output channel resources, reduce the structural complexity and cost of automatic test equipment, and increase the number of test excitation output channels of automatic test equipment.
Description
Technical Field
The invention relates to the technical field of automatic test equipment instruments, in particular to an expansion method and device for testing an excitation output channel of automatic test equipment.
Background
The number of channels capable of generating test stimuli in the automatic test equipment is related to the grade of the test equipment, the test equipment at the low end usually only has one test stimulus channel, the test equipment at the middle end usually has 8 or 16 test stimulus channels, only the test equipment at the high end adopts a perpin structure, independent test stimulus channels are equipped, and the number of the test stimulus channels can also reach more than 256.
When the automatic test equipment is used, if the low-end or middle-end test equipment is used, because the number of test excitation channels is limited, the test excitation channels can only be used successively in a sharing mode, and when the test excitation channels are used at the same time, the test requirements cannot be met, so that the test can be completed only by adopting the high-end test equipment.
Disclosure of Invention
In order to solve the defects of the prior art and realize the purpose of expanding a single test excitation output channel into more than 2 channels, the invention adopts the following technical scheme:
an expansion method for testing an excitation output channel by automatic test equipment comprises the following steps:
s1: the high-speed time sequence controller generates an N-channel test excitation vector and a test excitation vector time sequence table;
s2: the high-speed time sequence controller controls the test excitation single output channel to output a test excitation time sequence signal of a channel to be kept according to the test excitation vector time sequence table;
s3: opening a channel relay to be kept, and transmitting a test excitation timing sequence signal to a DUT (device under test) end of a chip to be tested;
s4: closing a relay circuit of a channel to be kept, opening a high-speed output holding circuit, and keeping a test excitation timing sequence signal of the channel to be kept;
s5: adding the channel numbers of the channels to be kept into a keeping time queue, and refreshing the test excitation timing sequence signals of the channels to be kept according to the sequence of the channels to be kept in the keeping time queue;
s6: and repeating the steps S2-S5 until the output of the N-channel test excitation vector is finished.
Further, the step S5 specifically includes the following steps:
s51: adding the channel numbers x of the channels to be kept into the keeping time queue in sequence according to the sequence defined in the test excitation vector time sequence table;
s52: when the test excitation signal output by the test excitation single output channel is idle, the high-speed time sequence controller accesses the test excitation single output channel into a channel corresponding to the channel number stored in the head of the retention time queue, and refreshes the retention time again;
s53: and deleting the channel number x of the queue in the hold time queue from the head of the hold time queue and adding the channel number x into the tail of the queue again.
Further, the operating frequency of the high-speed timing controller in step S1 is greater than or equal to 1 GHz.
Further, N in step S1 is an integer of 2 or more.
Further, the pulse amplitude range of the test excitation timing signal in the step S2 is 0-10V, and the pulse width is greater than or equal to 10 ns.
Further, the high-speed output holding circuit in step S4 is a high-speed sampling output holding circuit, the sampling time is equal to or less than 1ns, and the holding time is equal to or more than 100 us.
An expansion device for testing an excitation output channel of automatic test equipment comprises a high-speed time schedule controller, a testing excitation single output channel and a high-speed output holding relay circuit group, the high-speed output holding relay circuit group comprises N groups of high-speed output holding circuits and relay circuit combinations, the high-speed time sequence controller controls the test excitation single output channel to output the test excitation time sequence signal of the channel to be held according to the test excitation vector time sequence table generated by the high-speed time sequence controller, the time sequence signal is respectively connected with the N groups of high-speed output holding circuits and the relay circuit combinations, when a group of output timing signals is needed, firstly, the relays of the group are opened, the timing signals are transmitted to the DUT end of the chip to be tested, then the relay is closed and the high-speed output holding circuit is started, the output signals of the group are held, and the output signals of the group can be refreshed again in the next test excitation single output channel output gap.
Furthermore, the high-speed output holding relay circuit group is a high-speed sampling output holding relay circuit group and comprises N groups of high-speed sampling output holding circuits and relay circuits.
Furthermore, a holding time queue is set, the channel numbers of the channels to be held are added into the holding time queue, and the test excitation time sequence signals of the channels to be held are refreshed according to the sequence of the channels to be held in the holding time queue.
The invention has the advantages and beneficial effects that:
the invention expands the single test excitation output channel into a plurality of test excitation output channels through the sampling output holding circuit, saves the test excitation output channel resources of the automatic test equipment, reduces the structural complexity and the cost of the automatic test equipment, and can increase the number of the test excitation output channels of the automatic test equipment.
Drawings
FIG. 1 is a flow chart of the method of the present invention.
Fig. 2 is a schematic diagram of the internal structure of the high-speed sample output hold relay circuit group according to the present invention.
FIG. 3 is a schematic structural diagram of the test stimulus single output channel expansion in the present invention.
Fig. 4 is a schematic structural diagram of the test excitation single output channel group expansion in the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
As shown in fig. 1, an expansion method for testing an excitation output channel by automatic test equipment includes the following steps:
s1: the high-speed time sequence controller generates N-channel test excitation vectors and a test excitation vector time sequence table.
Preferably, the operating frequency of the high-speed timing controller is greater than or equal to 1GHz, and the N-channel test excitation vector timing table is generated by the high-speed timing controller according to the N-channel test excitation vector, where N is an integer greater than or equal to 2.
S2: and the high-speed time sequence controller controls the test excitation single output channel to output the test excitation time sequence signal of the channel to be kept according to the test excitation vector time sequence table.
Preferably, the pulse amplitude range of the test excitation timing signal is 0-10V, and the pulse width is greater than or equal to 10 ns.
S3: and keeping the channel relay open, and transmitting the test excitation timing sequence signal to the DUT end of the chip to be tested.
S4: and closing the relay circuit of the channel to be kept, opening the high-speed sampling output holding circuit, and keeping the test excitation timing sequence signal of the channel to be kept.
Preferably, the sampling time of the high-speed sampling output holding circuit is less than or equal to 1ns, and the holding time is greater than or equal to 100 us.
S5: adding the channel numbers of the channels to be kept into a keeping time queue, and refreshing the test excitation timing signals of the channels to be kept according to the sequence of the channels to be kept in the keeping time queue.
Specifically, the method for refreshing the holding time by the holding channel corresponding to the channel number in the holding time queue according to the principle of queue "first-in first-out" includes the following steps:
s51: and sequentially adding the channel numbers x of the channels to be kept into the keeping time queue according to the sequence defined in the test excitation vector time sequence table. The sequence defined by the test excitation vector time sequence table is also an execution sequence for keeping the channel output, and the execution sequence is added into the holding time queue immediately after the execution.
S52: and when the test excitation signal output by the test excitation single output channel is idle, the high-speed time sequence controller accesses the test excitation single output channel into a channel corresponding to the channel number stored in the head of the retention time queue, and refreshes the retention time again. The high-speed time sequence controller refers to the time interval of output of a certain two holding output channels when the test excitation single output channel outputs the test excitation signal.
S53: and deleting the channel number x of the queue in the hold time queue from the head of the hold time queue and adding the channel number x into the tail of the queue again.
S6: and repeating the steps S2-S5 until the output of the N-channel test excitation vector is finished.
Description of the working principle: as shown in fig. 2, the principle of the method for expanding the test stimulus output channel of the automatic test equipment provided by the present invention is as follows:
and the signal output by the test excitation single output channel is input into the high-speed sampling output holding relay circuit group and is expanded into an N-channel test excitation output channel to be sent to the DUT end of the chip to be tested through the high-speed sampling output holding relay circuit group. The high-speed sampling output holding relay circuit group consists of N groups of high-speed sampling output holding circuits and relay circuits, each group comprises 1 high-speed sampling output holding circuit and 1 relay circuit, and N is an integer greater than or equal to 2. And when a certain group of output signals are needed, firstly, the relay of the group is opened, the signals are transmitted to the DUT end of the chip to be tested, then, the relay is closed, the high-speed sampling output holding circuit is started to work, the output signals of the group are maintained, and the output signals of the group can be refreshed again in the output gap of the next test excitation single output channel. The high-speed sampling output holding relay circuit group can be realized in an analog voltage latching mode.
In the first embodiment, as shown in fig. 3, a system samples a group of test excitation single output channels and a group of high-speed sample output hold relay circuit groups expands test excitation signals of the group of test excitation single output channels.
In the second embodiment, as shown in fig. 4, the system samples M groups of test excitation single output channels and M groups of high-speed sample output hold relay circuit groups to expand M groups of test excitation signals of the M groups of test excitation single output channels, where M is an integer greater than or equal to 2.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. An expansion method for testing an excitation output channel by automatic test equipment is characterized by comprising the following steps:
s1: the high-speed time sequence controller generates an N-channel test excitation vector and a test excitation vector time sequence table;
s2: the high-speed time sequence controller controls the test excitation single output channel to output a test excitation time sequence signal of a channel to be kept according to the test excitation vector time sequence table;
s3: opening a channel relay to be kept, and transmitting a test excitation timing sequence signal to a DUT (device under test) end of a chip to be tested;
s4: closing a relay circuit of a channel to be kept, opening a high-speed output holding circuit, and keeping a test excitation timing sequence signal of the channel to be kept;
s5: adding the channel numbers of the channels to be kept into a keeping time queue, and refreshing the test excitation timing sequence signals of the channels to be kept according to the sequence of the channels to be kept in the keeping time queue;
s6: and repeating the steps S2-S5 until the output of the N-channel test excitation vector is finished.
2. The method according to claim 1, wherein the step S5 specifically includes the following steps:
s51: adding the channel numbers x of the channels to be kept into the keeping time queue in sequence according to the sequence defined in the test excitation vector time sequence table;
s52: when the test excitation signal output by the test excitation single output channel is idle, the high-speed time sequence controller accesses the test excitation single output channel into a channel corresponding to the channel number stored in the head of the retention time queue, and refreshes the retention time again;
s53: and deleting the channel number x of the queue in the hold time queue from the head of the hold time queue and adding the channel number x into the tail of the queue again.
3. The method according to claim 1, wherein the operating frequency of the high-speed timing controller in step S1 is greater than or equal to 1 GHz.
4. The method according to claim 1, wherein N in step S1 is an integer greater than or equal to 2.
5. The method as claimed in claim 1, wherein the test stimulus output channel of the automatic test equipment has a pulse amplitude of 0-10V and a pulse width of 10ns or more in the step S2.
6. The method according to claim 1, wherein the high speed output holding circuit in step S4 is a high speed sample and output holding circuit, the sample time is less than or equal to 1ns, and the hold time is greater than or equal to 100 us.
7. An expansion device for testing an excitation output channel of automatic test equipment comprises a high-speed time schedule controller, a testing excitation single output channel and a high-speed output holding relay circuit group, it is characterized in that the high-speed output holding relay circuit group comprises N groups of high-speed output holding circuits and the combination of relay circuits, the high-speed time sequence controller controls the test excitation single output channel to output the test excitation time sequence signal of the channel to be held according to the test excitation vector time sequence table generated by the high-speed time sequence controller, the time sequence signal is respectively accessed to the combination of the N groups of high-speed output holding circuits and the relay circuits, when a group of output timing signals is needed, firstly, the relays of the group are opened, the timing signals are transmitted to the DUT end of the chip to be tested, then the relay is closed and the high-speed output holding circuit is started, the output signals of the group are held, and the output signals of the group can be refreshed again in the next test excitation single output channel output gap.
8. The expanding device for the test excitation output channel of the automatic test equipment as claimed in claim 7, wherein the high-speed output holding relay circuit group is a high-speed sampling output holding relay circuit group, and comprises a combination of N groups of high-speed sampling output holding circuits and relay circuits.
9. The expanding apparatus of claim 7, wherein a hold time queue is provided, the channel number of the channel to be held is added to the hold time queue, and the test stimulus timing signals of the channels to be held are refreshed according to the sequence of the channels to be held in the hold time queue.
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Cited By (2)
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| CN114252756A (en) * | 2021-11-02 | 2022-03-29 | 航天科工防御技术研究试验中心 | ATE-based voltage regulator chip testing device and method |
| CN116449792A (en) * | 2022-01-10 | 2023-07-18 | 纬湃汽车电子(长春)有限公司 | ECU test box and ECU and vehicle including the test box |
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