CN112866102A - Network isolation circuit, method and device - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/18—Loop-free operations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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Abstract
The invention provides a network isolation circuit, a method and a device, wherein the circuit comprises a dial switch, a main chip 1, a main chip 2, a change-over switch chip, a first memory, a second memory, a switch chip and three RJ45 ports; the detection pins of the main chip 1 and the main chip 2 are connected with the middle pin of the dial switch; the main chip 1 and the main chip 2 are connected to a change-over switch chip; the main chip 1 is connected with a first RJ45 port, and the main chip 2 is connected with a second RJ45 port; the first memory is communicated with the switch chip through the switch chip, and the second memory is communicated with the switch chip through the switch chip; the switch chip is connected with a third RJ45 port. The state of the isolation network is selected through the dial switch, different network links are isolated, a plurality of networks are prevented from being interconnected to send a large number of data packets, and the network speed and the network performance are improved.
Description
Technical Field
The present invention relates to the field of network isolation technologies, and in particular, to a network isolation circuit, method, and apparatus.
Background
At present, network equipment on the market generally uses a switch chip, and network storms are easy to occur. One of the main reasons for the generation of network storms is: the two ends of a twisted pair are inserted into different ports of the same switch, which causes the sudden decline of network performance and makes it very difficult to open the web page. This failure is typical of a network loop. The network loop is generated generally because both ends of a physical network line are simultaneously connected to a network device. Therefore, there is a need for improvements in the prior art to address the problem of network storms due to network loops.
Disclosure of Invention
The invention aims to provide a network isolation circuit, a method and a device, which can solve the problems of network slowness and network performance reduction caused by network loops in the prior art.
The purpose of the invention is realized by the following technical scheme:
in a first aspect, the present invention provides a network isolation circuit, which includes a dial switch, a main chip 1, a main chip 2, a switch chip, a first memory, a second memory, a switch chip, and three RJ45 ports; the detection pins of the main chip 1 and the main chip 2 are connected with the middle pin of the dial switch; the main chip 1 and the main chip 2 are connected to a change-over switch chip; the main chip 1 is connected with a first RJ45 port, and the main chip 2 is connected with a second RJ45 port; the first memory is communicated with the switch chip through the switch chip, and the second memory is communicated with the switch chip through the switch chip; the switch chip is connected with a third RJ45 port.
Further, the dial switch comprises a pin 1, a pin 2 and a pin 3; the pin 2 is used as an intermediate pin and connected to the detection pins of the main chip 1 and the main chip 2.
Further, the main chip 1 and the main chip 2 are respectively connected with the switch chip through a pull-up circuit, wherein the pull-up circuit comprises a resistor RU27, a resistor RU28, a resistor RU31, a resistor RU32, a resistor RU1 and a resistor RU 2; the main chip 1 and the main chip 2 at least comprise an inspection pin, a change-over switch control pin 1 and a change-over switch control pin 2; the switch chip at least comprises a pin HSD0+, a pin HSD0-, a pin HSD2+, a pin HSD2-, a pin SEL0 and a pin SEL 1; the change-over switch control pin 1 of the main chip 1 is connected to a pin SEL1 of the change-over switch chip through a resistor RU31, and the change-over switch control pin 2 of the main chip 1 is connected to a pin SEL0 of the change-over switch chip through a resistor RU 32; the change-over switch control pin 1 of the main chip 2 is connected to a pin SEL1 of the change-over switch chip through a resistor RU1, and the change-over switch control pin 2 of the main chip 2 is connected to a pin SEL0 of the change-over switch chip through a resistor RU 2; resistor RU27 is connected between +3.3V and pin SEL1, and resistor RU28 is connected between +3.3V and pin SEL 0.
Further, the first memory or the second memory at least comprises a pin VCC, a pin WP, a pin SCL and a pin SDA; the first memory is connected with the change-over switch chip through a first peripheral circuit, and the second memory is connected with the change-over switch chip through a second peripheral circuit.
Furthermore, the SCL pin of the first memory is connected with a pin HSD 0' of the change-over switch chip, and the SDA pin of the first memory is connected with a pin HSD0+ of the change-over switch chip; the first peripheral circuit comprises a resistor RN126, a resistor RN127, a resistor RN147 and a capacitor CN 129; the capacitor CN129 is connected between +3.3V and the ground; the resistor RN126 is connected between +3.3V and a pin WP of the first memory; the resistor RN127 is connected between +3.3V and the pin SDA of the first memory; the resistor RN147 is connected between +3.3V and the pin SCL of the first memory.
Furthermore, the SCL pin of the second memory is connected with a pin HSD2 of the switch chip, and the SDA pin of the second memory is connected with a pin HSD2+ of the change-over switch chip; the second peripheral circuit comprises a resistor RN155, a resistor RN156, a resistor RN157 and a capacitor CN 130; the capacitor CN130 is connected between +3.3V and the ground; the resistor RN155 is connected between +3.3V and a pin WP of the second memory; the resistor RN156 is connected between +3.3V and the pin SDA of the second memory; the resistor RN157 is connected between +3.3V and the pin SCL of the second memory.
In a second aspect, the present invention provides a network isolation method, which is applied to the network isolation circuit, and includes the following steps:
and step 2, the main chip 1 or the main chip 2 controls the internal switch of the change-over switch chip through the two change-over switch control pins according to the state of the dial switch, so that different network links are conducted in different dial switch states.
Further, the step 2 comprises: when the state of the dial switch is high level, the main chip 1 or the main chip 2 controls the change-over switch control pin 1 to output high level, and the change-over switch control pin 2 outputs low level; the internal switch is switched by the switch chip, so that the second memory is conducted with the switch chip; when the state of the dial switch is low level, the main chip 1 or the main chip 2 controls the change-over switch control pin 1 and the change-over switch control pin 2 to output low level, and the change-over switch chip switches over the internal switch, so that the first memory is conducted with the switch chip.
Furthermore, the first memory and the second memory store isolation state software corresponding to the state of the dial switch, and the isolation state software records the network isolation state.
In a third aspect, the present invention provides a network isolation apparatus, including the network isolation circuit.
According to the network isolation circuit, the network isolation method and the network isolation device, the state of the isolation network can be selected through the dial switch, different network links are isolated, a plurality of networks are prevented from being interconnected to send a large number of data packets, and the network speed and the network performance are improved.
Drawings
FIG. 1 is a block circuit diagram of a network isolation device of the present invention;
FIG. 2 is a circuit schematic of the present dip switch;
FIG. 3 is a schematic circuit diagram of the main chip 1 connected to the switch chip through a pull-up circuit;
fig. 4 is a schematic circuit diagram of the first peripheral circuit and the second peripheral circuit connected to the switcher chip.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
The invention relates to a network isolation circuit designed based on a switch chip RTL8367, which is not limited to be available by the RTL8367 chip and is suitable for all switch chips supporting network isolation.
The network isolation circuit of the invention, as shown in fig. 1, includes a dial switch, a main chip 1, a main chip 2, a switch chip, a memory EEPROM1, a memory EEPROM2, a switch chip, and 3 RJ45 ports. The main chip 1 and the main chip 2 at least include an inspection pin, a changeover switch control pin 1, and a changeover switch control pin 2. The switch chip at least comprises a pin D +, a pin D-, a pin HSD0+, a pin HSD0-, a pin HSD2+, a pin HSD2-, a pin SEL0 and a pin SEL 1.
And the detection pins of the main chip 1 and the main chip 2 are connected to the middle pin of the dial switch to detect the level of the middle pin of the dial switch. The main chip 1 is connected to the switch chip through two IO ports, and the main chip 2 is connected to the switch chip through two IO ports. The main chip 1 is connected with the RJ45 port 1, and the main chip 2 is connected with the RJ45 port 2. The memory EEPROM1 communicates with the switch chip through the switch chip, and the memory EEPROM2 communicates with the switch chip through the switch chip. The switch chip is connected to RJ45 port 3.
The detection pin of the main chip 1 or the detection pin of the main chip 2 detects the level of the middle pin of the dial switch. In the invention, the main chip 1 and the main chip 2 can detect the level of the middle pin of the dial switch, the main chip 1 is used as the default main chip for detecting the middle pin of the dial switch, and when the main chip 1 has a functional fault and cannot normally detect, the main chip 2 is started to detect. The main chip 1 and the main chip 2 have the same level detection mode of the middle pin of the dial switch, and the main chip 1 is taken as an example to explain the working principle of fig. 1:
the dial switch can be dialed to 0 or 1, the middle pin is at high level when the dial switch is dialed to 1, and the middle pin is at low level when the dial switch is dialed to 0. The detection pin of the main chip 1 detects the state of the dial switch through an IO port, if the dial switch is dialed to 1, the detection pin of the main chip 1 detects 3.3V (high level), and if the dial switch is dialed to 0, the detection pin of the main chip 1 detects 0V (low level). The main chip 1 outputs two levels to the change-over switch chip through the change-over switch control pin 1 and the change-over switch control pin 2 according to the level detected by the detection pin, and controls the on-off state of the change-over switch chip. When the level detected by the detection pin of the main chip 1 is low level, the control switch control pin 1 and the control switch control pin 2 both output low level. At this time, the switch chip switches the internal switch, so that the memory EEPROM1 is conducted with the switch chip. The switch chip reads the pre-programmed network isolation status in the memory EEPROM 1. When the level detected by the detection pin of the main chip 1 is high level, the control pin 1 of the change-over switch is controlled to output high level, and the control pin 2 of the change-over switch outputs low level. At this time, the switch chip switches the internal switch, so that the memory EEPROM2 is conducted with the switch chip. The switch chip reads the pre-programmed network isolation status in the memory EEPROM 2. The conduction relationship between the control pin of the switch and the memory is shown in the following table 1:
| selector |
Selector |
Direction of conduction |
| 0 | 0 | EEPROM1 is connected with the switch chip and the two |
| 1 | 0 | EEPROM2 is connected with the switch chip and the two |
| 1 | 1 | NC |
| 0 | 1 | NC |
TABLE 1
The memories EEPROM1 and EEPROM2 can be programmed with isolation state software corresponding to the dial-up switches 0 and 1 in advance, and the isolation state software records the network isolation state. The memories EEPROM1 and EEPROM2 communicate with the switcher chip through the IIC. For example, in the memory EEPROM1, when the dial switch is 0, the network connection between the main chip 1 and the RJ45 port 1 is disconnected, the network connection between the main chip 2 and the RJ45 port 2 is disconnected, the RJ45 port 3 operates, and the main chip 1 and the main chip 2 are networked through the RJ45 port 3 connected to the switch chip. In the memory EEPROM2, when the dial switch is 1, the network connection between the switch chip and the RJ45 port 3 is disconnected, the RJ45 port 1 and the RJ45 port 2 work, the main chip 1 accesses the internet through the RJ45 port 1, and the main chip 2 accesses the internet through the RJ45 port 2. It should be noted that the burned network isolation status in the memories EEPROM1 and EEPROM2 is not limited thereto, and the above is only an example, and the specific case of the network isolation status should not be taken as a limitation to the present invention. The relationship between the dial switch and the network isolation state is shown in table 2:
TABLE 2
Further, in a preferred embodiment of the present application, a schematic circuit diagram of the dip switch is shown in fig. 2, and includes pin 1, pin 2, and pin 3. Pin 2 is connected as an intermediate pin to the sense pin of the main chip. Pin 1 is connected to +3.3V through resistor RN154, and pin 3 is connected to ground through resistor RN 158. Pin 1, pin 2, and pin 3 are disconnected from each other when the dial button is in the neutral position. When the dial button is dialed to the position of pin 1, pin 1 and pin 2 are connected, and pin 2 is at a low level. When the dial button is dialed to the position of pin 3, pin 3 is connected with pin 2, and pin 2 is at +3.3V high level.
Further, in a preferred embodiment of the present application, the master chip 1 and the master chip 2 are respectively connected to the switch chip UU3 through a pull-up circuit, as shown in fig. 3. The pull-up circuit comprises a resistor RU27, a resistor RU28, a resistor RU31, a resistor RU32, a resistor RU1 and a resistor RU2, wherein a switch control pin 1 of the main chip 1 is connected to a pin SEL1 of the switch chip through a resistor RU31, and a switch control pin 2 of the main chip 1 is connected to a pin SEL0 of the switch chip through a resistor RU 32. The switch control pin 1 of the main chip 2 is connected to a pin SEL1 of the switch chip through a resistor RU1, and the switch control pin 2 of the main chip 2 is connected to a pin SEL0 of the switch chip through a resistor RU 2. Resistor RU27 is connected between +3.3V and pin SEL1, and resistor RU28 is connected between +3.3V and pin SEL 0.
Taking the master chip 1 controlling the switch as an example, RU27 and RU28 are pull-up resistors, and RU31 and RU32 are resistors connected to the master chip 1 and the switch chip. RU1 and RU2 are resistors connected between the main chip 2 and the switcher chip, two alternative upper pieces.
The switching chip pins D + and D-are connected to the SDA and SCL pins of the switch chip, the switching chips HSD0+ and HSD 0-are connected to the SDA and SCL pins of the EEPROM1, and the switching chips HSD2+ and HSD 2-are connected to the SDA and SCL pins of the EEPROM 2. The conduction relationship between the control pin of the switch and the memory is shown in table 1 above.
Further, in a preferred embodiment of the present application, the memory EEPROM1 or the memory EEPROM2 includes at least pin VCC, pin WP, pin SCL, and pin SDA. The memory EEPROM1(UN8) is connected to the switcher chip through the first peripheral circuit, and the memory EEPROM2(UN1) is connected to the switcher chip through the second peripheral circuit, as shown in fig. 4.
The SCL pin of the memory EEPROM1 is connected with the pin HSD0 of the switch chip, and the SDA pin of the memory EEPROM1 is connected with the pin HSD0+ of the switch chip. The first peripheral circuit includes a resistor RN126, a resistor RN127, a resistor RN147 and a capacitor CN 129. Capacitor CN129 is connected between +3.3V and ground. Resistor RN126 is connected between +3.3V and pin WP of memory EEPROM 1. Resistor RN127 is connected between +3.3V and pin SDA of memory EEPROM 1. Resistor RN147 is connected between +3.3V and pin SCL of memory EEPROM 1.
The memory EEPROM1 is powered by +3.3V, and IIC communication is carried out between the SDA and the SCL and the switch chip, so that the switch chip reads the burnt software of the EEPROM chip. RN127 and RN147 are pull-up resistors for SDA and SCL, respectively, and RN126 is a reserved write protection pin pull-up, default to no-load.
The SCL pin of the memory EEPROM2 is connected with the pin HSD2 of the switch chip, and the SDA pin of the memory EEPROM2 is connected with the pin HSD2+ of the switch chip. The second peripheral circuit includes a resistor RN155, a resistor RN156, a resistor RN157, and a capacitor CN 130. Capacitor CN130 is connected between +3.3V and ground. Resistor RN155 is connected between +3.3V and pin WP of memory EEPROM 2. The resistor RN156 is connected between +3.3V and pin SDA of the memory EEPROM 2. Resistor RN157 is connected between +3.3V and pin SCL of memory EEPROM 2.
The working principle of the second peripheral circuit is the same as that of the first peripheral circuit, and is not described herein.
The network isolation method comprises the following steps:
and step 1, detecting the state of the dial switch by a detection pin 1 of the main chip or a detection pin 2 of the main chip.
The state of the dial switch indicates whether the level of the middle pin of the dial switch is high or low. The specific principles of the dip switch have been described above and will not be described in detail here.
And step 2, the main chip 1 or the main chip 2 controls the internal switch of the change-over switch chip through the two change-over switch control pins according to the state of the dial switch, so that different network links are conducted in different dial switch states.
Specifically, in a preferred embodiment of the present application, step 2 includes: when the state of the dial switch is high level, the main chip 1 or the main chip 2 controls the change-over switch control pin 1 to output high level, and the change-over switch control pin 2 outputs low level. The switch chip switches the internal switch so that the memory EEPROM2 is conductive with the switch chip. When the state of the dial switch is low level, the main chip 1 or the main chip 2 controls the change-over switch control pin 1 and the change-over switch control pin 2 to output low level. The switch chip switches the internal switch so that the memory EEPROM1 is conductive with the switch chip.
Further, the memories EEPROM1 and EEPROM2 can be programmed with isolation state software corresponding to the dial-up switches 0 and 1 in advance, and the isolation state software records the network isolation state.
Furthermore, in the memory EEPROM1, when the dial switch is 0, the network connection between the main chip 1 and the RJ45 port 1 is disconnected, the network connection between the main chip 2 and the RJ45 port 2 is disconnected, the RJ45 port 3 operates, and the main chip 1 and the main chip 2 are networked through the RJ45 port 3 connected to the switch chip. In the memory EEPROM2, when the dial switch is 1, the network connection between the switch chip and the RJ45 port 3 is disconnected, the RJ45 port 1 and the RJ45 port 2 work, the main chip 1 accesses the internet through the RJ45 port 1, and the main chip 2 accesses the internet through the RJ45 port 2. It should be noted that the burned network isolation status in the memories EEPROM1 and EEPROM2 is not limited thereto, and the above is only an example, and the specific case of the network isolation status should not be taken as a limitation to the present invention.
A network isolation apparatus comprising the network isolation circuit is configured to perform the network isolation method.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; may be mechanically coupled, may be electrically coupled or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The above description is for the purpose of illustrating embodiments of the invention and is not intended to limit the invention, and it will be apparent to those skilled in the art that any modification, equivalent replacement, or improvement made without departing from the spirit and principle of the invention shall fall within the protection scope of the invention.
Claims (10)
1. A network isolation circuit is characterized by comprising a dial switch, a main chip 1, a main chip 2, a change-over switch chip, a first memory, a second memory, a switch chip and three RJ45 ports; the detection pins of the main chip 1 and the main chip 2 are connected with the middle pin of the dial switch; the main chip 1 and the main chip 2 are connected to a change-over switch chip; the main chip 1 is connected with a first RJ45 port, and the main chip 2 is connected with a second RJ45 port; the first memory is communicated with the switch chip through the switch chip, and the second memory is communicated with the switch chip through the switch chip; the switch chip is connected with a third RJ45 port.
2. The network isolation circuit of claim 1, wherein the dip switch comprises pin 1, pin 2, and pin 3; the pin 2 is used as an intermediate pin and connected to the detection pins of the main chip 1 and the main chip 2.
3. The network isolation circuit of claim 1, wherein the main chip 1 and the main chip 2 are respectively connected with the switch chip through a pull-up circuit, and the pull-up circuit comprises a resistor RU27, a resistor RU28, a resistor RU31, a resistor RU32, a resistor RU1 and a resistor RU 2; the main chip 1 and the main chip 2 at least comprise an inspection pin, a change-over switch control pin 1 and a change-over switch control pin 2; the switch chip at least comprises a pin HSD0+, a pin HSD0-, a pin HSD2+, a pin HSD2-, a pin SEL0 and a pin SEL 1; the change-over switch control pin 1 of the main chip 1 is connected to a pin SEL1 of the change-over switch chip through a resistor RU31, and the change-over switch control pin 2 of the main chip 1 is connected to a pin SEL0 of the change-over switch chip through a resistor RU 32; the change-over switch control pin 1 of the main chip 2 is connected to a pin SEL1 of the change-over switch chip through a resistor RU1, and the change-over switch control pin 2 of the main chip 2 is connected to a pin SEL0 of the change-over switch chip through a resistor RU 2; resistor RU27 is connected between +3.3V and pin SEL1, and resistor RU28 is connected between +3.3V and pin SEL 0.
4. The network isolation circuit of claim 1, wherein the first memory or the second memory comprises at least pin VCC, pin WP, pin SCL, and pin SDA; the first memory is connected with the change-over switch chip through a first peripheral circuit, and the second memory is connected with the change-over switch chip through a second peripheral circuit.
5. The network isolation circuit of claim 4, wherein the SCL pin of the first memory is connected to pin HSD0 "of the switch chip, and the SDA pin of the first memory is connected to pin HSD0+ of the switch chip; the first peripheral circuit comprises a resistor RN126, a resistor RN127, a resistor RN147 and a capacitor CN 129; the capacitor CN129 is connected between +3.3V and the ground; the resistor RN126 is connected between +3.3V and a pin WP of the first memory; the resistor RN127 is connected between +3.3V and the pin SDA of the first memory; the resistor RN147 is connected between +3.3V and the pin SCL of the first memory.
6. The network isolation circuit of claim 4, wherein the SCL pin of the second memory is connected to pin HSD2 "of the switch chip, and the SDA pin of the second memory is connected to pin HSD2+ of the switch chip; the second peripheral circuit comprises a resistor RN155, a resistor RN156, a resistor RN157 and a capacitor CN 130; the capacitor CN130 is connected between +3.3V and the ground; the resistor RN155 is connected between +3.3V and a pin WP of the second memory; the resistor RN156 is connected between +3.3V and the pin SDA of the second memory; the resistor RN157 is connected between +3.3V and the pin SCL of the second memory.
7. A network isolation method applied to the network isolation circuit of any one of claims 1 to 6, comprising the steps of:
step 1, detecting the state of a dial switch by a detection pin 1 of a main chip or a detection pin 2 of the main chip;
and step 2, the main chip 1 or the main chip 2 controls the internal switch of the change-over switch chip through the two change-over switch control pins according to the state of the dial switch, so that different network links are conducted in different dial switch states.
8. The network isolation method according to claim 7, wherein the step 2 comprises: when the state of the dial switch is high level, the main chip 1 or the main chip 2 controls the change-over switch control pin 1 to output high level, and the change-over switch control pin 2 outputs low level; the internal switch is switched by the switch chip, so that the second memory is conducted with the switch chip; when the state of the dial switch is low level, the main chip 1 or the main chip 2 controls the change-over switch control pin 1 and the change-over switch control pin 2 to output low level, and the change-over switch chip switches over the internal switch, so that the first memory is conducted with the switch chip.
9. The network isolation method of claim 8, wherein the first memory and the second memory store isolation status software corresponding to the state of the dial-up switch, and the isolation status software records the network isolation status.
10. A network isolation device comprising the network isolation circuit of any of claims 1 to 6.
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| CN202011559331.0A CN112866102B (en) | 2020-12-25 | 2020-12-25 | Network isolation circuit, method and device |
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| CN202011559331.0A CN112866102B (en) | 2020-12-25 | 2020-12-25 | Network isolation circuit, method and device |
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