CN112860000B - A Matching Circuit Biasing Method with Large Voltage Margin Range - Google Patents

Abstract

The invention relates to a matching circuit biasing method with a large voltage margin range, including a main circuit and a bias generating circuit. _The main circuit includes transistors M1 and _M2 , and the power supply _Vdd sequentially passes through the resistor R, the transistors _M2 and _M1 grounding; the bias generating circuit includes transistors M3 _{- M6} , the power supply _{Vdd is grounded through the current mirror I0, the transistors M4 and M3 in sequence, and the power supply Vdd is grounded through} the current mirror _I2 , the transistors _M6 and _M5 in sequence _; A voltage margin boost circuit is provided in the bias circuit. The voltage margin boost circuit includes a resistor R _s and a current source _{Is. A resistor R s is} connected in series between the drain of the transistor M4 and the gate of the transistor M ₃ . The current sources I _s are connected in series in the upper and lower directions of R _s , and a transistor M _x is inserted between the transistors M ₅ and M ₆ to increase V _g2 to I _s R _s . The present invention can effectively improve the voltage margin range of the current mirror, and is more suitable for applications related to a large voltage margin range.

Description

A Matching Circuit Biasing Method with Large Voltage Margin Range

technical field

The invention relates to the technical field of integrated circuit design and manufacture, in particular to a matching circuit biasing method with a large voltage margin range.

Background technique

In analog circuits, current mirror matching and its bias circuit are very common and important circuit elements. Usually, since the current mirror matching and its bias circuit are not sensitive to the voltage margin range, the voltage margin range of the current mirror matching and its bias circuit is often compressed as much as possible, while providing other transistors with a larger voltage margin. voltage margin range. However, in some occasions, such as low noise amplifier input transistors, it is necessary to achieve good matching of the current mirror, and its bias circuit needs to have a large voltage margin range.

The traditional current mirror matching circuit and its bias circuit are shown in Figure ₁ , in which the transistor _M2 in the main circuit is called the Cascode tube of the transistor M1, and the transistor M4 in the corresponding bias circuit is called the Cascode tube _of the transistor M3 _.

The gate bias voltage V _g1 of the main circuit M ₁ is determined by connecting the gate of M ₃ in the bias circuit to the drain of M ₄ (point D), and the gate bias voltage V _g2 of the main circuit M ₂ is determined by M ₅ and M ₆ in the bias circuit are determined after being connected in series. The current mirror multiple is determined by the aspect ratio W ₃ /L ₃ of the transistor M ₃ and the aspect ratio W ₁ /L ₁ of the transistor M _1. If n*W ₃ /L ₃ =W ₁ /L ₁ , the main circuit current I ₁ =n*I ₀ .

Although M ₁ and M ₃ are well matched in the conventional current mirror matching circuit shown in FIG. 1 , the drain-source voltage of M ₁ is small, that is, the voltage VA at point _A in FIG. 1 is small. The specific reasons are as follows.

The transistor M ₄ in the bias circuit, the voltage V _D (=V _g1 ) of the drain point D, and the voltage V _C of the source point C have a relationship V _g1 =V _D =V _C +V _ds4 , where V _ds4 is M The drain-source voltage of ₄ is a value not less than 0, depending on the specific circuit design. In the main circuit V _A =V _g2 -V _th , when the main circuit and the bias circuit current mirror match well, there is V _A =V _C <V _D =V _g1 , that is, the drain voltage V _A of M1 in the main circuit is lower than gate voltage V _g1 . In general design, the gate voltage V _g ≈ 0.2+V _th , where V _th is a constant between 0.5-0.8 V. Here, take V _th = 0.5 V as an example, that is, V _g1 ≈ 0.7, which leads to M ₁ has the phenomenon that the drain-source voltage V _ds cannot exceed 0.7V, that is, M ₁ has the phenomenon that the drain-source voltage is small, that is, the drain-source voltage margin range of the transistor M ₁ is small.

If the gate voltage V _g2 of M2 is simply increased in order to obtain _a larger M1 drain-source voltage, although the voltage at point A can be increased, since V _C <V _D =V _g1 in the bias circuit, it will lead to V _A > V _C , which results in that the current mirror between the main circuit and the bias circuit cannot be well matched, resulting in a large deviation between I ₁ and n*I ₀ , resulting in a large deviation in the performance of the main circuit, especially when the M ₁ When the drain-source voltage V _ds is raised to 1V or even 2V to obtain a large voltage margin, the deviation between I ₁ and n*I ₀ caused by V _A > V _C may reach 20% or even higher.

SUMMARY OF THE INVENTION

In order to solve the existing technical problems, the present invention provides a matching circuit biasing method with a large voltage margin range.

The specific content of the present invention is as follows: a matching circuit bias method with a large voltage margin range, including a main circuit and a bias generating circuit, the main circuit includes transistors M ₁ and M ₂ , and the power supply V _dd passes through the resistor R and the transistor M in turn. ₂ and M1 are grounded _; the bias generating circuit includes transistors M3 _{- M6} , the power supply _Vdd is grounded through the current mirror _I0 , transistors _M4 and _M3 in turn, and the power supply _Vdd is connected to the ground through the current mirror _I2 , transistors _M6 and _M5 is grounded, the gate bias voltage _{Vg1 of} transistor M1 is determined by connecting the gate _of transistor M3 to the drain of M4, and the gate bias voltage _Vg2 of transistor _M2 is determined by transistor _M5 in the _bias circuit and _M6 are determined after being connected in series; a voltage margin boosting circuit is provided in the bias circuit, and the voltage margin boosting circuit includes a resistor R _s and a current source _Is , between the drain of the transistor M4 and the gate _of the transistor M3 A resistor R _s is connected in series between the resistors R _s and the current sources Is are connected in series in the upper and lower directions of the resistor R _s . A transistor M _x is inserted between the transistors M ₅ and M ₆ to increase V _g2 to I _s R _s .

Further, the currents I ₀ , I ₂ and Is are generated by a current generating circuit, and the current generating circuit includes PMOS transistors M _{p1 -M p10} , NMOS transistors _{Mn1 -Mn4} , an input reference current I _in , a resistor R _p and a resistor R _n ; the power supply _Vdd is connected to the sources of the PMOS transistors _Mp1 , _{Mp3, Mp5, Mp7 , and Mp9} respectively, the PMOS transistors _Mp1 and _Mp2 are connected in series, the PMOS transistors _Mp3 and _Mp4 are connected in series, the PMOS transistors _Mp5 and M _p6 is connected in series, PMOS transistors M _p7 and M _p8 are connected in series, PMOS transistors M _p9 and M _p10 are connected in series, the drain of PMOS transistor M _p1 is connected to ground through PMOS transistor M _p2 , resistor R _p and input reference current I _{in in} turn, and PMOS transistor M The gates of _p1 , _Mp3 , _{Mp5 , Mp7 and Mp9 are connected to each other and to one end of the resistor Rp, and the gates of the PMOS transistors Mp2 , Mp4 , Mp6 , Mp8 and Mp10 are connected to each other and connected to} each other. to the other end of the resistor R _p ; the NMOS transistors Mn2 and _Mn1 are connected in series and then grounded, the NMOS transistors _Mn4 and _Mn3 are connected in series and then grounded, the drain of the _PMOS transistor _Mp10 is connected to the drain of the NMOS transistor _Mn2 through the resistor _Rn , One end of the resistor _Rn close to the PMOS transistor _Mp10 is connected to the gates of the NMOS transistors _Mn2 and _Mn4 respectively, and the other end of the _Rn is connected to the gates of the NMOS transistors _Mn1 and _Mn3 respectively; the drain of the PMOS transistor _Mp4 The output current I ₂ , the drain of the PMOS transistor M _p6 outputs the current I ₀ , the drain of the PMOS transistor M _p8 outputs the current Is and flows into the resistor R _s from the power supply terminal, and the drain of the NMOS transistor _Mn4 outputs the current I _s and _flows from Resistor _Rs flows out to ground.

Further, the width-length ratio of the PMOS transistor and the NMOS transistor in the current generating circuit satisfies

_Sp1 : _Sp3 : _Sp5 : _Sp7 : _Sp9 = _Sp2 : _Sp4 : _Sp6 : _Sp8 : _Sp10 ,

_{Sn1 : Sn3 = Sn2} : _Sn4

Wherein, S _{p1 ˜S p10} are the width-to-length ratios of the PMOS transistors M _{p1 ˜M p10} , respectively, and _{Sn 1 ˜S n4} are the width-to-length ratios of the NMOS transistors Mn1 ˜M n4 , respectively.

Further, the width-length ratio of the PMOS transistor and the NMOS transistor in the current generating circuit satisfies

_Sp7 : _Sp9 = _Sp8 : _Sp10 =1

_{Sn1 : Sn3 = Sn2} : _Sn4 =1.

Further, several transistors _Mx are connected in series between the drain of the transistor _M5 and the source of _M6 , and the gates of the transistors _M5 , _M6 and _Mx are all connected to each other.

Further, the resistor R _s is a polysilicon resistor, and the resistance value is integrated on-chip through the process itself.

The present invention effectively improves the voltage margin range corresponding to the current mirror transistor on the premise of ensuring that the current mirror matching and its bias circuit have the same matching as the traditional current mirror. Compared with the traditional current mirror matching and its bias circuit with a low voltage margin range, the current mirror voltage margin range can be effectively improved, and it is more suitable for applications with a large voltage margin range.

Description of drawings

The specific embodiments of the present invention will be further explained below in conjunction with the accompanying drawings.

Figure 1 shows the traditional main circuit and its matching bias circuit;

2 is a schematic diagram of a matching circuit biasing method with a large voltage margin range of the present invention;

3 is a schematic diagram of a current generating circuit of the present invention;

Fig. 4 _is the Mx series connection diagram of the present invention.

Detailed ways

With reference to FIGS. 2 to 4 , this embodiment discloses a matching circuit biasing method with a large voltage margin range. By setting up a voltage margin boost circuit in the traditional bias circuit to increase the voltage margin range corresponding to the current mirror transistor, and then by inserting an appropriate transistor Mx between M ₅ and M ₆ to increase V _g2 to _{Is R s ,} it is possible to The voltage _{Is R s at} point A is boosted synchronously, while ensuring that VA _{= VC} , that is, while boosting the voltage at point A, it is ensured that the current sources of the main circuit and the bias circuit are well matched.

The specific structure is as follows:

The main circuit includes transistors M ₁ and M ₂ , and the power supply V _dd is connected to ground through a resistor R and transistors M ₂ and M ₁ in sequence.

The bias generating circuit includes transistors M ₃ to M ₆ , the power supply V _dd is grounded through the current mirror I ₀ , transistors M ₄ and M ₃ in sequence, the power supply V _dd is grounded through the current mirror I ₂ , transistors M ₆ and M ₅ in sequence, and the transistor M _The gate bias voltage _Vg1 of ₁ is determined by connecting the gate of transistor M3 to the drain of M4, and the gate bias voltage _{Vg2 of} transistor _M2 is determined by the series connection of transistors _M5 and _M6 in the bias circuit. Sure.

A voltage margin boost circuit is provided in the bias circuit. The voltage margin boost circuit includes a resistor R _s and a current source _{Is. A resistor R s is} connected in series between the drain of the transistor M4 and the gate of the transistor M ₃ . The upper and lower directions of R _s are connected in series with current sources _Is , the upper current source _Is is connected to the power supply V _dd , and the lower current source Is is _grounded . Transistor _Mx is inserted between transistors _M5 and _M6 , _{boosting Vg2 to IsRs .}

A resistor R _s is connected in series between V _D and V _g1 in the bias circuit, and an equal current source _Is is connected in series in the upper and lower directions of R _s , thus V _D =V _g1 +I _s R _s . V _g1 is mainly determined by I ₀ and M ₃ , so it does not change. Considering V _D =V _C +V _ds4 , it can be obtained that V _C =V _g1 -V _ds4 +I _s R _s , which improves _Is R _s compared to the original circuit. At this time, by inserting an appropriate transistor Mx between M ₅ and M ₆ to increase V _g2 to Is R _s , the voltage _Is R _s at point A can be boosted _{synchronously} , while ensuring that VA _{= VC} , that is, when boosting point A The voltage of the main circuit and the current source of the bias circuit are well matched.

In practical applications, it is only necessary to set I _s to a small current component, and select the appropriate value of R _s according to the required voltage margin improvement at point A.

In this embodiment, the current in the bias generating circuit is generated by the current generating circuit, and the structure of the current generating circuit is as follows:

It includes PMOS transistors _{Mp1-Mp10 ,} NMOS transistors _Mn1 - _Mn4 , input reference current _Iin , resistor _Rp and resistor _Rn ; the power supply _Vdd is connected to the PMOS transistors _Mp1 , _Mp3 , _Mp5 , _Mp7 , The source of M _p9 , the PMOS transistors M _p1 and M _p2 are connected in series, the PMOS transistors M _p3 and M _p4 are connected in series, the PMOS transistors M _p5 and M _p6 are connected in series, the PMOS transistors M _p7 and M _p8 are connected in series, and the PMOS transistors M _p9 and M _p10 are connected in series , the drain of the PMOS transistor M _p1 is grounded sequentially through the PMOS transistor M _p2 , the resistor R _p and the input reference current I _in , and the gates of the PMOS transistors M _p1 , M _p3 , M _p5 , M _p7 , and M _p9 are connected to each other and to One end of the resistor _Rp , the gates of the PMOS transistors _{Mp2, Mp4, Mp6, Mp8, and Mp10 are connected to each} other and connected to the other end of the resistor _Rp ; the NMOS transistors _Mn2 and _Mn1 are connected in series and then grounded, and the NMOS transistor Mn4 and _Mn3 are connected in series and then grounded. The drain of the PMOS transistor _Mp10 is connected to the drain of the NMOS transistor _Mn2 through the resistor _Rn . One end of the resistor _Rn close to the PMOS transistor _Mp10 is _connected to the gates of the NMOS transistors _Mn2 and _Mn4 respectively. The poles are connected to each other, and the other ends of R _n are respectively connected to the gates of the NMOS transistors _Mn1 and _Mn3 .

On the basis of the input reference current I _in , through the current generation circuit, four currents can be generated, I ₀ , _Is (including P tube output and N tube output) and I ₂ . The drain of the PMOS transistor M _p4 outputs the current I ₂ , the drain of the PMOS transistor M _p6 outputs the current I ₀ , the drain of the _PMOS transistor M _p8 outputs the current Is and flows into the resistor R _s from the power supply terminal, and the drain of the NMOS transistor _Mn4 The pole output current Is and _flows from the resistor _Rs to ground.

Let Sp _{= Wp} / _Lp be the aspect ratio of the PMOS transistor, _Sn = _Wn / _Ln the aspect ratio of the NMOS transistor, where W and P are the width and length of the transistor, respectively. The size relationship of each transistor in Figure 3 satisfies the

_Sp1 : _Sp3 : _Sp5 : _Sp7 : _Sp9 = _Sp2 : _Sp4 : _Sp6 : _Sp8 : _Sp10 ,

_{Sn1 : Sn3 = Sn2} : _Sn4

The current proportional coefficients of I ₀ and I ₂ are determined by specific circuit design requirements. _{The Is} scale factor satisfies:

_Sp7 : _Sp9 = _Sp8 : _Sp10 =1

_{Sn1 : Sn3 = Sn2} : _Sn4 =1

This ensures that the I _s of the NMOS and PMOS outputs are equal, while the current Is generated by the PMOS from the power supply into the R _s , and the current _{Is generated by the NMOS from the R s to} the ground is _proportional to a set of aspect ratio parameters. It is composed of small-sized transistors of 1, and has the characteristics of extremely low current consumption.

Several transistors _Mx are connected in series between the drain of the transistor _M5 and the source of _M6 , and the gates of the transistors _M5 , _M6 and _Mx are all connected to each other. By adjusting the size of the Mx transistor string, Vg2 can also be raised to I _s R _s .

Taking a transistor threshold voltage V _th =0.5V as an example, I ₀ and I ₂ in the bias circuit are generally about 50uA-100uA. To increase the V _ds voltage of the transistor M ₁ in the figure from less than 0.7V in the conventional circuit to 2V, Is can be designed to be 5uA. Taking the polysilicon resistor that comes with the process and designing the value of R _s to 260kΩ, it can effectively increase about 1.3V, and at the same time, it can ensure that V _A =V _C .

While increasing V _ds by 1.3V, without changing the current of I ₂ in Figure 2, a number of transistors M _x are connected in series between the source of M ₆ and the drain of M _5. By adjusting the size of the Mx transistor string, it is possible to achieve The Vg2 is also raised by about 1.3V to make the main circuit adapt to the DC operating point of the main transistor and its Cascode tube in the bias circuit.

This embodiment can effectively increase the drain voltage _of the M1 transistor in the main circuit on the premise that the current sources of the main circuit and the bias circuit are well matched, thereby increasing the V _ds voltage margin range _of the M1 transistor. In terms of power consumption, only a very weak current I _s is added, and the resistance value of the voltage boosting resistor R _s can also be integrated on-chip through the process itself, so it has a good application prospect.

In the above description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the above descriptions are only preferred embodiments of the present invention, and the present invention can be implemented in many other ways than those described herein, so the present invention is not limited by the specific implementations disclosed above. At the same time, any person skilled in the art can make many possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the scope of the technical solutions of the present invention, or modify them into equivalent implementations of equivalent changes. example. Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention still fall within the protection scope of the technical solutions of the present invention.

Claims (6)

1. a matching circuit biasing method of a large voltage margin range is characterized in that: comprising a main circuit and a bias generating circuit, the main circuit comprises transistors M ₁ and M ₂ , and the power supply V _dd sequentially passes through resistor R, transistor M ₂ and M1 is grounded; the bias generating circuit includes transistors M3 _{- M6} , the power supply _Vdd is grounded through the current mirror _I0 , transistors _M4 and M3 in turn, and the power supply _Vdd is connected to the ground through the current mirror _I2 , transistors _M6 and _M in _{turn 5} is grounded, the gate bias voltage _{Vg1 of} transistor M1 is determined by connecting the gate _of transistor M3 to the drain of M4, and the gate bias voltage _Vg2 of transistor _M2 is determined by transistors _M5 and _M4 in the bias circuit. _M6 is determined after being connected in series; a voltage margin boosting circuit is provided in the bias circuit, and the voltage margin boosting circuit includes a resistor _Rs and a current source Is, between the _drain of the transistor M4 and the gate _of the transistor M3 The resistors R _s are connected in series, the current sources Is are connected in series in the upper and lower directions of the resistors R _s , and the transistors M _x are inserted between the transistors M ₅ and M ₆ to _increase the V _g2 to I _s R _s . 2. The method for biasing a matching circuit with a large voltage margin range according to claim 1, wherein the currents I ₀ , I ₂ and Is are generated by a current generating circuit, and the current generating circuit comprises PMOS transistors M _{p1 ˜M p10} , NMOS transistors Mn1 to _Mn4 , input reference current I _in , resistor R _p and resistor R _n ; the power supply V _{dd is} connected to the sources of the PMOS transistors M _p1 , M _p3 , M _p5 , M _p7 , and M _p9 respectively, and the PMOS The transistors M _p1 and M _p2 are connected in series, the PMOS transistors M _p3 and M _p4 are connected in series, the PMOS transistors M _p5 and M _p6 are connected in series, the PMOS transistors M _p7 and M _p8 are connected in series, the PMOS transistors M _p9 and M _p10 are connected in series, and the drain of the PMOS transistor M _p1 is connected in series. The electrodes are grounded sequentially through the PMOS transistor _Mp2 , the resistor _Rp and the input reference current _Iin . The gates of the PMOS transistors _{Mp1, Mp3, Mp5, Mp7, and Mp9 are connected to each} other and to one end of the resistor _Rp . The _gates of the transistors M _p2 , M _p4 , M _p6 , _{M p8} , and _{M p10} are connected to each other and to the other end of the _resistor R _p ; Grounding, the drain of the PMOS transistor _Mp10 is connected to the drain of the NMOS transistor _Mn2 through the resistor _Rn , one end of the resistor _Rn close to the PMOS transistor _Mp10 is connected to the gates of the NMOS transistors Mn2 and Mn4 respectively, and the other end of the _Rn is connected to the gate of the NMOS transistor _Mn2 and _Mn4 . One end is connected to the gates of NMOS transistors _Mn1 and _Mn3 respectively; the drain of the PMOS transistor _Mp4 outputs the current I ₂ , the drain of the PMOS transistor _Mp6 outputs the current I ₀ , and the drain of the PMOS transistor _Mp8 outputs the current I _s And flows into the resistor R _s from the power supply terminal, the drain of the NMOS transistor _Mn4 outputs the current _{Is and flows out from the resistor R s to} the ground. 3. The matching circuit biasing method of the large voltage margin range according to claim 2, wherein the width-length ratio of the PMOS tube and the NMOS tube in the current generating circuit satisfies _Sp1 : _Sp3 : _Sp5 : _Sp7 : _Sp9 = _Sp2 : _Sp4 : _Sp6 : _Sp8 : _Sp10 , _{Sn1 : Sn3 = Sn2} : _Sn4 Wherein, S _{p1 ˜S p10} are the width-to-length ratios of the PMOS transistors M _{p1 ˜M p10} , respectively, and Sn1 _{˜S n4} are the width-to-length ratios of the NMOS transistors Mn1 ˜M n4 , respectively. 4. The matching circuit biasing method of the large voltage margin range according to claim 3, wherein the width-length ratio of the PMOS tube and the NMOS tube in the current generating circuit satisfies _Sp7 : _Sp9 = _Sp8 : _Sp10 =1 _{Sn1 : Sn3 = Sn2} : _Sn4 =1. 5. The method for biasing a matching circuit with a large voltage margin range according to claim _{1, wherein a plurality of transistors Mx are connected in series between the drain electrode of the transistor M5 and the source electrode of the transistor M6 , and} the transistor M The gates of ₅ , _M6 and _Mx are all connected to each other. 6 . The matching circuit biasing method with a large voltage margin range according to claim 1 , wherein the resistor R _s is a polysilicon resistor, and the resistance value is integrated on-chip through the process itself. 7 .

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