CN112886931A - Digital weighted current source circuit for eliminating offset error of operational amplifier - Google Patents
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Abstract
The invention discloses a digital weighted current source circuit for eliminating offset error of an operational amplifier in the field of integrated circuit design, which comprises a pair of input geminate transistors and a pair of mirror current source loads, wherein a positive input signal and a negative input signal are respectively connected with the input end of one input tube in the input geminate transistors, two input tubes are respectively connected with one load tube in the mirror current source loads, each load tube is connected with a plurality of trimming branches in parallel, each trimming branch is provided with a trimming tube and a trimming switch which are connected in series, and the on-off of the trimming branch is realized through the turn-off of the trimming switch. The invention can carry out trimming aiming at a single specific key amplifier, can reduce the random matching error inevitably produced in the production process of the amplifier in the integrated circuit, can carry out different combinations of trimming precision and trimming range in different products, realizes the configuration of the trimming precision and the trimming range in any proportion, and has wide applicability.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a digital weighted current source circuit for eliminating offset error of an operational amplifier.
Background
In an integrated circuit design, the output Vout of a voltage amplifier is a [ (Vin +) (Vin-) ], where a is the open-loop gain of the voltage amplifier, and Vin + and Vin-are the positive input signal and the negative input signal of the amplifier, respectively, and are typically voltage signals. The gain value of the open-loop gain A of the amplifier is generally greater than 40db, and in the case of considering common consumer electronics, particularly lithium battery power, the supply voltage of the amplifier is less than or equal to 5V, and once the difference between Vin + and Vin-is greater than 50mV, Vout will reach the positive or negative rail of the power supply, i.e., the Vdd voltage or GND ground.
As shown in fig. 1, in a simplified version of the operational amplifier, T1 and T2 are input pair transistors, T3 and T4 are mirror current source loads, Tb is a reference current source, Ts is a tail current source, Vi + and Vi-are input signals, and Vout is an output signal. In this circuit configuration, the low frequency accuracy of the transfer functions of the input signals Vi + and Vi-to the output signal Vout (the transfer functions are mathematical models representing a method of operation of differential equations of the output variables and the input variables) is determined by the process matching of the devices T1, T2, T3, and T4, which is random for each chip and each wafer.
In the differential amplification circuit, one important characteristic of the differential amplifier is the minimum direct current differential mode voltage which can be detected, and the traditional differential amplification circuit has a limited detection range, can only detect data in a respective numerical range and is limited in application; in addition, the mismatch effect of the amplifier can generate direct-current differential mode voltage which is difficult to distinguish at the output end, and the mismatch effect can convert common-mode input voltage into differential-mode input voltage, so that the performance is greatly influenced.
The above-mentioned drawbacks are worth solving.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a digital weighted current source circuit for eliminating offset errors of an operational amplifier.
The technical scheme of the invention is as follows:
a digital weighted current source circuit for eliminating offset errors of an operational amplifier comprises a pair of input geminate transistors and a pair of mirror current source loads, wherein a positive input signal and a negative input signal are respectively connected with an input end of one input tube of the input geminate transistors, and two input tubes are respectively connected with one load tube of the mirror current source loads.
The invention according to the above scheme is characterized in that a positive input signal is connected with a gate of a first input tube, a source of the first input tube is connected with a source of a second input tube, a drain of the first input tube is connected with a drain of a load tube, a gate of the first load tube, a gate of the second load tube, gates of the trimming tubes and one end of a trimming switch connected in parallel with the first load tube, and the other end of the trimming switch connected in parallel with the first load tube is connected with a drain of a trimming tube of a corresponding branch;
the negative input signal is connected with the grid electrode of a second input tube, the drain electrode of the second input tube is connected with a second load tube and one end of a trimming switch connected with the second load tube in parallel, and the other end of the trimming switch connected with the second load tube in parallel is connected with the drain electrode of the trimming tube of the corresponding branch;
and the source electrode of each trimming tube is connected with a power supply.
Furthermore, the source electrode of the first input tube and the source electrode of the second input tube are both connected with the drain electrode of the tail current source, the grid electrode of the tail current source is connected with the grid electrode of the reference voltage source and the drain electrode of the reference voltage source, and the source electrode of the reference voltage source and the drain electrode of the tail current source are both grounded.
The invention according to the above scheme is characterized in that the trimming tube is an MOS tube of the same type as the load tube.
The invention according to the above scheme is characterized in that the trimming switch is a fuse switch.
The invention according to the above scheme is characterized in that the weighted values of a plurality of trimming pipes in a plurality of trimming branches connected in parallel with the same load pipe are sequentially decreased.
Furthermore, in a plurality of trimming branches connected in parallel with the same load tube, the closer the trimming branch is to the load tube, the larger the weighting value is.
Furthermore, in a plurality of trimming branches connected in parallel with the same load tube, the weighted values of a plurality of trimming tubes are sequentially decreased by multiples.
Further, the weighted value of the trimming pipe is proportional to the width-to-length ratio of the trimming pipe.
The present invention according to the above aspect is characterized in that the trimming pipe connected in parallel with one of the load pipes and the trimming pipe connected in parallel with the other load pipe are in mirror image relationship with each other.
The invention according to the scheme has the advantages that the invention can be used for trimming a single specific key amplifier, can reduce the random matching error inevitably generated in the production process of the amplifier in an integrated circuit, can be applied to a single operational amplifier, and can be integrated in wider fields such as a lithium battery protection chip, a power supply management chip and the like. In addition, the invention can carry out different combinations of the trimming precision and the trimming range in different products, realizes the configuration of the trimming precision and the trimming range in any proportion, and has wide applicability.
Drawings
FIG. 1 is a schematic diagram of an operational amplifier;
FIG. 2 is a schematic structural view of the present invention;
FIG. 3 is a block diagram of one embodiment of the present invention;
FIG. 4 is a schematic diagram of an open state of a trimming switch according to an embodiment of the present invention;
fig. 5 is a layout diagram according to another embodiment of the present invention.
Detailed Description
The invention is further described with reference to the following figures and embodiments:
as shown in fig. 2, a digital weighted current source circuit for eliminating offset error of an operational amplifier includes a pair of input pair transistors and a pair of mirror current source loads, wherein a positive input signal and a negative input signal are respectively connected to an input terminal of one input transistor of the input pair transistors, and two input transistors are respectively connected to one load transistor of the mirror current source loads.
Since an important aspect of the performance of the differential amplifier is the minimum direct current differential mode voltage that can be detected, mismatch effects of the amplifier can generate a direct current differential mode voltage at the output terminal that is difficult to distinguish, and the mismatch effects can convert a common mode input voltage into a differential mode input voltage, which greatly affects the performance. Therefore, in order to solve the above problems, each load tube is connected in parallel with a plurality of trimming branches, each trimming branch is provided with a trimming tube and a trimming switch which are connected in series, and the on-off of the trimming branch is realized by turning off the trimming switch, so that the trimming of the load tube is realized.
Preferably, each trimming tube is an MOS tube of the same type as the load tube connected in parallel, each trimming switch is a fusing switch, and the on-off of different trimming branches can be realized more easily through the fusing switch.
The invention can carry out different combinations of the trimming precision and the trimming range in different products, fully realizes the design intention, can realize the configuration of the trimming precision and the trimming range in any proportion, has wide applicability, can be applied to independent operational amplifiers, and can be integrated into wider fields such as lithium battery protection chips, power management chips and the like.
In a differential operational amplifier:
the positive input signal Vi + is connected with the grid of the first input tube T1, the source of the first input tube T1 is connected with the source of the second input tube T2, the drain of the first input tube T1 is connected with the drain of the load tube (comprising the first load tube T3 and the second load tube T4), the grid of the first load tube T3, the grid of the second load tube T4, the grids of the trimming tubes (Ta1, Ta2 … … Tan; Tb1, Tb2 … … Tbn) and one end of the trimming switches (FA1, FA2 … … FAn) which are connected with the first load tube T3 in parallel, and the other end of the trimming switches (FA1, FA2 … … FAn) which are connected with the first load tube T3 in parallel is connected with the drains of the trimming tubes (FA1, Ta2 … … Tan) of the corresponding branch;
the negative input signal Vi-is connected with the grid electrode of the second input tube T2, the drain electrode of the second input tube T2 is connected with one ends of the second load tube T4 and the trimming switches (FB1 and FB2 … … FBn) which are connected with the second load tube T4 in parallel, and the other ends of the trimming switches (FB1 and FB2 … … FBn) which are connected with the second load tube T4 in parallel are connected with the drain electrodes of the trimming tubes (Tb1 and Tb2 … … Tbn) of the corresponding branch;
the sources of the trimming tubes (Ta1, Ta2 … … Tan; Tb1, Tb2 … … Tbn) are connected with a power supply Vdd;
the source electrode of the first input tube T1 and the source electrode of the second input tube T2 are both connected with the drain electrode of the tail current source Ts, the grid electrode of the tail current source Ts is connected with the grid electrode of the reference voltage source Tb and the drain electrode of the reference voltage source Tb, and the source electrode of the reference voltage source Tb and the drain electrode of the tail current source Ts are both grounded GND.
As shown in fig. 3, in one embodiment, each load tube is set in parallel with one trimming branch, that is:
the positive input signal Vi + is connected to the gate of the first input tube T1, the source of the first input tube T1 is connected to the source of the second input tube T2, the drain thereof is connected to the drains of the first load tube T3 and the second load tube T4, the gate of the first load tube T3, the gate of the second load tube T4, the gate of the first trimming tube T5, the gate of the second trimming tube T6, and one end of the first trimming switch F1 connected in parallel to the first load tube T3, and the other end of the first trimming switch F1 is connected to the drain of the first trimming tube T5; the negative input signal Vi-is connected with the grid of a second input tube T2, the drain of the second input tube T2 is connected with a second load tube T4 and one end of a second trimming switch F2 which is connected with the second load tube T4 in parallel, the other end of the second trimming switch F2 is connected with the drain of a second trimming tube T6, and the source of the first trimming tube T5 and the source of the second trimming tube T6 are both connected with a power supply Vdd;
the source electrode of the first input tube T1 and the source electrode of the second input tube T2 are both connected with the drain electrode of the tail current source Ts, the grid electrode of the tail current source Ts is connected with the grid electrode of the reference voltage source Tb and the drain electrode of the reference voltage source Tb, and the source electrode of the reference voltage source Tb and the drain electrode of the tail current source Ts are both grounded GND.
In this differential amplifier, the first input transistor T1 and the second input transistor T2 are NMOS input pair transistors, the first load transistor T3 and the second load transistor T4 are PMOS mirror current source loads, and Vout is an output signal. If the first input tube T1 and the second input tube T2 are replaced by PMOS input pair tubes, the corresponding tail current source Ts is replaced by PMOS tubes, and the load current mirror is replaced by NMOS tubes. Subsequently, an NMOS input amplifier is taken as an example for explanation. In order to eliminate process errors of the first input tube T1, the second input tube T2, the first load tube T3 and the second load tube T4, the first trimming tube T5 and the second trimming tube T6 are respectively used as dummy tubes of current mirrors of the first load tube T3 and the second load tube T4, and the first trimming switch F1 and the second trimming switch F2 are respectively used as trimmed Fuse.
When the introduction of the first trimming tube T5 and the second trimming tube T6 is not considered, the equivalent input offset errors Vos at the Vi + and Vi-ends caused by the process errors of the first input tube T1, the second input tube T2, the first load tube T3 and the second load tube T4 are calculated as follows:
1. and calculating the threshold voltage error of the first input tube T1 and the second input tube T2, namely Vos1 is Vt1-Vt 2.
2. The voltage error generated by the currents of the first input tube T1 and the second input tube T2 is:
wherein λ isNIs inverse number of Herley voltage of NMOS tube, VDSNThe source-drain voltages of the first input tube T1 and the second input tube T2,
toxfor a given thickness of the oxide layer between the gate and the inversion layer in the process,. epsilonoxIs dielectric constant, munIs the electron mobility in the channel.
Under small mismatch conditions, the above equation can be simplified to:
wherein, VovNIs the overdrive voltage, Δ I, of the NMOS transistorNIs the difference between the currents flowing through the first input tube T1 and the second input tube T2; i isNIs the average value of the current flowing through the first input tube T1 and the second input tube T2;
is the difference of the width-length ratio of the first input pipe T1 and the second input pipe T2,
is the average value of the width-to-length ratios of the first input pipe T1 and the second input pipe T2.
To obtain finally
3. Calculating the error generated by the mismatch of the first load tube T3 and the second load tube T4
Since the current flowing through the first input tube T1 and the first load tube T3 are the same and the current flowing through the second input tube T2 and the second load tube T4 are the same, the current flowing through the first input tube T1 and the second load tube T4 are the same
KVL analysis is carried out on a grid source loop of the load to obtain
Wherein λ isPIs inverse number of Herley voltage of PMOS tube, VDSPIs the source-drain voltage of the first load tube T3 and the second load tube T4.
In consideration of small mismatch conditions, obtaining
Wherein, Delta IPTo flow through the first load tube T3 and the secondThe difference between the currents of the two load tubes T4; i isPIs the average value of the current flowing through the first load tube T3 and the second load tube T4;
which is a difference between the width-to-length ratios of the first and second load tubes T3 and T4,
is an average value of the width-to-length ratios of the first and second load tubes T3 and T4.
To obtain finally
4. Combine the three points to
Substituted into Vos2 formula expression, and assuming VovN≈VovPObtaining:
in the above formula, Vt1, Vt2, Vt3 and Vt4 in the brackets in the first middle are inherent errors in the process manufacturing process and are difficult to improve; the second middle bracket is the error caused by the mismatching of the MOS tube grid source working voltage, therefore, the invention changes the width-length ratio of the load current source (namely the first load tube T3 and the second load tube T4) to totally pair VOSAnd (6) adjusting.
In one embodiment, the width to length ratios of the first load tube T3, the second load tube T4, the first trim tube T5, and the second trim tube T6 before trimming are 40um/10um, 4um/10um, and 4um/10um, respectively. During the specific trimming process, the second trimming switch F2 is turned on, and the first trimming tube F1 is turned off, as shown in fig. 4.
Calculating the adjustment value delta V before and after trimmingOS：
Therefore, only one pair of adjustable PMOS current source load tubes is added, and basic realization can be realized
One tenth of the equivalent input tube offset voltage adjustment value.
When further determining the magnitude of the absolute voltage value, calculations are required
The size of (2).
By the formula
In a clear view of the above, it is known that,
the parameter k' given by 0.18um process of a certain foundry is 2500uA/V2Calculating and taking values
IN＝0.5uA，
Based on this, the trimming control of the first trimming switch F1 is performed according to the proportion shown in fig. 4, and the input voltage equivalent offset voltage of about 1mV can be adjusted at a time, and the trimming precision completely meets the requirement of the non-analog-to-digital converter of the consumer electronics.
From the above calculations, it is possible to achieve a misalignment error lower than 1mV by modifying the size of the first and second trim tubes T5 and T6 relative to the first and second load tubes T3 and T4.
As shown in fig. 1 and 5, in order to realize different combinations of trimming accuracy and trimming range and realize different design intentions, the invention realizes the preparation of the trimming accuracy and the trimming range in any proportion by controlling the design of different trimming branch weighted values. Specifically, in a plurality of trimming branches connected in parallel with the same load tube, the weighted values of the plurality of trimming tubes are sequentially decreased.
In the invention, the weighted value of a plurality of trimming branches which are connected with the same load tube in parallel is smaller as the distance between the trimming branches and the load tube is closer. In one embodiment, in a plurality of trimming branches connected with the same load tube in parallel, the weighted values of a plurality of trimming tubes are sequentially decreased by times; in other embodiments, the weighting values of the trimming pipes are decreased in a non-multiple relationship, and the decreasing form of the weighting values can be selected by the designer according to specific situations.
Specifically, in a preferred embodiment, the weighting values of the trimming pipes are decreased in proportion to the power exponent. That is, when the weighting value of the first modulation tube is set to z, the weighting value of the second modulation tube is set to 2z, the weighting value of the third modulation tube is set to 4z, and the weighting value of the nth modulation tube is set to 2 in … …n-1z. The weighting value may be an integer or a non-integer.
For example, in the present invention, the trimming MOS transistors corresponding to the first load transistor T3 are Ta1 and Ta2 … … Tan, respectively, and n MOS transistors having the same channel length as that of the first load transistor T3 are provided, and Ta1 and Ta2 … … Tan are connected in parallel to the first load transistor T3 through n fuse switches of FA1 and FA2 … … FAn, respectively; similarly, the trimming MOS transistors corresponding to the second load transistor T4 are Tb1 and Tb2 … … Tbn, respectively, and n MOS transistors having the same channel length as the second load transistor T4 are provided, and Tb1 and Tb2 … … Tbn are connected in parallel to the second load transistor T4 through n fuse switches FB1 and FB2 … … FBn, respectively. In the present invention, the Ta series of trimming transistors connected in parallel to the first load transistor T3 and the Tb series of trimming transistors connected in parallel to the second load transistor T4 are mirror images of each other, and the Ta series MOS transistor and the Tb series MOS transistor respectively correspond to the case where the offset error is a positive value and a negative value.
In this embodiment, the trimming pipe Ta1 is the minimum trimming unit of the trimming value, and the width-to-length ratio is
At this time, the weight value and the precision requirement of the trimming tube Ta1 are the highest, and the width-length ratio of the trimming tube Ta2 is twice that of the trimming tube Ta1, namely
The weight value is next to the trimming pipe Ta 1; the width-length ratio of the trimming pipe Ta3 is
By analogy, the width-to-length ratio of Tan is
The MOS tube of the trimming tube Tb series is completely the same as the MOS tube of the trimming tube Ta series, and the magnitude values are arranged in a same way according to the weighted value.
As can be seen from the above example, the weighted value of the trimming pipe is proportional to the width-to-length ratio of the trimming pipe, so that different trimming results can be obtained by adjusting the width-to-length ratio of the trimming pipe in the trimming branch connected in parallel with the load pipe.
In the specific example shown in fig. 5, each load tube is connected in parallel with 3 trimming branches, i.e. n is 3. At this time, dummy tubes (dummy devices) are added to the left side of the trimming tube Ta3 and the right side of the trimming tube Tb3, respectively, to ensure the environmental consistency of the trimming tube Ta3 and the trimming tube Tb3, and the line connection of the substrate bias portion is omitted in fig. 5.
In this embodiment, the weight of the trimming tube Ta1 and the trimming tube Tb1 is the largest, so the trimming tube Ta1 is placed at the left side of the first load tube T3 and the trimming tube Tb1 is placed at the right side of the second load tube T4, so that the requirement of central symmetry is fully met, and the trimming tube Ta2, the trimming tube Ta3, the trimming tube Tb2 and the trimming tube Tb3 are sequentially placed at a distance.
FA 1-FA 3 and FB 1-FB 3 are fuses for trimming corresponding to the weighted current mirror, respectively, wherein a fusing switch FA1 corresponds to a trimming tube Ta1, a fusing switch FA2 corresponds to a trimming tube Ta2, a fusing switch FA3 corresponds to a trimming tube Ta3, a fusing switch FB1 corresponds to a trimming tube Tb1, a fusing switch FB2 corresponds to a trimming tube Tb2, and a fusing switch FB3 corresponds to a trimming tube Tb 3. In this embodiment, the pattern of the metal fuse is selected and can be modified by laser. In other embodiments, other metal fuses for current, polysilicon fuses for current, or MOS switches controlled by digital circuits may be used.
Through the calculation mode, if the weight of the trimming tube Ta1 is 1mV, the weight of Ta2 is 2mV, and the weight of Ta3 is 4mV, at the moment, the offset error adjusting range with the accuracy of 1mV of +/-7 mV can be realized through the adjustment of the fusing switch. Assuming that the weight of the trimming pipe Ta1 is 2mV, the weight of Ta2 is 4mV, and the weight of Ta3 is 5mV, at this time, the trimming error adjusting range of ± 14mV and the precision of 2mV can be realized through the adjustment of the fuse switch.
Therefore, the invention can be used for trimming a single specific key amplifier, and can reduce the random matching error inevitably generated in the production process of the amplifier in the integrated circuit. In actual production life, for MOS tube technology, the inherent random offset voltage of an unmodified operational amplifier is usually as high as 10mV to 50mV, but the invention can adjust the modification precision to 1mV or below, and has great influence on the accuracy of a system.
It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.
The invention is described above with reference to the accompanying drawings, which are illustrative, and it is obvious that the implementation of the invention is not limited in the above manner, and it is within the scope of the invention to adopt various modifications of the inventive method concept and technical solution, or to apply the inventive concept and technical solution to other fields without modification.
Claims (10)
1. A digital weighted current source circuit for eliminating offset errors of an operational amplifier comprises a pair of input geminate transistors and a pair of mirror current source loads, wherein a positive input signal and a negative input signal are respectively connected with an input end of one input tube of the input geminate transistors, and two input tubes are respectively connected with one load tube of the mirror current source loads.
2. The digital weighted current source circuit for eliminating the offset error of the operational amplifier as claimed in claim 1, wherein the positive input signal is connected to the gate of the first input tube, the source of the first input tube is connected to the source of the second input tube, the drain of the first input tube is connected to the drain of the load tube, the gate of the first load tube, the gate of the second load tube, the gate of each trimming tube and one end of the trimming switch connected in parallel to the first load tube, and the other end of the trimming switch connected in parallel to the first load tube is connected to the drain of the trimming tube of the corresponding branch;
the negative input signal is connected with the grid electrode of a second input tube, the drain electrode of the second input tube is connected with a second load tube and one end of a trimming switch connected with the second load tube in parallel, and the other end of the trimming switch connected with the second load tube in parallel is connected with the drain electrode of the trimming tube of the corresponding branch;
and the source electrode of each trimming tube is connected with a power supply.
3. The digital weighted current source circuit for eliminating operational amplifier offset error of claim 2, wherein the source of the first input tube and the source of the second input tube are connected to the drain of a tail current source, the gate of the tail current source is connected to the gate of a reference voltage source and the drain of the reference voltage source, and the source of the reference voltage source and the drain of the tail current source are both grounded.
4. The digital weighted current source circuit for eliminating operational amplifier offset error as claimed in claim 1, wherein the trimming transistor is a MOS transistor of the same type as the load transistor.
5. The digitally weighted current source circuit of claim 1, wherein the trimming switch is a fuse switch.
6. The digital weighted current source circuit of claim 1, wherein the weighting values of the trimming transistors in the trimming branches connected in parallel with the same load transistor are sequentially decreased.
7. The digital weighted current source circuit for eliminating operational amplifier offset error of claim 6, wherein the weighted value of the plurality of trimming branches connected in parallel with the same load tube is larger the closer the trimming branch is to the load tube.
8. The digital weighted current source circuit of claim 6, wherein the weighting values of the plurality of trimming transistors in the plurality of trimming branches connected in parallel with the same load transistor are sequentially decreased by multiples.
9. The digitally weighted current source circuit of claim 6, wherein the weight of the trimming transistor is proportional to the aspect ratio of the trimming transistor.
10. The digitally weighted current source circuit according to claim 1, wherein the trimming transistor connected in parallel with one of the load transistors and the trimming transistor connected in parallel with the other load transistor are mirror images of each other.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113671258A (en) * | 2021-08-19 | 2021-11-19 | 苏州瀚瑞微电子有限公司 | Touch screen channel short-circuit resistance measuring circuit and method |
| CN115173817A (en) * | 2022-09-05 | 2022-10-11 | 深圳市单源半导体有限公司 | Differential amplification circuit, error amplification circuit and trimming method thereof |
| CN115454199A (en) * | 2022-09-20 | 2022-12-09 | 圣邦微电子（北京）股份有限公司 | Current selection circuit |
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