CN112910447A - Low-power-consumption comparator circuit with rail-to-rail input swing amplitude - Google Patents
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Abstract
The invention relates to an electronic circuit, in particular to a low-power-consumption comparator circuit with rail-to-rail input swing amplitude. The invention adopts the idea of using complementary input pairs to trade the rail-to-rail swing by modifying the structure of the preamplifier, adopts a pair of complementary clock signals CLK and CLKN, realizes the aim of covering a low input range by using a mode of combining a PMOS dynamic preamplifier controlled by a clock and an NMOS current mirror, adopts a full dynamic circuit, has low power consumption, and is suitable for being applied to a single-ended ADC or an ADC structure with great common-mode input level change. The invention realizes higher comparison speed and precision under the condition of very low amplitude of the input signal, and utilizes the power supply voltage swing to the maximum extent.
Description
Technical Field
The invention relates to an electronic circuit, in particular to a low-power-consumption comparator circuit with rail-to-rail input swing amplitude.
Background
The analog-to-digital converter is a bridge connecting the analog and digital domains. The comparator is used as a core module of the analog-to-digital converter, and compares the input analog voltage with the reference voltage so as to obtain digital output corresponding to the input analog voltage. The fully differential analog-to-digital converter is favored by designers because it can reduce the influence of even harmonics by differential input to improve the conversion accuracy and linearity, but it needs two DAC arrays and has large area and power consumption overhead. The single-ended input analog-to-digital converter only needs one DAC array, the power consumption and the area are smaller than those of a fully differential structure, the input swing amplitude of the single-ended input analog-to-digital converter is only half of that of the fully differential structure, and the speed of a comparator is seriously influenced by an input signal under the condition that the input signal is close to a power supply voltage or a ground potential. In order to ensure the speed of the comparator, the conventional method is to control the input swing within the range where the comparator can work at the required speed, but this further limits the input swing under the condition that the power supply voltage is continuously reduced, thereby severely limiting the precision of the analog-to-digital converter. In order to guarantee the accuracy and speed of the analog-to-digital converter as much as possible, the comparator needs to be made to have rail-to-rail swing as much as possible. This is especially true in low power applications.
Fig. 1 is a conventional two-stage dynamic comparator for comparing the magnitude of input voltage and outputting the result, and the operation principle is as follows: VIN and VIP are input voltages. M1～M5Constituting a dynamic preamplifier, M6～M11Constituting a Latch (Latch). The preamplifier is controlled by a pair of complementary clocks CLK and CLKN, so that a normally open path from a power supply VDD to a ground potential GND is avoided, and power consumption is reduced. The latch uses a conventional PMOS latch structure. When the comparator enters a reset state, CLK is at GND and CLKN is at VDD, M5Cutoff, M3And M4On, charge VON and VOP nodes to VDD. At the same time, M10And M11Conducting to output the powerThe VOUT and VOUTB potentials bleed to GND, so M8And M9And also cut off. When the comparator is at the comparison stage, CLK is at VDD and CLKN is at GND. Thus, M3And M4Off, M5On, the path from VON and VOP to GND is provided, so VON and VOP fall from VDD. Suppose VIP>VIN and the circuit is completely symmetrical, M1Leakage current of greater than M2VON falls faster than VOP, so VON and VOP reach GND at any time before VON and VOP reach GND<VOP. Thus, M6Leakage current ratio M of7The leakage current of (2) is large. At the same time due to M10And M9On, VOUT rises to reach M faster than VOUTB9Threshold voltage V ofTH9Result in M9And conducting. M7And M9At this point, the path from VDD to GND is provided in common, VOUTB therefore begins to fall and does not reach VTH8Thus M is8The off state is maintained, so VOUT continues to rise to VDD, while VOUTB is pulled down to GND, thereby producing comparison results VOUT-VDD and VOUTB-GND, representing VIP>VIN. On the contrary, if VIP<VIN, VOUT is GND, VOUTB is VDD, and VIP is shown<VIN。
The comparator has low power consumption and high speed, but has the problem of small input swing. Because the input voltages VIN and VIP are at least greater than M1And M2Otherwise, input to the pair transistor M1And M2The current of (a) is very small, which severely limits the speed of the comparator, thereby severely limiting the application of such a comparator in a single-ended input ADC or an ADC structure using a monotonic switching scheme.
Disclosure of Invention
Aiming at the problems or the defects, the problem that the precision and the speed of an ADC are reduced due to the fact that a single-ended ADC is limited in input swing caused by the fact that a traditional two-stage dynamic comparator allows the input swing to be small is solved; the invention provides a low-power-consumption comparator circuit with rail-to-rail input swing amplitude. The invention changes the structure of the preamplifier to increase the cost of an input amplifier to exchange the rail-to-rail swing, realizes the aim of covering a low input range by using a mode of combining a PMOS dynamic preamplifier controlled by a clock and an NMOS current mirror, adopts a full dynamic circuit, has low power consumption, and is suitable for being applied to an ADC with single-end input or an ADC structure with large common-mode input level variation.
The specific technical scheme is as follows:
a low power consumption comparator circuit with rail-to-rail input swing comprises an NMOS dynamic preamplifier, a PMOS dynamic preamplifier, an NMOS current mirror and a PMOS latch.
The input end of the PMOS dynamic preamplifier is connected with an input signal, and the output end of the PMOS dynamic preamplifier is connected with an NMOS current mirror; the input end of the NMOS dynamic preamplifier is connected with an input signal, and the output end of the NMOS dynamic preamplifier is connected with the PMOS latch; the input end of the NMOS current mirror is connected with the output end of the PMOS dynamic prevention amplifier, and the output end of the NMOS current mirror is connected with the input end of the PMOS latch; the input end of the PMOS latch is connected with the output ends of the NMOS dynamic preamplifier and the NMOS current mirror, and the output end of the PMOS latch is the output of the comparator.
The control signals used are a pair of complementary clock signals CLK and CLKN, all controlled by the CLK/CLKN clock signal. When the CLK is at the high level VDD and the CLKN is at the low level GND, the whole comparator circuit is in a comparison state, and analog signals of the input ends VOP and VON are compared; on the other hand, if CLK is at a low level and CLKN is at a high level, the comparator circuit is in a reset state, and the comparison between the input terminals VOP and VON is not performed.
The control signals CLK and CLKN are specifically:
when the CLK is at a high level (VDD), and the CLKN is at a low level (GND), the whole comparator circuit is in a comparison state, and the analog signals of the input terminals VIP and VIN are compared; at this time, the high level of the CLK clock signal and the low level of the CLKN clock signal control the related MOS tube, so that the output of the NMOS dynamic preamplifier is connected to GND, the output end of the PMOS preamplifier and the output end of the PMOS latch are connected to VDD, and the output end of the NMOS current mirror is connected to GND to form a current path. The input differential signal thus produces a differential comparison result at the comparator output.
Conversely, if CLK is at a low level and CLKN is at a high level, the comparator circuit is in a reset state and does not compare the input terminals VIP and VIN; at this time, since the CLK and CLKN clock signals make the NMOS dynamic preamplifier and the NMOS current mirror output terminals at the high level VDD, the PMOS dynamic preamplifier output terminals at the low level GND, and the PMOS latch output nodes are connected to GND, the comparator does not output the differential comparison result, but outputs two 0 s.
Further, the NMOS dynamic preamplifier comprises a first NMOS transistor M1A second NMOS transistor M2And the third NMOS transistor M5And a first PMOS transistor M3Second PMOS transistor M4. First NMOS transistor M1The grid end is connected with an input level VIP, the drain end is connected with the inverted input end VON of the PMOS latch, and the source end is connected with a third NMOS tube M5The drain terminal of (1); second NMOS transistor M2The grid is connected with an input level VIN, the drain is connected with a positive phase input end VOP of the PMOS input latch, and the source is connected with a third NMOS tube M5The drain terminal of (1); third NMOS transistor M5The grid electrode of the NMOS transistor is connected with a clock control signal CLK, and the drain end of the NMOS transistor is connected with a first NMOS transistor M and a second NMOS transistor M1And M2The source end is grounded at the ground potential GND; first PMOS transistor M3The drain terminal of the PMOS latch is connected with the inverted input end VON of the PMOS latch, the source electrode of the PMOS latch is connected with the power supply voltage VDD, and the grid electrode of the PMOS latch is connected with the clock signal CLK; second PMOS transistor M4The drain terminal of the PMOS latch is connected with the positive phase input terminal VOP of the PMOS latch, the source terminal of the PMOS latch is connected with the power supply voltage VDD, and the grid terminal of the PMOS latch is connected with the clock signal CLK.
Further, the PMOS latch structure comprises a third PMOS tube M6And the fourth PMOS transistor M7And a fourth NMOS transistor M8The fifth NMOS transistor M9And a sixth NMOS transistor M10And a seventh NMOS transistor M11. Third PMOS transistor M6The grid end VON is the inverting input end of the PMOS latch, is connected to the NMOS dynamic preamplifier and the inverting output end of the NMOS current mirror, the source end is connected with a power voltage VDD, and the drain end is connected with the positive phase output end VOUT of the comparator; fourth PMOS transistor M7The grid end VOP of the PMOS latch is a positive phase input end of the PMOS latch and is connected with positive phase output ends of the NMOS dynamic preamplifier and the NMOS current mirror, the source end of the PMOS latch is connected with a power supply voltage VDD, and the drain end of the NMOS latch is connected with a positive phase output end VOUTB of the comparator; fourth NMOS transistor M8Gate-terminated comparator invertingThe output end VOUTB, the drain end is connected with the positive phase output end VOUT of the comparator, and the source end is grounded; fifth NMOS transistor M9The grid end is connected with a positive phase output end VOUT of the comparator, the drain end is connected with a negative phase output end VOUTB of the comparator, and the source end is grounded at the ground potential GND; sixth NMOS transistor M10The grid end is connected with a comparator control clock CLKN, the drain end is connected with a positive phase output end VOUT of the comparator, and the source end is grounded; seventh NMOS transistor M11The grid end is connected with the comparator control clock CLKN, the drain end is connected with the inverted output end VOUTB of the comparator, and the source end is grounded at the ground potential GND.
Further, the PMOS dynamic preamplifier comprises a fifth PMOS tube M12Sixth PMOS transistor M13Seventh PMOS transistor M16And an eighth NMOS transistor M14And a ninth NMOS transistor M15. The fifth PMOS tube M12The grid end is connected with an input level VIP, the drain end is connected with an NMOS tube M of the NMOS current mirror17Grid and eighth NMOS transistor M14The source end of the drain electrode is connected with a seventh PMOS tube M16The drain terminal of (1); sixth PMOS transistor M13The grid end is connected with an input level VIN, and the drain end is connected with an NMOS tube M of the NMOS current mirror18Grid and ninth NMOS transistor M15The source end of the drain electrode is connected with a seventh PMOS tube M16The drain terminal of (1); seventh PMOS tube M16The gate terminal of the transistor is connected with a control clock CLKN, and the drain terminal of the transistor is connected with a fifth PMOS tube M and a sixth PMOS tube M12And M13The source end is connected with a power voltage VDD; eighth NMOS transistor M14The grid of the NMOS transistor is connected with a control clock CLKN, the source end is grounded and connected with a ground potential GND, and the drain end is connected with an NMOS tube M of the NMOS current mirror17Gate terminal of and fifth PMOS transistor M12The drain terminal of (1); ninth NMOS transistor M15The grid of the NMOS transistor is connected with a control clock CLKN, the source end is grounded and connected with a ground potential GND, and the drain end is connected with an NMOS tube M of the NMOS current mirror18Gate terminal of and sixth PMOS transistor M13The drain terminal of (1).
Further, the NMOS current mirror comprises a tenth NMOS transistor M17And an eleventh NMOS transistor M18. Tenth NMOS transistor M17The grid end of the fifth PMOS tube M of the PMOS dynamic preamplifier is connected with12The source end is grounded at the ground potential GND, and the drain end is connected with the positive phase input end VOP of the PMOS latch; eleventh NMOS transistor M18The grid end of the sixth PM of the PMOS dynamic preamplifier is connected withOS tube M13The drain terminal of the PMOS latch is connected with the ground potential GND, and the drain terminal is connected with the inverted input end VON of the PMOS latch.
The scheme adopts the idea of using complementary input pairs (PMOS dynamic preamplifier and NMOS dynamic preamplifier), realizes higher comparison speed and precision under the condition of very low input signal amplitude, and utilizes the power supply voltage swing to the maximum extent. The circuit structure is applied to the analog-digital converter with low power supply voltage, and can enable the analog-digital converter with the structure to realize higher precision and higher speed under low power supply voltage compared with the analog-digital converter with the traditional structure dynamic comparator. Meanwhile, different from the traditional comparator, the preamplifier with the structure adopts a full-dynamic structure, obtains higher speed and lower power consumption, and is more suitable for an analog-to-digital converter applied with low power consumption.
The low-power-consumption comparator circuit with rail-to-rail input swing amplitude is a comparator circuit with a dynamic preamplifier, and when the input voltage swing amplitude is rail-to-rail, the influence of noise on the comparison result of the comparator is effectively reduced, and higher comparison speed and higher comparison precision are provided. The invention adopts a full dynamic structure while covering the rail-to-rail swing, thereby effectively reducing the power consumption of the comparator.
Drawings
FIG. 1 is a circuit diagram of a conventional two-stage dynamic comparator;
FIG. 2 is a block diagram of a two-stage dynamic comparator of the present invention;
FIG. 3 is a circuit diagram of an NMOS dynamic prevention amplifier according to an embodiment of the present invention;
FIG. 4 illustrates a PMOS latch structure according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of an NMOS current mirror and a PMOS dynamic prevention amplifier according to an embodiment of the present invention;
fig. 6 shows an overall structure of a two-stage dynamic comparator according to an embodiment of the present invention.
Detailed Description
The technical scheme of the invention is detailed below by combining the accompanying drawings and the embodiment.
As in fig. 2, there is a difference between the input signal and VIN/VIP. The latches of the NMOS dynamic preamplifier, the PMOS dynamic preamplifier and the PMOS input pair are in a reset state when clock signals CLK and CLKN are respectively at a low level and a high level, and the VIN/VIP is not compared by the comparator; the comparator is in an active state when the CLK and CLKN signals are high and low, respectively. At this time, since VIN/VIP has a difference, it generates a voltage difference at the output of the PMOS pre-dynamic amplifier and the NMOS pre-dynamic amplifier. The voltage difference of the output end of the NMOS preventive amplifier is directly detected by the PMOS latch, and the output voltage difference of the PMOS preventive amplifier is converted to be connected to the input end of the latch of the PMOS input pair through the NMOS current mirror. The resulting VIN/VIP voltage difference produces a digital output VOUT/VOUTB at the comparator output.
FIG. 3 is the NMOS dynamic prevention amplifier. Wherein, the first NMOS transistor M1And the third NMOS transistor M5First PMOS transistor M3Forming a first current branch; the first NMOS transistor M2And the third NMOS transistor M5First PMOS transistor M4Forming a second current branch; when CLK is low, VSG3,4Is (VDD-GND) and is greater than | VTH3,4|，M3And M4Conducting; m5Off, cutting off the current path from VON and VOP to GND. Thus, M3And M4VON and VOP are charged to VDD. When CLK is high, M3And M4Off, cutting off the path from VDD to VON and VOP; m5On, a path from VON and VOP to GND is provided. At this time, the voltage between two points VON and VOP drops from VDD. If VIP>VIN, then through M1Will be greater than through M2Thus, VON is less than VOP at the same time; on the contrary, if VIN>VIP, then by M2Will be greater than through M1VON at the same time is larger than VOP. Thus, the difference between the input voltages VIN and VIP is converted to the difference between the input voltages VON and VOP of the PMOS latch. The NMOS dynamic preamplifier can cover the input swing above the common mode level.
FIG. 4 is the PMOS latch. Wherein, a third PMOS transistor M6Fourth NMOS transistor M8Forming a third current branch; a fourth PMOS transistor M7Fifth NMOS transistor M9Forming a fourth current branch; a third PMOS transistor M6Sixth NMOS transistor M10Forming a fifth current branch; a fourth PMOS transistor M7Seventh NMOS transistor M11Constituting a sixth current branch. When CLKN is high, M is charged to VDD because VON and VOP are charged to VDD6、M7Cutoff, M10And M11On, the output nodes VOUT and VOUTB are discharged to GND, so M8And M9And (6) cutting off. When CLKN becomes low, M10、M11Is cut off and M6And M7In the case where VON and VOP are less than (VDD- | V)THP6,7|) is on. If VON<VOP, then M6Leakage current of greater than M7So that VOUT starts to rise faster from GND than VOUTB when VOUT reaches M9Threshold value V ofTHN9When M is in contact with9On, provides a path for VOUTB to GND, so that VOUTB rises slowly and then begins to fall, so that M8The conduction time is short or even non-conductive, so VOUT still remains raised to VDD, and VOUTB is eventually driven by M9Pulled to GND. On the contrary, if VOP<VON, then similarly VOUT is multiplied by M8Pulled to GND, and VOUTB is finally driven by M7Charge to VDD. In combination with the previous analysis, the final VIN>When VIP, the comparator outputs VOUTB at high level and VOUT at low level; conversely, VOUT is high and VOUTB is low. Thereby, comparison of the input signals and output of the digitized comparison results are achieved.
FIG. 5 shows the PMOS dynamic preamplifier and NMOS current mirror structure. Wherein, a fifth PMOS transistor M12Seventh PMOS transistor M16And an eighth NMOS transistor M14Forming a seventh current branch; a sixth PMOS transistor M13Seventh PMOS transistor M16And a ninth NMOS transistor M15Forming an eighth current branch; tenth NMOS transistor M with NMOS current mirror17Forming a ninth current branch; eleventh NMOS transistor M with NMOS current mirror18Constituting a tenth current branch. When CLKN is high, M16Is cut off and M14And M15And conducting.Thus M14And M15Will M17And M18Is drained to GND, so M17、M18Cutting off; m17And M18VOP and VON of the drain terminal are respectively M4And M3Charge to VDD. When CLKN is at low level, M16Is turned on and M14And M15And (6) cutting off. M17And M18Are respectively M12And M13And (6) charging. If VIP>VIN, then M12Leakage current ratio M of13So that, at the same time, M is small18Gate voltage ratio of M17The gate voltage of (2) is high. Thus M18Leakage current ratio M of17I.e. VON falls faster than VOP, thereby producing a voltage difference VON>VOP. Similarly, if VIP<VIN, then M12Leakage current of greater than M13Of the leakage current, thus M18Gate voltage ratio of M17So that its leakage current is also smaller, and therefore VOP falls faster than VON, thereby generating a voltage difference VON<VOP. Thus, the PMOS dynamic preamplifier and the NMOS current mirror shown in fig. 5 can achieve the same amplification function as the NMOS dynamic preamplifier, and cover the input swing at the common mode level one, thereby achieving rail-to-rail of the input signal.
It can be seen from the above embodiments that the low power consumption rail-to-rail input swing comparator circuit provided by the present invention changes the structure of the preamplifier to increase the cost of one input amplifier to obtain rail-to-rail swing, and uses the combination of the clocked PMOS dynamic preamplifier and the NMOS current mirror to achieve the goal of covering a low input range. The control signals used are a pair of complementary clock signals CLK and CLKN. When CLK is at high level (VDD) and CLKN is at low level (GND), the whole comparator circuit is in a comparison state, comparing the analog signals of the input terminals VOP and VON. On the other hand, if CLK is at a low level and CLKN is at a high level, the comparator circuit is in a reset state, and the comparison between the input terminals VOP and VON is not performed. The invention adopts the idea of using complementary input pairs (PMOS dynamic preamplifier and NMOS dynamic preamplifier), realizes higher comparison speed and precision under the condition of very low input signal amplitude, and utilizes the power supply voltage swing to the maximum extent.
Claims (3)
1. A low power consumption rail-to-rail input swing comparator circuit, comprising: the dynamic pre-amplifier circuit comprises an NMOS dynamic pre-amplifier, a PMOS dynamic pre-amplifier, an NMOS current mirror and a PMOS latch;
the input end of the PMOS dynamic preamplifier is connected with an input signal, and the output end of the PMOS dynamic preamplifier is connected with an NMOS current mirror; the input end of the NMOS dynamic preamplifier is connected with an input signal, and the output end of the NMOS dynamic preamplifier is connected with the PMOS latch; the input end of the NMOS current mirror is connected with the output end of the PMOS dynamic prevention amplifier, and the output end of the NMOS current mirror is connected with the input end of the PMOS latch; the input end of the PMOS latch is connected with the output ends of the NMOS dynamic preamplifier and the NMOS current mirror, and the output end of the PMOS latch is the output of the comparator;
the adopted control signals are a pair of complementary clock signals CLK and CLKN, and all components are controlled by the CLK/CLKN clock signals; when the CLK is at the high level VDD and the CLKN is at the low level GND, the whole comparator circuit is in a comparison state, and analog signals of the input ends VOP and VON are compared; on the other hand, if CLK is at a low level and CLKN is at a high level, the comparator circuit is in a reset state, and the comparison between the input terminals VOP and VON is not performed.
2. The low power consumption rail-to-rail input swing comparator circuit of claim 1, further comprising:
the control signals CLK and CLKN are specifically:
when the clock signal CLK is at a high level VDD, and the clock signal CLKN is at a low level GND, the entire comparator circuit is in a comparison state, and compares the analog signals of the input terminals VIP and VIN; at this time, the high level of the CLK clock signal and the low level of the CLKN clock signal control the related MOS tube, so that the output of the NMOS dynamic preamplifier is output to GND, the output end of the PMOS preamplifier and the output end of the PMOS latch are connected with VDD, and the output end of the NMOS current mirror is connected with GND to form a current path; the input differential signal thus produces a differential comparison result at the comparator output.
On the contrary, if the clock signal CLK is at a low level, and the clock signal CLKN is at a high level, the comparator circuit is in a reset state, and the comparison of the input terminals VIP and VIN is not performed; at this time, since the CLK and CLKN clock signals make the NMOS dynamic preamplifier and the NMOS current mirror output terminals at the high level VDD, the PMOS dynamic preamplifier output terminals at the low level GND, and the PMOS latch output nodes are connected to GND, the comparator does not output the differential comparison result, but outputs two 0 s.
3. The low power consumption rail-to-rail input swing comparator circuit of claim 1, further comprising:
the NMOS dynamic preamplifier comprises a first NMOS tube M1A second NMOS transistor M2And the third NMOS transistor M5And a first PMOS transistor M3Second PMOS transistor M4(ii) a First NMOS transistor M1The grid end is connected with an input level VIP, the drain end is connected with the inverted input end VON of the PMOS latch, and the source end is connected with a third NMOS tube M5The drain terminal of (1); second NMOS transistor M2The grid is connected with an input level VIN, the drain is connected with a positive phase input end VOP of the PMOS input latch, and the source is connected with a third NMOS tube M5The drain terminal of (1); third NMOS transistor M5The grid electrode of the NMOS transistor is connected with a clock control signal CLK, and the drain end of the NMOS transistor is connected with a first NMOS transistor M and a second NMOS transistor M1And M2The source end is grounded at the ground potential GND; first PMOS transistor M3The drain terminal of the PMOS latch is connected with the inverted input end VON of the PMOS latch, the source electrode of the PMOS latch is connected with the power supply voltage VDD, and the grid electrode of the PMOS latch is connected with the clock signal CLK; second PMOS transistor M4The drain terminal of the PMOS latch is connected with the positive phase input terminal VOP of the PMOS latch, the source terminal of the PMOS latch is connected with the power supply voltage VDD, and the grid terminal of the PMOS latch is connected with the clock signal CLK;
the PMOS latch structure comprises a third PMOS tube M6And the fourth PMOS transistor M7And a fourth NMOS transistor M8The fifth NMOS transistor M9And a sixth NMOS transistor M10And a seventh NMOS transistor M11(ii) a Third stepPMOS tube M6The grid end VON is the inverting input end of the PMOS latch, is connected to the NMOS dynamic preamplifier and the inverting output end of the NMOS current mirror, the source end is connected with a power voltage VDD, and the drain end is connected with the positive phase output end VOUT of the comparator; fourth PMOS transistor M7The grid end VOP of the PMOS latch is a positive phase input end of the PMOS latch and is connected with positive phase output ends of the NMOS dynamic preamplifier and the NMOS current mirror, the source end of the PMOS latch is connected with a power supply voltage VDD, and the drain end of the NMOS latch is connected with a positive phase output end VOUTB of the comparator; fourth NMOS transistor M8The grid end is connected with the inverted output end VOUTB of the comparator, the drain end is connected with the positive output end VOUT of the comparator, and the source end is grounded; fifth NMOS transistor M9The grid end is connected with a positive phase output end VOUT of the comparator, the drain end is connected with a negative phase output end VOUTB of the comparator, and the source end is grounded at the ground potential GND; sixth NMOS transistor M10The grid end is connected with a comparator control clock CLKN, the drain end is connected with a positive phase output end VOUT of the comparator, and the source end is grounded; seventh NMOS transistor M11The grid end is connected with a comparator control clock CLKN, the drain end is connected with the inverted output end VOUTB of the comparator, and the source end is grounded at the ground potential GND;
the PMOS dynamic preamplifier comprises a fifth PMOS tube M12Sixth PMOS transistor M13Seventh PMOS transistor M16And an eighth NMOS transistor M14And a ninth NMOS transistor M15(ii) a The fifth PMOS tube M12The grid end is connected with an input level VIP, the drain end is connected with an NMOS tube M of the NMOS current mirror17Grid and eighth NMOS transistor M14The source end of the drain electrode is connected with a seventh PMOS tube M16The drain terminal of (1); sixth PMOS transistor M13The grid end is connected with an input level VIN, and the drain end is connected with an NMOS tube M of the NMOS current mirror18Grid and ninth NMOS transistor M15The source end of the drain electrode is connected with a seventh PMOS tube M16The drain terminal of (1); seventh PMOS tube M16The gate terminal of the transistor is connected with a control clock CLKN, and the drain terminal of the transistor is connected with a fifth PMOS tube M and a sixth PMOS tube M12And M13The source end is connected with a power voltage VDD; eighth NMOS transistor M14The grid of the NMOS transistor is connected with a control clock CLKN, the source end is grounded and connected with a ground potential GND, and the drain end is connected with an NMOS tube M of the NMOS current mirror17Gate terminal of and fifth PMOS transistor M12The drain terminal of (1); ninth NMOS transistor M15The grid of the NMOS transistor is connected with a control clock CLKN, the source end is grounded and connected with a ground potential GND, and the drain end is connected with an NMOS tube M of the NMOS current mirror18Gate terminal of and sixth PMOS transistor M13The drain terminal of (1).
The NMOS current mirror comprises a tenth NMOS tube M17And an eleventh NMOS transistor M18(ii) a Tenth NMOS transistor M17The grid end of the fifth PMOS tube M of the PMOS dynamic preamplifier is connected with12The source end is grounded at the ground potential GND, and the drain end is connected with the positive phase input end VOP of the PMOS latch; eleventh NMOS transistor M18The grid end of the sixth PMOS tube M is connected with the PMOS dynamic preamplifier13The drain terminal of the PMOS latch is connected with the ground potential GND, and the drain terminal is connected with the inverted input end VON of the PMOS latch.
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| CN202110061448.4A CN112910447A (en) | 2021-01-18 | 2021-01-18 | Low-power-consumption comparator circuit with rail-to-rail input swing amplitude |
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| CN114337617A (en) * | 2021-12-13 | 2022-04-12 | 重庆邮电大学 | A Low-Power Fast Dynamic Comparator |
| CN114665849A (en) * | 2022-02-23 | 2022-06-24 | 电子科技大学 | High-precision current comparator |
| CN115149931A (en) * | 2022-06-20 | 2022-10-04 | 共模半导体技术(苏州)有限公司 | Complementary Fully Differential Dynamic Comparator for Common-Mode Voltage Mismatch |
| CN117526944A (en) * | 2023-11-09 | 2024-02-06 | 电子科技大学 | Low-power consumption multi-bit analog voltage quantizer circuit with small area |
| CN119093929A (en) * | 2024-11-07 | 2024-12-06 | 江苏帝奥微电子股份有限公司 | A pin multiplexing circuit structure for realizing enable input and communication input |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114337617A (en) * | 2021-12-13 | 2022-04-12 | 重庆邮电大学 | A Low-Power Fast Dynamic Comparator |
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| CN115149931A (en) * | 2022-06-20 | 2022-10-04 | 共模半导体技术(苏州)有限公司 | Complementary Fully Differential Dynamic Comparator for Common-Mode Voltage Mismatch |
| CN117526944A (en) * | 2023-11-09 | 2024-02-06 | 电子科技大学 | Low-power consumption multi-bit analog voltage quantizer circuit with small area |
| CN117526944B (en) * | 2023-11-09 | 2024-11-15 | 电子科技大学 | Low-power consumption multi-bit analog voltage quantizer circuit with small area |
| CN119093929A (en) * | 2024-11-07 | 2024-12-06 | 江苏帝奥微电子股份有限公司 | A pin multiplexing circuit structure for realizing enable input and communication input |
| CN119093929B (en) * | 2024-11-07 | 2025-03-21 | 江苏帝奥微电子股份有限公司 | A pin multiplexing circuit structure for realizing enable input and communication input |
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