CN112967938B - A total dose shielding method for space-grade integrated circuits and a method for verifying the effect of radiation-resistant reinforcement - Google Patents

Abstract

The invention discloses an aerospace-level integrated circuit total dose shielding method and an anti-radiation reinforcement effect verification method, and belongs to the technical field of integrated circuits. The method comprises the following steps: (1) The method comprises the steps of (1) designing an assembly process, and developing chip selection and chip bonding, bonding and sealing process design aiming at the most core tolerance temperature in the reinforcement design; (2) The design of the shell, develop the design of the total dose shielding from aspects such as overall dimension and shell structure, etc.; (3) Test shows that the circuit after shielding reinforcement is subjected to reliability test and irradiation resistance test, and the design scheme of the shell is optimized again if necessary. The method for shielding the total dose of the integrated circuit and verifying the anti-radiation reinforcing effect can optimize the shielding effect and achieve the aerospace-level device.

Description

A total dose shielding method for space-grade integrated circuits and verification of radiation-resistant reinforcement effect Method

Technical Field

The present invention relates to the technical field of integrated circuits, and in particular to a total dose shielding method for aerospace-grade integrated circuits and a method for verifying the anti-radiation reinforcement effect.

Background Art

With the development of satellite technology, while satellite performance is constantly improving, its working life has been extended to months and years. Small and medium-sized integrated circuits have begun to be used in onboard electronic equipment. The total dose effect shows that the harm to satellites has increased, causing attention to satellite reinforcement work. The total dose effect is the degradation of electrical properties caused by the interaction between irradiated particles and aerospace-grade integrated circuit chip materials. Various artificial satellites and spacecraft operating in space will be exposed to various radiations such as charged particles from the earth and cosmic rays from the sun, causing varying degrees of damage.

Today, satellites have been commercialized and have become an industry in the world, with fierce international competition. In order to meet the needs of my country's national defense construction, national economy and social development, users have higher and higher requirements for satellite performance, that is, they require satellites to provide a high payload ratio (the ratio of satellite payload weight to satellite total weight), and require satellites to have strong on-orbit autonomy, high precision and good dynamic performance. In satellite design, large-scale integrated circuits and onboard computers are needed to achieve long life, high reliability and high performance design requirements. However, one of their defects is that they are sensitive to radiation and have poor radiation resistance.

In order to improve the radiation resistance of satellites and other spacecraft, many countries in the world are committed to the research of anti-nuclear reinforcement technology. The anti-radiation reinforcement technology of microelectronic devices is the guarantee for the reliable operation of electronic systems or devices in radiation environments. The research on the anti-radiation reinforcement technology of electronic components covers a series of reinforcement technologies from material selection to component structure, manufacturing process, circuit design, shielding and packaging inside the device.

Using effective materials to shield space radiation and prevent chips from being affected by radiation has the characteristics of low cost, simple and practical manufacturing process, and high versatility. Research on structures and methods with high efficiency and radiation resistance and lightweight is one of the development directions of future radiation resistance reinforcement technology.

Summary of the invention

The purpose of the present invention is to provide a total dose shielding method for aerospace-grade integrated circuits and a method for verifying the anti-radiation reinforcement effect. The method of the present invention can optimize the shielding effect and meet the requirements of aerospace-grade devices.

To achieve the above purpose, the technical solution adopted by the present invention is as follows:

A total dose shielding method for aerospace-grade integrated circuits, the method comprising the following steps:

(1) Assembly process design: Aiming at the core temperature tolerance in the radiation hardening design of integrated circuit chips, the chip selection, die bonding, bonding and sealing processes are designed to enable the integrated circuit assembly process to withstand a temperature of 300°C;

(2) Package shell design: Total dose shielding design is carried out based on the package shell structure and external dimensions.

The assembly process design of step (1) above includes the following steps (1a)-(1d):

(1a) Chip selection: Perform a temperature resistance test on the chips used: First, perform a wafer test on the bare chips. If the test passes, it means that the electrical performance of the bare chips on the wafer is good. Then, perform a high-temperature baking on the wafer. The high-temperature baking condition is 300°C for 1 hour. After the high-temperature baking, perform an electrical performance test on the wafer. If the electrical performance is good, the chip can be selected. Otherwise, the chip must be replaced.

(1b) Bonding process: When welding the chip to the shell, a high-temperature alloy should be selected as the welding material for welding, or a high-temperature glue with a temperature resistance of more than 300°C should be selected to weld the chip by bonding; the high-temperature alloy selected in the welding is a lead-indium-silver alloy sheet, a lead-tin-silver alloy sheet, a gold-silicon alloy sheet or a gold-germanium alloy sheet. It is not advisable to select a gold-tin alloy sheet or a tin-lead solder with a lower temperature when welding.

(1c) Bonding process: Aluminum wire is used as bonding wire (preferably Al-Si wire with a wire diameter of 32 μm);

(1d) Sealing process: Select the parallel seam welding sealing process to complete the sealing between the cover plate and the tube shell.

In the process of designing the package shell in the above step (2), a flattened structure is adopted in which pins are led out from the sides of the shell so as to maximize the area and height ratio of the shell. At the same time, shielding layers are provided on the upper and lower parts of the shell to achieve the maximum shielding effect. The flattened structure design can increase the adhesion between the shielding material and the shell, thereby improving the overall reliability of the shielding structure in environments such as stress and temperature.

In the process of designing the package shell in the above step (2), the shielding layers on the upper and lower surfaces of the shell have a process boundary of 1-2mm from the outermost frame of the shell; the upper shielding layer and the lower shielding layer of the shell are no more than 1mm away from the chip plane; the shielding layers can be arranged on the upper and lower surfaces of the shell, or the upper shielding layer can be embedded in the cavity, and the lower shielding layer can be embedded in the back of the shell, that is, the back of the shell has a mounting groove for the shielding layer; it is sufficient to ensure that the upper and lower shielding layers cover the upper and lower surfaces of the chip respectively; the area of the upper and lower shielding layers should be larger than the chip area, and the length of each side of the shielding layer should be at least 0.5mm longer than the side length of the chip, and the strength of the package structure should not be damaged while ensuring the adhesion strength.

The shielding layer is a double-layer composite structure formed by an inner secondary ionization absorption layer and an outer main shielding layer; the space radiation sources that cause the total dose effect in the GEO orbit are mainly protons and electrons, the main shielding layer is used to directly block protons and electrons, and the secondary ionization absorption layer is used to absorb secondary ionization generated after protons and electrons act on the main shielding layer.

The material of the main shielding layer is a metal or non-metal material with a high atomic number, preferably a metal such as nano-bismuth oxide, nano-tungsten, nano-tantalum or nano-lead; the thickness of the main shielding layer is 0.2-0.4 mm (preferably 0.3 mm), and the main shielding layer is doped with 0.5-2 wt.% of lanthanide rare earth elements; the material of the secondary ionization absorption layer is a metal with a low atomic number, preferably aluminum; the thickness of the secondary ionization absorption layer is 0.1-0.3 mm (preferably 0.15 mm).

The shielding layer is prepared on the shell by welding, bonding, cold spraying or atomic deposition process, and the process temperature should be controlled within 350°C.

The method for verifying the radiation resistance reinforcement effect of the integrated circuit designed by the total dose shielding method of the aerospace-grade integrated circuit is characterized in that: the integrated circuit after shielding reinforcement is subjected to reliability test and radiation resistance test, and the specific process is as follows:

(A) Reliability verification: Check the bonding stability between the shielding layer and the shell, including temperature cycle test, constant acceleration test and appearance inspection; in the temperature cycle test, the test conditions are: the cycle temperature range is -65 to 150°C or -55 to 125°C, the number of cycles is 200 times, and the coating is qualified if there is no shedding after the test; the constant acceleration test is qualified if the coating is qualified under the conditions of 10000g or 5000g acceleration; the appearance inspection is to observe the shielding layer with a microscope of 50 times or more, and it is qualified if there is no shedding, cracks or damage.

(B) Radiation resistance test: A high level is applied to the power pin of the chip, a low level is applied to the ground pin, an input signal is applied to the input pin, and the output pin is left floating. Then an ammeter is used to monitor the change in power current. By comparing the leakage current of the reinforced design and the original chip after being exposed to radiation to the same level, the difference in the total radiation dose received by the two is the radiation resistance value improved by the reinforced design.

The beneficial effects are as follows:

The present invention effectively improves the radiation shielding performance of the device by designing the assembly process and the packaging shell of the integrated circuit and performing reliability tests and radiation resistance tests on the shielded and reinforced circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flow chart of the total dose shielding method for aerospace-grade integrated circuits and the method for verifying the anti-radiation reinforcement effect of the present invention.

FIG. 2 is a structural diagram of an integrated circuit housing.

FIG. 3 is a structural diagram of a shielding layer on an integrated circuit housing of the present invention.

FIG. 4 is a QFP (quad flat package) integrated circuit in Example 1.

FIG. 5 is a DIP (dual in-line package) integrated circuit in Embodiment 2.

FIG6 is a comparison of the total radiation dose received after the reinforcement design is performed in Example 1 and after the reinforcement design is performed.

DETAILED DESCRIPTION

In order to further understand the present invention, the present invention is described below in conjunction with examples, but the examples are only for further elaboration of the features and advantages of the present invention, rather than for limiting the claims of the present invention.

The present invention first provides a total dose shielding method for aerospace-grade integrated circuits and a method for verifying the shielding effect, and the specific process is shown in Figure 1. The process of the total dose shielding method for aerospace-grade integrated circuits is as follows: first, the integrated circuit assembly process design is performed: for the core temperature tolerance in the chip reinforcement design, chip selection and die bonding, bonding, and sealing process design are performed; then, the package shell design is performed: the total dose shielding design is performed based on the package shell structure and external dimensions.

In view of the most core temperature tolerance in the reinforcement design, chip selection and bonding, bonding, and sealing process design are carried out. Because in the subsequent preparation of the shielding layer, it is inevitable to apply a certain process temperature, which generally reaches above 300°C. Therefore, it is necessary to select a process that can withstand a temperature of 300°C when designing the assembly process. The details are as follows:

(1) Chip selection: Perform temperature resistance test on the chips used. First, perform wafer test on bare chips. If the test is passed, it means that the electrical performance of bare chips on the wafer is good. Then, perform high temperature baking on the wafer. The high temperature baking condition is 300℃ for 1 hour. After high temperature baking, perform electrical performance test on the wafer again. If the electrical performance is good, the chip can be selected. Otherwise, the chip must be replaced.

(2) The bonding process: high-temperature alloys should be used for welding the chip to the shell. The preferred materials are lead-indium-silver alloy sheets, lead-tin-silver alloy sheets, gold-silicon alloy sheets, gold-germanium alloy sheets, or high-temperature glue that can withstand temperatures above 300°C. It is not advisable to choose gold-tin alloy sheets, tin-lead solder, etc. with lower temperatures.

(3) Bonding process: Considering that the coating material on the chip PAD point is aluminum, in order to avoid the gold-aluminum effect in a high temperature environment that reduces the bonding reliability, aluminum wire should be used as the bonding wire, preferably 32μm Al-Si wire.

(4) Sealing process: preferably, parallel seam welding sealing process is used to complete the sealing between the cover plate and the tube shell. It is not easy to choose gold-tin alloy sintering sealing process.

The shell design includes: shell structure and external dimensions. On the one hand, a flattened structure is adopted in which pins are led out from the sides to maximize the shell area and height ratio. After adding shielding materials on the upper and lower surfaces of the shell, the maximum shielding effect is achieved. On the other hand, the flattened design can increase the adhesion between the shielding material and the shell, and improve the overall reliability of the shielding structure in stress, temperature and other environments. The details are as follows:

(1) The preferred housing form is one in which the pins are led out from the side, such as a QFP (quad flat housing), as shown in FIG2 .

(2) The upper and lower surfaces of the shell have shielding layers (Figure 3). The shielding layer has a process boundary of 1-2 mm from the outermost frame of the shell. If there is no process boundary, the coating will have poor adhesion to the edge of the shell.

The distance between the upper and lower shielding layers and the chip plane should not exceed 1mm. The upper and lower shielding layers should be as close to the chip as possible to avoid the radiation of rays with low incident angles. The upper shielding layer can be embedded in the cavity, and the lower shielding layer can be embedded in the back of the shell, that is, a mounting groove is reserved on the back of the shell.

The upper and lower shielding layers need to cover the upper and lower surfaces of the chip. Their area should be larger than the chip area. The length of each side should be at least 0.5 mm longer than the side length of the chip. Under the premise of ensuring the adhesion strength, the strength of the package structure should not be destroyed.

The shielding layer is a double-layer structure, including the main shielding layer and the secondary ionization absorption layer. The space radiation sources that cause the total dose effect in the GEO orbit are mainly protons and electrons. The main shielding layer is used to directly block protons and electrons, and the secondary ionization absorption layer is used to absorb the secondary ionization generated after protons and electrons act on the main shielding layer.

(3) The material of the main shielding layer is preferably a metal or non-metal material with a high atomic number, preferably nano-bismuth oxide. Bismuth oxide itself has stable physical and chemical properties and is an environmentally friendly material that is harmless to the human body. At the same time, bismuth oxide is easier to combine with the shell, and the interface bonding force is higher. In addition, metals such as nano-tungsten, nano-tantalum, and nano-lead can also be selected.

The thickness of the main shielding layer is 0.2-0.4 mm, preferably 0.3 mm.

The main shielding layer is doped with 0.5% to 2% by mass of lanthanide rare earth elements.

(4) The material of the secondary ionization absorption layer is preferably a metal with a low atomic number, such as aluminum.

The thickness of the secondary ionization absorption layer is 0.1-0.3 mm, preferably 0.15 mm.

(5) The shielding layer can be installed by welding, bonding, cold spraying, atomic deposition and other methods, and the process temperature should be controlled within 350°C.

Conduct reliability tests and radiation resistance tests on the shielded and reinforced circuits, as follows:

(1) Reliability verification mainly tests the bonding stability between the shielding layer and the shell, including temperature cycle test (the test conditions are preferably -65℃～150℃, 200 times, and the coating does not fall off. The temperature range of -55℃～125℃ can also be selected), constant acceleration test (10000g acceleration, the coating does not fall off. 5000g can also be selected), and appearance inspection (the shielding layer is observed under a microscope of 50 times or more to ensure that there is no shedding, cracks, or damage).

(2) Anti-radiation test is mainly to verify whether the total dose reinforcement design scheme of components can protect the chip to meet the design requirements.

During the radiation resistance test, a high level is applied to the power pin of the chip, a low level is applied to the ground pin, an input signal is applied to the input pin, the output pin is left floating, and the change of the power supply current is monitored by an ammeter. By comparing the leakage current of the reinforced design and the original chip after being irradiated to the same level, the difference in the total radiation dose received by the two is the radiation resistance value improved by the reinforced design.

(3) If the reliability test and radiation resistance test do not meet the requirements, it is necessary to optimize the shell structure and external dimensions, and then conduct reliability test and radiation resistance test again until the ideal effect is achieved.

Embodiment 1:

A QFP (quad flat package) integrated circuit ( FIG4 ) adopts a reinforcement design scheme of nano-Al and nano-Ta, respectively, with a shielding layer thickness of 0.5 mm and a secondary ionization absorption layer thickness of 0.2 mm.

During the reliability test, it was found that the Ta coating often fell off due to its excessive thickness. Therefore, the optimization plan was to use a Ta shielding layer with a thickness of 0.2 mm and an Al secondary ionization absorption layer with a thickness of 0.15 mm.

The circuit after shielding reinforcement was subjected to reliability test and radiation resistance test. The temperature cycle was -65℃～150℃, and there was no shedding for 200 times. The constant acceleration test was 10000g without shedding. The radiation test was completed with 1MeV electron accelerator. The results showed that the coating increased the total electron dose index by 30K krad(Si), as shown in Figure 6.

Embodiment 2:

A DIP (dual in-line package) integrated circuit ( FIG5 ) adopts a reinforcement design scheme of nano-Al and nano-Cu, respectively, with a shielding layer thickness of 0.5 mm and a secondary ionization absorption layer thickness of 0.2 mm Al.

The shielded and reinforced circuits were subjected to reliability tests and radiation resistance tests. The temperature cycle was -65℃～150℃, and there was no shedding for 200 times. The constant acceleration test was 10000g without shedding. The radiation test was completed using a 1MeV electron accelerator. The results showed that the coating increased the total electron dose index by 20K krad(Si).

Embodiment 3:

A DIP (dual in-line package) integrated circuit adopts a reinforcement design scheme of nano-Al and nano-Ta respectively, and mixes nano-Al and nano-Ta together to form a shielding layer and a secondary ionization absorption layer, with a total thickness of 0.35mm.

The shielded and reinforced circuits were subjected to reliability tests and radiation resistance tests. The temperature cycle was -65℃～150℃, and there was no shedding for 200 times. The constant acceleration test was 10000g without shedding. The radiation test was completed using a 1MeV electron accelerator. The results showed that the coating increased the total electron dose index by 30K krad(Si).

Claims (9)

1. A total dose shielding method for an aerospace-level integrated circuit is characterized by comprising the following steps of: the method comprises the following steps:

(1) And (3) the assembly process design: aiming at the most core resistant temperature in the radiation-resistant reinforcement design of the integrated circuit chip, the chip selection, the bonding and the sealing processes are designed, so that the integrated circuit can resist 300 ℃ in the assembly process;

(2) And (3) designing a packaging shell: performing a total dose shield design from the package housing structure and the form factor;

The assembly process design of the step (1) comprises the following steps (1 a) - (1 d):

(1a) Chip selection: and (3) performing temperature resistance test on the used chip: firstly, testing a bare chip by a wafer, and after the test is passed, indicating that the electrical performance of the bare chip on the wafer is good; then, baking the wafer at a high temperature under the condition of 300 ℃ for 1 hour; after baking at high temperature, testing the electrical property of the wafer, if the electrical property is good, selecting the chip, otherwise, replacing the chip;

(1b) And (3) a sticking process: when the chip and the shell are welded, a high-temperature alloy is selected as a welding material for welding, or a high-temperature adhesive with the temperature resistance of more than 300 ℃ is selected for welding the chip in an adhesive mode;

(1c) And (3) a bonding process: aluminum wires are selected as bonding wires during bonding;

(1d) The sealing process comprises the following steps: and (5) sealing between the cover plate and the tube shell is completed by selecting a parallel seam welding sealing process.

2. The aerospace level integrated circuit total dose shielding method of claim 1, wherein: in the step (1 b), the high-temperature alloy selected in the welding is a lead-indium-silver alloy sheet, a lead-tin-silver alloy sheet, a gold-silicon alloy sheet or a gold-germanium alloy sheet, and the gold-tin alloy sheet or tin-lead solder with lower temperature is not selected during the welding.

3. The aerospace level integrated circuit total dose shielding method of claim 1, wherein: in the design process of the packaging shell, a flattened structure with pins led out from the periphery of the side surface of the shell is adopted, so that the area and the height ratio of the shell are improved as much as possible, and shielding layers are arranged at the upper part and the lower part of the shell to achieve the maximum shielding effect; the flat structure design can increase the adhesive force between the shielding material and the shell, so that the whole reliability of the shielding structure is improved in the environments of stress, temperature and the like.

4. The aerospace level integrated circuit total dose shielding method of claim 3, wherein: in the design process of the packaging shell, the shielding layers on the upper surface and the lower surface of the shell are 1-2mm away from the outermost frame of the shell; the distance between the upper shielding layer and the lower shielding layer of the shell and the plane of the chip is not more than 1mm; the shielding layers can be arranged on the upper surface and the lower surface of the shell, or the upper shielding layer can be embedded in the cavity, and the lower shielding layer can be embedded on the back surface of the shell, namely, the mounting groove of the shielding layer is reserved on the back surface of the shell; only the upper shielding layer and the lower shielding layer are ensured to cover the upper surface and the lower surface of the chip respectively; the areas of the upper shielding layer and the lower shielding layer are larger than the area of the chip, the side length of each side of the shielding layer is at least 0.5mm larger than the side length of the chip, and the strength of the packaging structure is not damaged on the premise of ensuring the adhesion strength.

5. The aerospace level integrated circuit total dose shielding method of claim 3, wherein: the shielding layer is a double-layer composite structure formed by an inner secondary ionization absorption layer and an outer main shielding layer; the spatial radiation source causing the total dose effect at the GEO orbit is mainly protons and electrons, the main shielding layer is used for directly blocking the protons and the electrons, and the secondary ionization absorption layer is used for absorbing the secondary ionization generated after the protons and the electrons act on the main shielding layer.

6. The method of total dose masking for an aerospace level integrated circuit of claim 5, wherein: the main shielding layer is made of metal or nonmetal materials with high atomic numbers, the thickness of the main shielding layer is 0.2-0.4mm, and 0.5-2 wt.% of lanthanide rare earth elements are doped in the main shielding layer;

the material of the secondary ionization absorption layer is metal with low atomic number, and the thickness of the secondary ionization absorption layer is 0.1-0.3mm.

7. The method of total dose masking for an aerospace level integrated circuit of claim 6, wherein: the shielding layer is prepared on the shell by adopting welding, bonding, cold spraying or atomic deposition process, and the process temperature is controlled within 350 ℃.

8. A method for verifying the radiation-proof reinforcement effect of an integrated circuit designed by the total dose shielding method of an aerospace-level integrated circuit according to any one of claims 1 to 7, wherein: and carrying out a reliability test and an irradiation resistance test on the integrated circuit after shielding reinforcement, wherein the specific process is as follows:

(A) And (3) reliability verification: checking the bonding stability between the shielding layer and the shell, including a temperature cycle test, a constant acceleration test and an appearance check;

(B) Irradiation resistance test: applying high level to a power supply pin of the chip, applying low level to a grounding pin, applying an input signal to an input pin, suspending an output pin, and then monitoring the change condition of power supply current by using an ammeter; when the leakage current is increased to the same level after the reinforcing design scheme and the original chip are subjected to radiation, the difference value of the total radiation dose received by the reinforcing design scheme and the original chip is the radiation resistance value improved by the reinforcing design scheme.

9. The irradiation resistance reinforcing effect verification method according to claim 8, wherein: in the step (a), in the temperature cycle test, the test conditions are as follows: the circulation temperature interval is-65-150 ℃ or-55-125 ℃, the circulation times are 200 times, and the coating is qualified after the test without falling off; the constant acceleration test is that the coating is qualified under the acceleration condition of 10000g or 5000g without falling off; the appearance inspection is to observe the shielding layer by a microscope with the power of more than 50 times, and the shielding layer is qualified when no falling, crack or damage occurs.