CN112986796A

CN112986796A - Parameter trimming device and method for chip

Info

Publication number: CN112986796A
Application number: CN202110174507.9A
Authority: CN
Inventors: 李卓研; 李萌; 朱力强
Original assignee: On Bright Electronics Shanghai Co Ltd
Current assignee: On Bright Electronics Shanghai Co Ltd
Priority date: 2021-02-07
Filing date: 2021-02-07
Publication date: 2021-06-18
Also published as: TW202232704A; TWI763469B

Abstract

Provided are a parameter trimming device and method for a chip. The parameter trimming device includes a switch, a parameter trimming signal, and a latch, wherein: the switch controls whether the bias current for the parameter trimming signal is provided or not; when the parameter trimming signal is provided with the bias current, the The bias current generates the parameter trimming signal and provides the parameter trimming signal to the latch; the latch generates the latch trimming signal by latching the parameter trimming signal and provides the latch trimming signal to the chip of the chip The control circuit enables the chip control circuit to trim one or more parameters inside the chip based on the latch trim signal. The parameter trimming device and method for a chip according to the embodiments of the present invention can realize continuous trimming of one or more parameters inside the chip without continuous bias current, thus reducing the operating current of the chip , thereby reducing the power consumption of the chip.

Description

Parameter trimming device and method for chip

Technical Field

The invention relates to the field of circuits, in particular to a parameter trimming device and method for a chip.

Background

Some parameters inside the chip need to be modified during the chip test. These parameters may be reference voltage, bias current, oscillator frequency, or function selection, etc. There are many parameter trimming methods for chips, and trimming by fusing fuses is a widely used method.

Fig. 1 is a schematic diagram illustrating a conventional fuse blow trimming method. In fig. 1, R _ fuse is a resistance related to the resistance of the fuse, and I _ bias is a fixed bias current; when one or more parameters in the chip do not need to be modified, the fuse is not blown, the R _ fuse is small, and the parameter modifying circuit 100 outputs a logic low level parameter modifying signal Trim _ logic to the chip control circuit 200; when one or more parameters inside the chip need to be modified, the fuse is blown, the R _ fuse increases due to the blown fuse, and the parameter modifying circuit 100 outputs the parameter modifying signal Trim _ logic of a logic high level to the chip control circuit 200. When the chip operates, the chip control circuit 200 may Trim one or more parameters inside the chip according to the parameter trimming signal Trim _ logic.

Fig. 2 is a schematic diagram of a parameter trimming circuit 100 for implementing the trimming method shown in fig. 1. As shown in fig. 2, the parameter trimming circuit 100 includes a resistor R1 and a shaping circuit buffer 1; the bias current I1 flows through the resistor R1 and the fuse1 connected in series, and the generated voltage is subjected to level shaping by the shaping circuit Bufer1 to generate a digital signal; when one or more parameters in the chip do not need to be modified, the fuse1 is not blown, the total impedance of the resistor R1 and the fuse1 is small, the voltage generated by the bias current I1 flowing through the resistor R1 and the fuse1 at the node A1 is smaller than the overturning threshold value of the shaping circuit Buffer1, and the shaping circuit Buffer1 outputs a parameter modification signal B1 with a logic low level; when one or more parameters in the chip need to be modified, the fuse1 is blown, the total impedance of the resistor R1 and the fuse1 is large, the voltage generated by the bias current I1 flowing through the resistor R1 and the fuse1 at the node a1 is larger than the flipping threshold of the shaping circuit Buffer1, and the shaping circuit Buffer1 outputs a parameter modification signal B1 with a logic high level.

In order to ensure that the chip control circuit 200 receives the continuous parameter trimming signal B1, a continuous bias current I1 needs to be provided to the parameter trimming circuit 100. When a plurality of trimming bits inside a chip need to be trimmed, a plurality of bias currents are needed, which may result in an increase in the operating current of the chip.

Disclosure of Invention

In view of the above-mentioned problems, a parameter trimming apparatus and method for a chip according to an embodiment of the present invention are proposed.

The parameter trimming device for the chip according to the embodiment of the invention comprises a switch, a parameter trimming circuit and a latch, wherein: the switch controls whether the bias current of the parameter trimming circuit is provided or not; when the bias current is provided to the parameter trimming circuit, generating a parameter trimming signal by using the bias current and providing the parameter trimming signal to the latch; the latch generates a latch trimming signal by latching the parameter trimming signal and provides the latch trimming signal to a chip control circuit of the chip, so that the chip control circuit trims one or more parameters inside the chip based on the latch trimming signal.

The parameter trimming method for the chip according to the embodiment of the invention comprises the following steps: in a preset time period after the chip is electrified, generating a parameter trimming signal based on the bias current; latching the parameter trimming signal at a predetermined time in a predetermined period to generate a latched trimming signal; and utilizing the latch trimming signal to trim one or more parameters inside the chip.

In the parameter trimming device and method for the chip according to the embodiments of the present invention, the latch trimming signal is generated by latching the parameter trimming signal, and one or more parameters inside the chip are trimmed based on the latch trimming signal, so that the continuous trimming of the one or more parameters inside the chip can be achieved without a continuous bias current. Therefore, the operating current of the chip can be reduced, thereby reducing the power consumption of the chip.

Drawings

The invention may be better understood from the following description of specific embodiments thereof taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic diagram illustrating a conventional fuse blow trimming method.

Fig. 2 is a schematic diagram of a parameter trimming circuit for implementing the trimming method shown in fig. 1.

Fig. 3 is a schematic diagram illustrating a parameter tuning apparatus for a chip according to an embodiment of the present invention.

Fig. 4 is a timing diagram showing a plurality of signals related to the parameter trimming apparatus shown in fig. 3.

Fig. 5 illustrates an example circuit implementation of the latch shown in fig. 3.

Fig. 6 shows a flowchart of a parameter trimming method for a chip according to an embodiment of the present invention.

Detailed Description

Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is in no way limited to any specific configuration and algorithm set forth below, but rather covers any modification, replacement or improvement of elements, components or algorithms without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present invention.

In view of the above problems of the conventional fuse blowing trimming method, a parameter trimming device and method for a chip are provided, wherein a parameter trimming signal output by a parameter trimming circuit is locked at the beginning of chip power-on, and then the parameter trimming circuit is closed, so that the current of the parameter trimming circuit during chip operation is reduced to an extremely low value close to 0A, and the working current of the chip is reduced, thereby reducing the power consumption of the chip.

Fig. 3 is a schematic diagram illustrating a parameter tuning apparatus 300 for a chip according to an embodiment of the present invention. As shown in fig. 3, the parameter tuning apparatus 300 includes a switch S1, a parameter tuning circuit 302, and a latch 304, wherein: the switch S1 controls the supply or non-supply of the bias current I1 to the parameter trimming circuit 302; the parametric trimming circuit 302, when supplied with the bias current I1, generates the parametric trimming signal B1 using the bias current I1 and supplies the parametric trimming signal B1 to the latch 304; the latch 304 generates a latch trim signal B1_ latch by latching the parameter trim signal B1 and supplies the latch trim signal B1_ latch to the chip control circuit 200 of the chip, so that the chip control circuit 200 trims one or more parameters inside the chip based on the latch trim signal B1_ latch.

As shown in fig. 3, in some embodiments, the switch S1 controls the supply or non-supply of the bias current I1 to the parameter trimming circuit 302 based on the trimming down electric signal Trimpower down. For example, in some embodiments, when the Trim down electrical signal Trim power down is at a logic low level, the switch S1 is in a closed state, and the parameter trimming circuit 302 is provided with the bias current I1 (i.e., the parameter trimming circuit 302 is turned on); when the Trim down electrical signal Trim power down is at a logic high level, the switch S1 is in an off state, and the parameter trimming circuit 302 is not supplied with the bias current I1 (i.e., the parameter trimming circuit 302 is turned off).

As shown in fig. 3, in some embodiments, the latch 304 latches the parameter trimming signal B1 based on the trimming latch signal Trimlatch. For example, in some embodiments, when the trimming latch signal Trim latch is at a logic high level, the latch 304 latches the parameter trimming signal B1; when the trimming latch signal is at a logic low level, the latch 304 outputs a logic low level.

Fig. 4 is a timing diagram of a plurality of signals associated with the parameter tuning apparatus 300 shown in fig. 3. As can be seen from fig. 3 and 4, after the chip is powered on, the timing enable signal en changes from a logic low level to a logic high level, and the timer of the chip starts timing; the trimming lower electrical signal Trim powerdown is at a logic low level, the switch S1 is in a closed state, and the parameter trimming circuit 302 generates a parameter trimming signal B1 at a logic high level based on the bias current I1; when the timer counts a first predetermined time T1, the trimming latch signal Trim latch changes from a logic low level to a logic high level, and the latch 304 latches the parameter trimming signal B1 at the logic high level to generate a latch trimming signal B1_ latch at the logic high level; when the timer counts to the second predetermined time T2, the trimming-down electrical signal Trim power down changes from a logic low level to a logic high level, the switch S1 is turned off, the parameter trimming circuit 302 is turned off (i.e., the bias current I1 is not supplied to the parameter trimming signal 302), the current Trim cell current in the parameter trimming circuit 302 is 0, and the parameter trimming signal B1 changes from a logic high level to a logic low level.

Since the parameter trimming signal B1 has been latched by the latch 304 at the first predetermined time T1, the parameter trimming circuit 302 is turned off and does not affect the chip control circuit 304 to trim one or more parameters inside the chip. In the subsequent working period of the chip, the power consumption of the parameter trimming circuit 302 is close to zero, so that the power consumption of the chip can be reduced.

In other words, as can be seen from fig. 3 and 4, when the timer counts to the first predetermined time T1, the latch 304 latches the logic level of the parameter trimming signal B1 to generate a latched trimming signal B1_ latch for the chip control circuit 200 to trim one or more parameters inside the chip; when the timer counts a second predetermined time T2, S1 turns off, the bias current I1 flowing to the parameter trimming circuit 302 is cut off, the parameter trimming circuit 302 turns off, the current Trim cell current in the parameter trimming circuit 302 decreases to approximately 0 ampere, and the parameter trimming signal B1 changes from a logic high level to a logic low level.

As can be seen in connection with fig. 4, in some embodiments, the latch 304 generates the latch trim signal B1_ latch by latching the parameter trim signal B1 at a first predetermined time (e.g., T1) after the power-on time of the chip. In addition, in some embodiments, the switch S1 is in a closed state for a period from a power-on time of the chip to a second predetermined time (e.g., T2), and is in an off state after the second predetermined time. It will be appreciated that the second predetermined time is subsequent to the first predetermined time (i.e., the second predetermined time is later than the first predetermined time).

Fig. 5 illustrates an example circuit implementation of the latch shown in fig. 3. In the circuit implementation shown in fig. 5, when the trimming latch signal Trim latch is at a logic low level, the latch trimming signal B1_ latch generated by the latch 304 is at a logic low level; when the trimming latch signal Trim latch is at a logic high level, the latch 304 latches the parameter trimming signal B1 to the output terminal of the latch 304. Specifically, when the parameter trimming signal B1 is at a logic low level, the latch trimming signal B1_ latch is at a logic low level; when the parameter trimming signal B1 is at a logic high level, the latch trimming signal B1_ latch is at a logic high level. When the trimming-down electrical signal Trim power down turns off the parameter trimming circuit 302, the parameter trimming signal B1 changes from logic high to logic low and does not affect the latch trimming signal B1_ latch.

Fig. 6 shows a flowchart of a parameter trimming method 400 for a chip according to an embodiment of the invention. As shown in fig. 6, the parameter tuning method 400 includes: s402, in a preset time period after the chip is electrified, generating a parameter trimming signal based on the bias current; s404, latching the parameter trimming signal at a preset moment in a preset time period to generate a latching trimming signal; and S406, utilizing the latch trimming signal to trim one or more parameters in the chip.

In summary, according to the device and the method for trimming parameters of a chip in the embodiments of the present invention, the parameter trimming signal output by the parameter trimming circuit is latched at the beginning of the chip start, and then the parameter trimming circuit is turned off, so that the current of the parameter trimming circuit during the chip operation is reduced to an extremely low value close to 0 a, thereby reducing the operating current and the power consumption of the chip.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. For example, the algorithms described in the specific embodiments may be modified without departing from the basic spirit of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

1. A parameter trimming device for a chip, comprising a switch, a parameter trimming signal, and a latch, wherein:

the switch controls whether the bias current for the parameter trimming signal is provided or not;

the parameter trimming signal, when supplied with the bias current, generates a parameter trimming signal using the bias current and provides the parameter trimming signal to the latch;

The latch generates a latch trim signal by latching the parameter trim signal and provides the latch trim signal to the chip control circuit of the chip, so that the chip control circuit is based on the parameter trim signal. The latch trim signal trims one or more parameters inside the chip.

2 . The parameter trimming apparatus of claim 1 , wherein the latch generates the said parameter trimming signal by latching the parameter trimming signal at a first predetermined time after the power-on time of the chip. 3 . Latch trim signal.

3. The parameter trimming device according to claim 1, wherein the switch is in a closed state during a period from the power-on time of the chip to a second predetermined time, and at the second predetermined time Then in an off state, the second predetermined time is later than the first predetermined time, the parameter trim signal is supplied with the bias current when the switch is in the closed state, and the switch is in the closed state The bias current is not supplied in the off state.

4. The parameter trimming apparatus according to any one of claims 1 to 3, wherein the switch controls whether or not to supply the bias current for the parameter trimming signal based on a trimming down power signal.

5. The parameter trimming device of claim 4, wherein the switch is in a closed state when the trimming power-off signal is a logic low level, and when the trimming power-off signal is a logic high level in the off state.

6. The parameter trimming apparatus according to any one of claims 1 to 3, wherein the latch latches the parameter trimming signal based on the trimming latch signal.

7. The parameter trimming device of claim 6, wherein the latch latches the parameter trimming signal when the trimming latch signal is at a logic high level, and latches the parameter trimming signal when the trimming latch signal is at a logic high level. A logic low level is output when the tune latch signal is a logic low level.

8. A chip, comprising the parameter adjustment device according to any one of claims 1 to 7.

9. A parameter trimming method for a chip, comprising:

generating a parameter trimming signal based on the bias current in a predetermined period after the chip is powered on;

latching the parameter trim signal at a predetermined time in the predetermined period to generate a latch trim signal; and

One or more parameters inside the chip are trimmed using the latch trim signal.