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CN113066852B - Sensing Power Semiconductor Devices - Google Patents

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CN113066852B
CN113066852B CN202110274144.6A CN202110274144A CN113066852B CN 113066852 B CN113066852 B CN 113066852B CN 202110274144 A CN202110274144 A CN 202110274144A CN 113066852 B CN113066852 B CN 113066852B
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CN113066852A (en
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朱袁正
黄薛佺
杨卓
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Wuxi NCE Power Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/668Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/669Vertical DMOS [VDMOS] FETs having voltage-sensing or current-sensing structures, e.g. emulator sections or overcurrent sensing cells
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/111Field plates
    • H10D64/117Recessed field plates, e.g. trench field plates or buried field plates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141VDMOS having built-in components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Abstract

本发明公开了一种感测功率半导体器件,其中的主晶体管具有第一电流路径,副晶体管具有第二电流路径,用于监测第一电流路径中的电流,感测晶体管具有第三电流路径,用于监测第二电流路径中的电流,最终感测晶体管能够间接监测第一电流路径中的电流;其中的测温二极管具有第四电流路径,用于监测功率半导体的芯片温度,本发明器件将感测晶体管内的电流进一步缩小,以便增大采样电阻,提高精准度,同时还可以减少能量的浪费。

Figure 202110274144

The invention discloses a sensing power semiconductor device, wherein a main transistor has a first current path, a secondary transistor has a second current path for monitoring the current in the first current path, and the sensing transistor has a third current path, It is used to monitor the current in the second current path, and finally the sensing transistor can indirectly monitor the current in the first current path; the temperature measuring diode has a fourth current path for monitoring the chip temperature of the power semiconductor, and the device of the present invention will The current in the sensing transistor is further reduced in order to increase the sampling resistance, improve the accuracy, and reduce the waste of energy.

Figure 202110274144

Description

感测功率半导体器件Sensing Power Semiconductor Devices

技术领域technical field

本发明涉及功率半导体器件技术领域,具体地说是一种集成电流监测与温度监测的功率半导体器件。The invention relates to the technical field of power semiconductor devices, in particular to a power semiconductor device integrating current monitoring and temperature monitoring.

背景技术Background technique

在终端应用中,一些厂商希望能监测流过功率器件的电流,以便故障检测、电流大小控制。用以测量功率器件中的电流的结构通常被称为感测场效应晶体管。感测场效应晶体管是与主功率场效应晶体管分离开的小的场效应晶体管。感测场效应晶体管一般被配置为产生与主场效应晶体管中的电流相对应的电压以便提供电流感测,并且可以被集成到与主场效应晶体管相同的半导体芯片中。In the end application, some manufacturers want to monitor the current flowing through the power device for fault detection and current size control. The structures used to measure current in power devices are often referred to as sensing field effect transistors. The sense field effect transistors are small field effect transistors separate from the main power field effect transistors. The sensing field effect transistor is generally configured to generate a voltage corresponding to the current in the main field effect transistor in order to provide current sensing, and may be integrated into the same semiconductor chip as the main field effect transistor.

目前,厂商希望能够将监测电流的精度进一步提高。这需要将感测场效应晶体管内的电流进一步缩小,以便增大采样电阻,提高精准度,同时还可以减少能量的浪费。At present, manufacturers hope to further improve the accuracy of monitoring current. This needs to further reduce the current in the sensing field effect transistor, so as to increase the sampling resistance, improve the accuracy, and reduce the waste of energy.

发明内容SUMMARY OF THE INVENTION

本发明的目的在于克服现有技术中存在的不足,提供一种可以提高监测电流精度的功率半导体器件。The purpose of the present invention is to overcome the deficiencies in the prior art, and to provide a power semiconductor device that can improve the accuracy of monitoring current.

按照本发明提供的技术方案,一种感测功率半导体器件,包括:According to the technical solution provided by the present invention, a sensing power semiconductor device includes:

主晶体管,其具有第一电流路径,电流从漏极焊盘流经主晶体管的第一漏极金属、第一源极金属,最后进入第一源极焊盘;a main transistor, which has a first current path, and the current flows from the drain pad through the first drain metal and the first source metal of the main transistor, and finally enters the first source pad;

副晶体管,其具有第二电流路径,用于监测第一电流路径中的电流,电流从漏极焊盘流经副晶体管的第二漏极金属、第二源极金属,最后进入第一源极焊盘;A secondary transistor with a second current path for monitoring the current in the first current path, the current flows from the drain pad through the second drain metal, the second source metal of the secondary transistor, and finally enters the first source pad;

感测晶体管,其具有第三电流路径,用于监测第二电流路径中的电流,电流从漏极焊盘流经感测晶体管的第三漏极金属、第三源极金属,最后进入第二源极焊盘;a sense transistor having a third current path for monitoring current in the second current path, the current flows from the drain pad through the third drain metal, the third source metal of the sense transistor, and finally into the second source pad;

测温二极管,其具有第四电流路径,用于监测功率半导体的芯片温度,电流从正极焊盘流经测温二极管的正极金属、负极金属,最后进入漏极焊盘。The temperature measuring diode has a fourth current path for monitoring the chip temperature of the power semiconductor, and the current flows from the anode pad through the anode metal and the cathode metal of the temperature measuring diode, and finally enters the drain pad.

进一步地,主晶体管的第一漏极金属、副晶体管的第二漏极金属、感测晶体管的第三漏极金属、测温二极管的负极金属和漏极焊盘彼此电耦合;主晶体管的第一源极金属、副晶体管的第二源极金属和第一源极焊盘彼此电耦合;感测晶体管的第三源极金属通过第一金属连接线和第二源极焊盘彼此电耦合;测温二极管的正极金属通过第二金属连接线和正极焊盘彼此电耦合;主晶体管的第一栅极金属和第一栅极焊盘彼此电耦合;副晶体管的第二栅极金属、感测晶体管的第三栅极金属和第二栅极焊盘彼此电耦合。Further, the first drain metal of the main transistor, the second drain metal of the sub transistor, the third drain metal of the sensing transistor, the negative metal of the temperature measuring diode and the drain pad are electrically coupled to each other; A source metal, the second source metal of the secondary transistor and the first source pad are electrically coupled to each other; the third source metal of the sensing transistor is electrically coupled to each other through the first metal connection line and the second source pad; The anode metal of the temperature measuring diode is electrically coupled to each other through the second metal connection line and the anode pad; the first gate metal and the first gate pad of the main transistor are electrically coupled to each other; the second gate metal of the secondary transistor, the sensing The third gate metal and the second gate pad of the transistor are electrically coupled to each other.

进一步地,主晶体管与副晶体管的源极区面积之比为n:1,所述n的范围为1<n≤1000;副晶体管与感测晶体管的源极区面积之比为m:1,所述m的范围为1<m≤1000。Further, the ratio of the area of the source region of the main transistor to the sub-transistor is n:1, and the range of n is 1<n≤1000; the ratio of the area of the source region of the sub-transistor to the sensing transistor is m:1, The range of m is 1<m≦1000.

进一步地,所述主晶体管、副晶体管与感测晶体管有相同的功率半导体结构。Further, the main transistor, the auxiliary transistor and the sensing transistor have the same power semiconductor structure.

更进一步地,主晶体管包括:在所述漏极焊盘的上方设有第一导电类型衬底,在所述第一导电类型衬底的上方设有第一导电类型外延层,在所述第一导电类型外延层的表面设有第二导电类型体区,在所述第二导电类型体区的表面设有第一导电类型源区,在所述第二导电类型体区内设有第二导电类型源区,在所述第一导电类型源区的表面设有沟槽,所述沟槽穿透第一导电类型源区与第二导电类型体区,然后进入第一导电类型外延层内,所述沟槽呈条状互相平行且等间距分布,所述沟槽的侧壁与底部设有场氧层,所述场氧层包裹着屏蔽栅多晶硅,在所述屏蔽栅多晶硅顶部的两侧设有栅极多晶硅,所述栅极多晶硅通过栅氧层与第一导电类型源区、第二导电类型体区、第一导电类型外延层互相绝缘,在所述沟槽与第一导电类型源区的上方设有绝缘介质层,在所述绝缘介质层的上方设有第一源极金属,所述第一源极金属穿透绝缘介质层与第一导电类型源区、第二导电类型源区欧姆接触。Further, the main transistor includes: a first conductive type substrate is provided above the drain pad, a first conductive type epitaxial layer is provided above the first conductive type substrate, and a first conductive type epitaxial layer is provided above the first conductive type substrate. A second conductivity type body region is provided on the surface of a conductivity type epitaxial layer, a first conductivity type source region is provided on the surface of the second conductivity type body region, and a second conductivity type body region is provided in the second conductivity type body region A conductive type source region, a trench is provided on the surface of the first conductive type source region, the trench penetrates the first conductive type source region and the second conductive type body region, and then enters the first conductive type epitaxial layer , the trenches are parallel to each other and equally spaced in stripes, the sidewalls and the bottom of the trenches are provided with a field oxide layer, the field oxide layer wraps the shielding gate polysilicon, and the two sides on the top of the shielding gate polysilicon A gate polysilicon is provided on the side, and the gate polysilicon is insulated from the first conductivity type source region, the second conductivity type body region, and the first conductivity type epitaxial layer through the gate oxide layer, and is in the trench and the first conductivity type. An insulating dielectric layer is provided above the source region, a first source metal is provided above the insulating dielectric layer, and the first source metal penetrates the insulating dielectric layer and the first conductive type source region and the second conductive type source ohmic contact.

更进一步地,对于N型功率半导体器件,所述第一导电类型为N型,所述第二导电类型为P型;对于P型功率半导体器件,所述第一导电类型为P型,所述第二导电类型为N型。Further, for an N-type power semiconductor device, the first conductivity type is N-type, and the second conductivity type is P-type; for a P-type power semiconductor device, the first conductivity type is P-type, and the The second conductivity type is N-type.

进一步地,所述主晶体管的第一栅极金属环绕在所述功率半导体器件的外围;第一栅极金属通过通孔连接栅极多晶硅。Further, the first gate metal of the main transistor surrounds the periphery of the power semiconductor device; the first gate metal is connected to the gate polysilicon through a through hole.

进一步地,所述感测晶体管与测温二极管位于所述功率半导体器件的中心位置。Further, the sensing transistor and the temperature measuring diode are located at the center of the power semiconductor device.

相较于传统器件不存在副晶体管;本发明公开了一种感测功率半导体器件,其中的主晶体管具有第一电流路径,副晶体管具有第二电流路径,用于监测第一电流路径中的电流,感测晶体管具有第三电流路径,用于监测第二电流路径中的电流,最终感测晶体管能够间接监测第一电流路径中的电流;其中的测温二极管具有第四电流路径,用于监测功率半导体的芯片温度。Compared with the conventional device, there is no secondary transistor; the invention discloses a sensing power semiconductor device, wherein the primary transistor has a first current path, and the secondary transistor has a second current path for monitoring the current in the first current path , the sensing transistor has a third current path for monitoring the current in the second current path, and finally the sensing transistor can indirectly monitor the current in the first current path; wherein the temperature sensing diode has a fourth current path for monitoring Die temperature of power semiconductors.

本发明具有以下优点:The present invention has the following advantages:

1、本发明器件工作时流过副晶体管的电流对外工作,不会浪费流过副晶体管的电流。1. When the device of the present invention works, the current flowing through the sub-transistor works externally, and the current flowing through the sub-transistor will not be wasted.

2、本发明器件的感测晶体管需要的采样电流远小于传统器件,所以在采样上消耗的能量比较少。2. The sampling current required by the sensing transistor of the device of the present invention is much smaller than that of the traditional device, so the energy consumed in sampling is relatively small.

3、本发明可以使用阻值更大的采样电阻,提高采样精度。3. The present invention can use a sampling resistor with a larger resistance value to improve the sampling accuracy.

4、本发明器件集成了测温二极管,能够对器件的核心温度进行监控,保证器件在安全的范围内工作。4. The device of the present invention integrates a temperature measuring diode, which can monitor the core temperature of the device and ensure that the device works within a safe range.

附图说明Description of drawings

图1为本发明器件的电路结构示意图。FIG. 1 is a schematic diagram of the circuit structure of the device of the present invention.

图2为本发明器件的芯片表面结构示意图。FIG. 2 is a schematic diagram of the chip surface structure of the device of the present invention.

图3为本发明器件的功率半导体的元胞结构示意图。FIG. 3 is a schematic diagram of the cell structure of the power semiconductor of the device of the present invention.

具体实施方式Detailed ways

需要说明的是,在不冲突的情况下,本发明中的实施例及实施例中的特征可以相互结合。下面将参考附图并结合实施例来详细说明本发明。It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

为了使本领域技术人员更好地理解本发明方案,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分的实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都应当属于本发明保护的范围。In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments of some, but not all, of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

需要说明的是,本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换,以便这里描述的本发明的实施例。此外,术语“包括”和“具有”以及他们的任何变形,意图在于覆盖不排他的包括,例如,包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元,而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

实施例1;Embodiment 1;

一种感测功率半导体器件,如图1所示,包括:A sensing power semiconductor device, as shown in Figure 1, includes:

主晶体管1,其具有第一电流路径11,电流从漏极焊盘5流经主晶体管1的第一漏极金属15、第一源极金属16,最后进入第一源极焊盘8;The main transistor 1 has a first current path 11, and the current flows from the drain pad 5 through the first drain metal 15 and the first source metal 16 of the main transistor 1, and finally enters the first source pad 8;

副晶体管2,其具有第二电流路径12,用于监测第一电流路径11中的电流,电流从漏极焊盘5流经副晶体管2的第二漏极金属17、第二源极金属18,最后进入第一源极焊盘8;The secondary transistor 2 has a second current path 12 for monitoring the current in the first current path 11 , and the current flows from the drain pad 5 through the second drain metal 17 and the second source metal 18 of the secondary transistor 2 , and finally enter the first source pad 8;

感测晶体管3,其具有第三电流路径13,用于监测第二电流路径12中的电流,电流从漏极焊盘5流经感测晶体管3的第三漏极金属19、第三源极金属20,最后进入第二源极焊盘9;The sensing transistor 3 has a third current path 13 for monitoring the current in the second current path 12 , the current flows from the drain pad 5 through the third drain metal 19 , the third source electrode of the sensing transistor 3 The metal 20 finally enters the second source pad 9;

测温二极管4,其具有第四电流路径14,用于监测功率半导体的芯片温度,电流从正极焊盘10流经测温二极管4的正极金属22、负极金属21,最后进入漏极焊盘5。The temperature measuring diode 4 has a fourth current path 14 for monitoring the chip temperature of the power semiconductor. The current flows from the anode pad 10 through the anode metal 22 and the cathode metal 21 of the temperature measuring diode 4 , and finally enters the drain pad 5 .

如图2所示,主晶体管1的第一漏极金属15、副晶体管2的第二漏极金属17、感测晶体管3的第三漏极金属19、测温二极管4的负极金属21和漏极焊盘5彼此电耦合;主晶体管1的第一源极金属16、副晶体管2的第二源极金属18和第一源极焊盘8彼此电耦合;感测晶体管3的第三源极金属20通过第一金属连接线25和第二源极焊盘9彼此电耦合;测温二极管4的正极金属22通过第二金属连接线24和正极焊盘10彼此电耦合;主晶体管1的第一栅极金属23和第一栅极焊盘6彼此电耦合;副晶体管2的第二栅极金属27、感测晶体管3的第三栅极金属26和第二栅极焊盘7彼此电耦合。As shown in FIG. 2 , the first drain metal 15 of the main transistor 1 , the second drain metal 17 of the sub-transistor 2 , the third drain metal 19 of the sensing transistor 3 , the negative electrode metal 21 of the temperature measuring diode 4 and the drain metal The electrode pads 5 are electrically coupled to each other; the first source metal 16 of the main transistor 1 , the second source metal 18 of the secondary transistor 2 and the first source pad 8 are electrically coupled to each other; the third source of the sensing transistor 3 The metals 20 are electrically coupled to each other through the first metal connecting wire 25 and the second source pad 9; the anode metal 22 of the temperature measuring diode 4 is electrically coupled to each other through the second metal connecting wire 24 and the anode pad 10; A gate metal 23 and the first gate pad 6 are electrically coupled to each other; the second gate metal 27 of the sub-transistor 2, the third gate metal 26 and the second gate pad 7 of the sense transistor 3 are electrically coupled to each other .

主晶体管1与副晶体管2的源极区面积之比为100:1;副晶体管2与感测晶体管3的源极区面积之比为100:1。The ratio of the area of the source region of the main transistor 1 to the sub-transistor 2 is 100:1; the ratio of the area of the source region of the sub-transistor 2 to the sensing transistor 3 is 100:1.

所述主晶体管1、副晶体管2与感测晶体管3有相同的功率半导体结构,如图3所示,在所述漏极焊盘5的上方设有N型衬底28,在所述N型衬底28的上方设有N型外延层29,在所述N型外延层的表面设有P型体区35,在所述P型体区35的表面设有N型源区37,在所述P型体区35内设有P型源区36,在所述N型源区37的表面设有沟槽30,所述沟槽30穿透N型源区37与P型体区35,然后进入N型外延层29内,所述沟槽30呈条状互相平行且等间距分布,所述沟槽30的侧壁与底部设有场氧层31,所述场氧层31包裹着屏蔽栅多晶硅32,在所述屏蔽栅多晶硅32顶部的两侧设有栅极多晶硅33,所述栅极多晶硅33通过栅氧层34与N型源区37、P型体区35、N型外延层29互相绝缘,在所述沟槽30与N型源区37的上方设有绝缘介质层38,在所述绝缘介质层38的上方设有第一源极金属16,所述第一源极金属16穿透绝缘介质层38与N型源区37、第二导电类型源区36欧姆接触。The main transistor 1 , the sub transistor 2 and the sensing transistor 3 have the same power semiconductor structure. As shown in FIG. 3 , an N-type substrate 28 is provided above the drain pad 5 . An N-type epitaxial layer 29 is provided above the substrate 28, a P-type body region 35 is provided on the surface of the N-type epitaxial layer, and an N-type source region 37 is provided on the surface of the P-type body region 35. The P-type body region 35 is provided with a P-type source region 36, and a trench 30 is provided on the surface of the N-type source region 37, and the trench 30 penetrates the N-type source region 37 and the P-type body region 35. Then enter the N-type epitaxial layer 29, the trenches 30 are parallel to each other in stripes and distributed at equal intervals, the sidewalls and the bottom of the trenches 30 are provided with a field oxide layer 31, and the field oxide layer 31 wraps the shielding The gate polysilicon 32 is provided with gate polysilicon 33 on both sides of the top of the shielded gate polysilicon 32. The gate polysilicon 33 is connected to the N-type source region 37, the P-type body region 35, and the N-type epitaxial layer through the gate oxide layer 34. 29 are insulated from each other, an insulating dielectric layer 38 is provided above the trench 30 and the N-type source region 37, and a first source metal 16 is provided above the insulating dielectric layer 38, and the first source metal 16 penetrates through the insulating medium layer 38 and is in ohmic contact with the N-type source region 37 and the second-conductivity-type source region 36 .

所述感测晶体管3与测温二极管4位于所述功率半导体器件的中心位置;由于功率半导体器件中心位置的电流最为均匀,因此感测晶体管3配置于该位置可以提高电流检测精度;测温二极管4位于所述功率半导体器件的中心位置,也可以提高温度检测精度;The sensing transistor 3 and the temperature measuring diode 4 are located at the center of the power semiconductor device; since the current at the center of the power semiconductor device is the most uniform, the sensing transistor 3 can be arranged at this position to improve the current detection accuracy; the temperature measuring diode 4 is located in the center of the power semiconductor device, which can also improve the temperature detection accuracy;

所述主晶体管1的第一栅极金属23环绕在所述功率半导体器件的外围;以方便实现第一栅极金属23与栅极多晶硅33的连接,第一栅极金属23通过通孔连接栅极多晶硅33。The first gate metal 23 of the main transistor 1 surrounds the periphery of the power semiconductor device; in order to facilitate the connection between the first gate metal 23 and the gate polysilicon 33, the first gate metal 23 is connected to the gate through a through hole Very polysilicon 33.

最后所应说明的是,以上具体实施方式仅用以说明本发明的技术方案而非限制,尽管参照实例对本发明进行了详细说明,本领域的普通技术人员应当理解,可以对本发明的技术方案进行修改或者等同替换,而不脱离本发明技术方案的精神和范围,其均应涵盖在本发明的权利要求范围当中。Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be Modifications or equivalent substitutions without departing from the spirit and scope of the technical solutions of the present invention should be included in the scope of the claims of the present invention.

Claims (5)

1.一种感测功率半导体器件,其特征在于,包括:1. A sensing power semiconductor device, characterized in that, comprising: 主晶体管(1),其具有第一电流路径(11),电流从漏极焊盘(5)流经主晶体管(1)的第一漏极金属(15)、第一源极金属(16),最后进入第一源极焊盘(8);A main transistor (1) having a first current path (11), current flowing from a drain pad (5) through a first drain metal (15), a first source metal (16) of the main transistor (1) , and finally enter the first source pad (8); 副晶体管(2),其具有第二电流路径(12),用于监测第一电流路径(11)中的电流,电流从漏极焊盘(5)流经副晶体管(2)的第二漏极金属(17)、第二源极金属(18),最后进入第一源极焊盘(8);A secondary transistor (2) having a second current path (12) for monitoring the current in the first current path (11), the current flowing from the drain pad (5) through the second drain of the secondary transistor (2) The electrode metal (17), the second source metal (18), and finally enter the first source pad (8); 感测晶体管(3),其具有第三电流路径(13),用于监测第二电流路径(12)中的电流,电流从漏极焊盘(5)流经感测晶体管(3)的第三漏极金属(19)、第三源极金属(20),最后进入第二源极焊盘(9);A sensing transistor (3) having a third current path (13) for monitoring the current in the second current path (12), the current flowing from the drain pad (5) through the third current path of the sensing transistor (3) Three drain metal (19), third source metal (20), and finally enter the second source pad (9); 测温二极管(4),其具有第四电流路径(14),用于监测功率半导体的芯片温度,电流从正极焊盘(10)流经测温二极管(4)的正极金属(22)、负极金属(21),最后进入漏极焊盘(5);A temperature measuring diode (4), which has a fourth current path (14) for monitoring the chip temperature of the power semiconductor, the current flows from the anode pad (10) through the anode metal (22) and the cathode of the temperature measuring diode (4) Metal (21), which finally enters the drain pad (5); 主晶体管(1)的第一漏极金属(15)、副晶体管(2)的第二漏极金属(17)、感测晶体管(3)的第三漏极金属(19)、测温二极管(4)的负极金属(21)和漏极焊盘(5)彼此电耦合;主晶体管(1)的第一源极金属(16)、副晶体管(2)的第二源极金属(18)和第一源极焊盘(8)彼此电耦合;感测晶体管(3)的第三源极金属(20)通过第一金属连接线(25)和第二源极焊盘(9)彼此电耦合;测温二极管(4)的正极金属(22)通过第二金属连接线(24)和正极焊盘(10)彼此电耦合;主晶体管(1)的第一栅极金属(23)和第一栅极焊盘(6)彼此电耦合;副晶体管(2)的第二栅极金属(27)、感测晶体管(3)的第三栅极金属(26)和第二栅极焊盘(7)彼此电耦合;The first drain metal (15) of the main transistor (1), the second drain metal (17) of the secondary transistor (2), the third drain metal (19) of the sensing transistor (3), the temperature measuring diode ( 4) The negative metal (21) and the drain pad (5) are electrically coupled to each other; the first source metal (16) of the main transistor (1), the second source metal (18) of the secondary transistor (2) and The first source pads (8) are electrically coupled to each other; the third source metal (20) of the sense transistor (3) is electrically coupled to each other through the first metal connection line (25) and the second source pad (9) ; the anode metal ( 22 ) of the temperature measuring diode ( 4 ) are electrically coupled to each other through the second metal connecting line ( 24 ) and the anode pad ( 10 ); the first gate metal ( 23 ) of the main transistor ( 1 ) and the first The gate pads (6) are electrically coupled to each other; the second gate metal (27) of the secondary transistor (2), the third gate metal (26) of the sense transistor (3) and the second gate pad (7) ) are electrically coupled to each other; 主晶体管(1)与副晶体管(2)的源极区面积之比为n:1,所述n的范围为1<n≤1000;副晶体管(2)与感测晶体管(3)的源极区面积之比为m:1,所述m的范围为1<m≤1000;The ratio of the area of the source region of the main transistor (1) to the sub-transistor (2) is n:1, and the range of n is 1<n≤1000; the source of the sub-transistor (2) and the sensing transistor (3) The area ratio is m:1, and the range of m is 1<m≤1000; 所述感测晶体管(3)与测温二极管(4)位于所述功率半导体器件的中心位置;The sensing transistor (3) and the temperature measuring diode (4) are located at the center of the power semiconductor device; 所述主晶体管(1)与副晶体管(2)设置在不同的区域中;The main transistor (1) and the auxiliary transistor (2) are arranged in different regions; 所述主晶体管(1)的第一源极金属(16)与副晶体管(2)的第二源极金属(18)分别设置在不同的源极区域中,感测晶体管(3)的第三源极金属(20)与测温二极管(4)的正极金属(22)位于所述功率半导体器件的中心位置。The first source metal (16) of the main transistor (1) and the second source metal (18) of the secondary transistor (2) are respectively arranged in different source regions, and the third source metal of the sensing transistor (3) The source metal (20) and the anode metal (22) of the temperature measuring diode (4) are located at the center of the power semiconductor device. 2.根据权利要求1所述的一种感测功率半导体器件,其特征在于,所述主晶体管(1)、副晶体管(2)与感测晶体管(3)有相同的功率半导体结构。2 . The sensing power semiconductor device according to claim 1 , wherein the main transistor ( 1 ), the secondary transistor ( 2 ) and the sensing transistor ( 3 ) have the same power semiconductor structure. 3 . 3.根据权利要求2所述的一种感测功率半导体器件,其特征在于,3. A sensing power semiconductor device according to claim 2, wherein, 主晶体管(1)包括:The main transistor (1) includes: 在所述漏极焊盘(5)的上方设有第一导电类型衬底(28),在所述第一导电类型衬底(28)的上方设有第一导电类型外延层(29),在所述第一导电类型外延层的表面设有第二导电类型体区(35),在所述第二导电类型体区(35)的表面设有第一导电类型源区(37),在所述第二导电类型体区(35)内设有第二导电类型源区(36),在所述第一导电类型源区(37)的表面设有沟槽(30),所述沟槽(30)穿透第一导电类型源区(37)与第二导电类型体区(35),然后进入第一导电类型外延层(29)内,所述沟槽(30)呈条状互相平行且等间距分布,所述沟槽(30)的侧壁与底部设有场氧层(31),所述场氧层(31)包裹着屏蔽栅多晶硅(32),在所述屏蔽栅多晶硅(32)顶部的两侧设有栅极多晶硅(33),所述栅极多晶硅(33)通过栅氧层(34)与第一导电类型源区(37)、第二导电类型体区(35)、第一导电类型外延层(29)互相绝缘,在所述沟槽(30)与第一导电类型源区(37)的上方设有绝缘介质层(38),在所述绝缘介质层(38)的上方设有第一源极金属(16),所述第一源极金属(16)穿透绝缘介质层(38)与第一导电类型源区(37)、第二导电类型源区(36)欧姆接触。A first conductive type substrate (28) is provided above the drain pad (5), a first conductive type epitaxial layer (29) is provided above the first conductive type substrate (28), A second conductivity type body region (35) is provided on the surface of the first conductivity type epitaxial layer, a first conductivity type source region (37) is provided on the surface of the second conductivity type body region (35), A second conductivity type source region (36) is provided in the second conductivity type body region (35), a trench (30) is provided on the surface of the first conductivity type source region (37), and the trench (30) penetrate the first conductivity type source region (37) and the second conductivity type body region (35), and then enter the first conductivity type epitaxial layer (29), the trenches (30) are parallel to each other in the shape of stripes and are equally spaced, the sidewalls and bottom of the trench (30) are provided with a field oxide layer (31), the field oxide layer (31) wraps the shielding gate polysilicon (32), and the shielding gate polysilicon ( 32) Gate polysilicon (33) is provided on both sides of the top, and the gate polysilicon (33) is connected to the first conductivity type source region (37) and the second conductivity type body region (35) through the gate oxide layer (34) , the first conductivity type epitaxial layers (29) are insulated from each other, an insulating medium layer (38) is provided above the trench (30) and the first conductivity type source region (37), and the insulating medium layer (38) ) is provided with a first source metal (16), the first source metal (16) penetrates the insulating dielectric layer (38) and the first conductivity type source region (37), the second conductivity type source region ( 36) Ohmic contact. 4.根据权利要求3所述的一种感测功率半导体器件,其特征在于,4. A sensing power semiconductor device according to claim 3, characterized in that, 对于N型功率半导体器件,所述第一导电类型为N型,所述第二导电类型为P型;对于P型功率半导体器件,所述第一导电类型为P型,所述第二导电类型为N型。For an N-type power semiconductor device, the first conductivity type is N-type, and the second conductivity type is P-type; for a P-type power semiconductor device, the first conductivity type is P-type, and the second conductivity type is P-type for the N type. 5.根据权利要求3所述的一种感测功率半导体器件,其特征在于,5. A sensing power semiconductor device according to claim 3, characterized in that, 所述主晶体管(1)的第一栅极金属(23)环绕在所述功率半导体器件的外围;第一栅极金属(23)通过通孔连接栅极多晶硅(33)。The first gate metal (23) of the main transistor (1) surrounds the periphery of the power semiconductor device; the first gate metal (23) is connected to the gate polysilicon (33) through a through hole.
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