CN113098516B

CN113098516B - Staggered ADC ping-pong pre-sampling holding buffer

Info

Publication number: CN113098516B
Application number: CN202110241518.4A
Authority: CN
Inventors: 郭啸峰; 陈润; 陈振骐; 陈勇刚
Original assignee: Shenzhen Nuoruixin Technology Co ltd
Current assignee: Shenzhen Nuoruixin Technology Co ltd
Priority date: 2021-03-04
Filing date: 2021-03-04
Publication date: 2022-11-15
Anticipated expiration: 2041-03-04
Also published as: CN113098516A

Abstract

The invention relates to a ping-pong pre-sampling hold buffer of an interleaved ADC (analog to digital converter), belonging to the technical field of analog to digital converter circuits in integrated circuit design. The buffer comprises a pre-sample-and-hold buffer circuit of a ping-pong architecture and a ping-pong clock generation circuit in a signal link; the circuit of the pre-sampling holding buffer consists of a first-stage emitter-stage following isolator, a pre-sampling holding circuit and a second-stage source-stage following isolator; the ping-pong clock generating circuit consists of a reset signal phase shift circuit and two frequency dividers which are mirror images of each other. The invention has the advantage that the classical pre-sampling holding buffer does not need to additionally calibrate the sampling delay error of the sub-channel ADC, and simultaneously reduces the speed requirement of the pre-sampling holding buffer by one time by utilizing a ping-pong architecture, thereby realizing more conciseness and robustness and having much lower realization cost.

Description

Staggered ADC ping-pong pre-sampling holding buffer

Technical Field

The invention belongs to the technical field of analog-to-digital converter (ADC) circuits in integrated circuit design, and particularly relates to a ping-pong pre-sampling hold buffer of an interleaved ADC (multichannel time-interleaved ADC).

Background

Interleaved analog-to-digital converter (ADC) architectures are generally suitable for high-speed high-precision ADC applications such as 5G rf chips, ultra-wideband receivers, phased array radars, electronic warfare and the like. The conversion accuracy requirements for ADCs for these scenarios are typically above 12 bits, while the sampling rate requirements reach several GSPS. For an ADC with high sampling rate and high linearity requirement, a buffer with high driving capability is needed to isolate an ADC sampling capacitor and a sampling switch, and the stray-free dynamic range (SFDR) of the system is improved by injecting a peak to a pre-stage anti-aliasing filter (or a transformer coupling front end) during sampling. Meanwhile, due to the large delay error of the sampling clock between the sub-channel ADCs of the interleaved ADC, the error may cause the actual sampling signal of each sub-channel ADC to generate a sampling error related to the delay error and the signal, which may ultimately greatly limit the signal-to-noise-and-distortion ratio (SNDR) of the interleaved ADC. At present, two schemes are used to solve the limitation of the delay error, the first scheme is to eliminate the delay error between the sub-channels by an extra heavy and complex calibration circuit, and the implementation cost of the delay error requirement of several 10fs stages is very high. The second scheme is that a pre-sampling holding buffer is used for sampling, holding and converting an input signal which changes at a high speed into a fixed level step signal, even if a certain amount of delay error exists between the sub-channel ADCs, the sampling error between the sub-channel ADCs cannot be caused finally, and therefore the requirement on the delay error is relaxed.

For the pre-sample-and-hold buffer architecture of a classical interleaved analog-to-digital converter (for example, for an interleaved ADC with four sub-channel ADCs), the system architecture is shown in fig. 1, and comprises two buffers, a full-rate pre-sample-and-hold circuit composed of a cascade of a sample switch SW and a sample-and-hold capacitor Cs in a dashed box. The input signal is connected with the input end of the buffer 1, and the buffer 1, the sample hold circuit and the buffer 2 are cascaded in sequence. The input end of the buffer 2 is respectively connected with the sub-channel ADC1, the sub-channel ADC2, the sub-channel ADC3 and the sub-channel ADC4. The clock timing of the pre-sample-hold and sub-channel sample-hold is shown in fig. 2, the sampling frequency of the sample-hold circuit is Fs, the sampling frequency of the four sub-channel ADCs is Fs/4, and the phases of their sampling clocks are 0 °,90 °,180 ° and 270 °, respectively (the sampling rate Fs/4 of the sub-channel ADC is one cycle). The working principle of the sampling circuit is as shown in fig. 3, a full-rate sampling and holding circuit with the sampling frequency of Fs is used for firstly holding the sampling of the changed input signal, in the holding stage, the signal is a fixed level, and the four sub-channel ADCs respectively complete the sampling in four continuous holding stages of the sampling and holding circuit in phases of 0 °,90 °,180 ° and 270 ° in sequence, and the sampling rate and the conversion rate of each sub-channel ADC are improved by 4 times in the time interleaving sampling mode. Because the sampling of each sub-channel ADC all occurs in the holding stage of the sample-hold circuit, when the sampling clock of the sub-channel ADC has a certain amount of delay error, the final sampling error can not be caused. As shown in fig. 3, which is an exemplary diagram of the operation principle of the pre-sampling and holding buffer, the sine wave signal of the upper half is the input signal, and the waveform of the lower half is the pre-sampling and holding signal, which is the sampling and holding signal based on the sampling and holding capacitor lower plate sampling architecture. The method specifically comprises two stages of sampling and holding, wherein in the sampling stage, signals are turned to an upper electrode plate after sampling is finished on a lower electrode plate of a sampling and holding capacitor, and in the holding stage, the signals are held on the upper electrode plate and do not change. For the interleaved ADC of this classical pre-sample and hold buffer architecture, no extra calibration circuit is generally needed to calibrate the sample clock delay error between the sub-channels, but it is very demanding for the pre-sample and hold circuit. Taking a 5GSPS12bit adc as an example, the above architecture requires a pre-sampling hold circuit and buffer with the same 5GSPS sampling rate and 12bit precision, which cannot be realized for non-advanced processes (below 28 nm) except for design optimization, which is a limit of process limit performance. The staggered ADC mainly based on the calibration of the sub-channel delay errors without adding a pre-sampling holding buffer can realize higher sampling rate by increasing the number of channels without excessively depending on the process.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a ping-pong pre-sampling holding buffer of an interleaved analog-to-digital converter, which has the advantage that the classic pre-sampling holding buffer does not need to additionally calibrate the sampling delay error of a sub-channel ADC (analog-to-digital converter), and simultaneously reduces the speed requirement of the pre-sampling holding buffer by one time by utilizing a ping-pong framework. Its advantages over conventional full-rate pre-sample-and-hold buffers are reduced requirements for pre-sample-and-hold buffers and the dependency of this type of architecture on advanced processes (below 28 nm). The realization is more concise and robust, and the realization cost is much lower.

The invention provides a ping-pong pre-sampling hold buffer of an interleaved ADC, which is used for the interleaved ADC with N sub-channel ADCs, wherein N is a positive integer of more than 2, and the buffer is characterized by comprising a pre-sampling hold buffer circuit with a ping-pong structure and a ping-pong clock generating circuit in a signal link;

the pre-sampling holding buffer circuit consists of a first-stage emitter-stage following isolator, a pre-sampling holding circuit and a second-stage source-stage following isolator; the first-stage emitter-stage following isolator consists of an NPN type triode and an initial current source; the pre-sampling holding circuit is a lower polar plate sampling circuit consisting of a first group of three sampling switches, a first sampling capacitor, a second group of three sampling switches and a second sampling capacitor which are mirrored; the second-stage source-level following isolator consists of a first NMOS tube, a first current source, a second NMOS tube and a second current source which are mirror images of the first NMOS tube and the first current source; the connection relationship is as follows: the base electrode of the NPN type triode is connected with the radio frequency signal input, the collector electrode of the NPN type triode is connected with the power supply, and the emitter electrode of the NPN type triode is connected to the ground through the initial current source; two transmission ends of a second switch in the first group of sampling switches are respectively connected with an emitting electrode of the NPN type triode and a lower polar plate of the first sampling capacitor, and a control end is connected with a first bootstrap clock of the first ping-pong clock; two transmission ends of a third switch in the first group of sampling switches are respectively grounded and a lower polar plate of the first sampling capacitor, and a control end is connected with an inverted clock of the first bootstrap clock; two transmission ends of a first switch in the first group of sampling switches are respectively connected with a power supply and an upper polar plate of a first sampling capacitor, and a control end is connected with a first ping-pong clock; the lower pole plate of the first sampling capacitor is connected with a second switch and a third switch in the first group of sampling switches, and the upper pole plate is connected with a first switch in the first group of sampling switches and is simultaneously connected with the grid electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with the upper polar plate of the first sampling capacitor, the drain electrode is connected with the power supply, the source electrode is connected to the ground through the first current source, and simultaneously the source electrode is connected with the interleaved ADC sub-channels ADC-1 and ADC-3, \ 8230 \ 8230, ADC-N-1 and odd-numbered channel ADCs; two transmission ends of a second switch in the second group of sampling switches are respectively connected with an emitting electrode of the NPN type triode and a lower polar plate of a second sampling capacitor, and a control end is connected with a second bootstrap clock of a second ping-pong clock; two transmission ends of a third switch in the second group of sampling switches are respectively grounded and a lower polar plate of a second sampling capacitor, and a control end is connected with a second bootstrap clock and a clock with the opposite phase thereof; two transmission ends of a first switch in the second group of sampling switches are respectively connected with a power supply and an upper polar plate of a second sampling capacitor, and a control end is connected with a second ping-pong clock; the lower pole plate of the second sampling capacitor is connected with a second switch and a third switch in the second group of sampling switches, and the upper pole plate is connected with a first switch in the second group of sampling switches and is simultaneously connected with the grid electrode of the second NMOS tube; the grid electrode of the second NMOS tube NMOS2 is connected with the upper polar plate of the second sampling capacitor Cs2, the drain electrode is connected with a power supply, and the source electrode passes through a current source;

the ping-pong clock generating circuit consists of a reset signal phase shift circuit and two frequency dividers which are mirror images of each other, wherein the reset signal phase shift circuit consists of two cascaded D-triggers, each frequency divider consists of a D-trigger with reset and an inverter, and the two frequency dividers are mirror images of each other; the connection relationship is as follows: an input signal D of the first D-trigger is connected with an initial reset signal, a trigger clock CK is connected with a main clock, and an output Q end outputs a first reset signal; an input signal D of the second D-trigger is connected with the first reset signal, a trigger clock CK is connected with the main clock, and an output end Q outputs a second reset signal; the output Q end of the first D-flip-flop with reset is connected with the input end of the first inverter, and the input D end is connected with the output end of the first inverter; the reset rst of the first two-frequency divider is connected with a first reset signal, and the trigger clock CK is connected with the output of the first delay unit; the output Q of the second D-trigger with reset is connected with the input of the second inverter, the input D is connected with the output of the second inverter, the reset rst of the second frequency divider is connected with the second reset signal, and the trigger clock CK is connected with the output of the first delay unit; the input of the first delay unit is connected with the main clock signal, and the output of the first delay unit is connected with the CK end clock input of the first frequency divider and the second frequency divider.

The invention has the characteristics and beneficial effects that:

(1) The structure provided by the invention is based on the mathematical symmetry of a ping-pong structure, the function of a full-rate pre-sampling holding buffer is realized by two physical layouts which are completely mirror-symmetrical, and ping-pong staggered half-rate pre-sampling holding buffers in time sequence, and compared with the conventional full-rate pre-sampling holding buffer, the structure has the advantages that the requirement on the pre-sampling holding buffer and the dependency of the type of architecture on an advanced process (below 28 nm) are reduced.

(2) For the realization of a ping-pong clock with extremely low phase error, the invention provides a double-initial-state frequency divider structure, the delay error of the double-initial-state frequency divider structure is only caused by the process mismatch between mirror image frequency dividers, the influence of the process deviation can be robustly eliminated by increasing the layout area (a plurality of standard unit frequency dividers are connected in parallel), and the specific expression is that the standard deviation of the delay error is reduced by one time when the standard unit of the frequency divider is increased by four times.

(3) For the implementation of the two-stage buffer, the invention provides a mixed structure combination of emitter follower (composed of NPN and a current source Ie) and source follower (composed of NMO1 and Ie1, and NMOS2 and Ie 2)

Drawings

Fig. 1 is a schematic diagram of a conventional pre-sample hold buffer architecture.

FIG. 2 is a diagram of an example of conventional pre-sample-and-hold and sub-channel sample-and-hold clock timing.

Fig. 3 is a schematic diagram illustrating the operation of a conventional pre-sample-and-hold buffer.

Fig. 4 is a circuit diagram of a ping-pong pre-sample-and-hold buffer of the present invention.

FIG. 5 is a diagram of an example of a ping-pong pre-sample-and-hold and sub-channel sample-and-hold clock timing of the present invention.

Fig. 6 is a schematic diagram of the operating principle of the ping-pong pre-sample hold buffer of the present invention.

Detailed Description

The ping-pong pre-sample hold buffer of interleaved ADC proposed by the present invention is described in detail below with reference to the accompanying drawings and embodiments:

the invention provides a ping-pong pre-sampling hold buffer of an interleaved ADC, which is composed of a pre-sampling hold buffer circuit with a ping-pong structure and a ping-pong clock generating circuit, as shown in FIG. 4, and is used for the interleaved ADC with N sub-channel ADCs, wherein N is a positive integer of more than 2. The input signal of the pre-sampling holding buffer circuit is a radio frequency signal input and is output to each sub-channel ADC, the input clock of the clock generating circuit is CLK, and the output clocks are CLK1 and CLK2. The two bootstrap clocks CLK1_ P, CLK2_ P and their inverted clocks CLK1_ Pb, CLK2_ Pb (CLK 1_ P, CLK2_ P and CLK1_ Pb, CLK2_ Pb are generated by CLK1 and CLK2, respectively, through a bootstrap peripheral circuit (which includes a bootstrap circuit and an inverter circuit, not shown in the figure).

The circuit of the pre-sampling holding buffer of the ping-pong structure in the signal link is composed of a first stage emitter stage following isolator, a pre-sampling holding circuit and a second stage source stage following isolator as shown in the upper half dotted line frame of fig. 4; the first emitter follower isolator is composed of an NPN type triode BJT tube NPN and an initial current source Ie (the BJT tube has stronger driving capability and higher linearity compared with an MOS tube, and the NPN type triode BJT has higher speed than the PNP type triode). The pre-sampling holding circuit comprises a first group of three sampling switches S1/SS1/SSS1, a first sampling capacitor Cs1, a second group of three sampling switches S2/SS2/SSS2 and a second sampling capacitor Cs2 which are mirrored, wherein SS1 is used as a switch for supplying power to an upper plate of Cs1 during sampling, a control signal of the S1 is CLK1, S1 is used as a switch for supplying a signal to a lower plate of Cs1 during sampling, a control signal of the S1 is a first clock CLK1_ P generated after CLK1 passes through a bootstrap circuit (bootstrap circuit is a common technology for improving the linearity of the switch by raising a high-level following signal of a clock at a control end of the switch), SSS1 is used as a switch for supplying the signal to the lower plate of Cs1 during sampling, and a control signal of the S1 is a first inverted clock CLK1_ Pb signal of the first bootstrap clock CLK1_ P. (for the bottom plate sampling structure, the specific sampling phase of the sample-and-hold signal is determined by the control clock phase of the top plate switch, i.e. by the two clocks CLK1 and CLK2, the two bootstrap clocks CLK1_ P/CLK2_ P and their inverted clocks CLK1_ Pb/CLK2_ Pb only affect the functional implementation). The second stage source stage following isolator consists of a first NMOS tube NMOS1 and a first current source Ie1, and a second NMOS tube NMOS2 and a second current source Ie2 which are mirror images of the first NMOS tube NMOS1 and the first current source Ie1 (the source stage follower is widely used as an isolator in a CMOS circuit, and the source stage following of the NMOS tube is stronger in driving capacity compared with a PMOS tube). The connection relationship is as follows: the base (b) of NPN type triode NPN is connected with radio frequency signal input, the collector (c) is connected with power supply, and the emitter (e) is connected to ground through initial current source Ie. Two transmission ends of a second switch SS1 in the first group of sampling switches are respectively connected with an emitting electrode of an NPN type triode NPN and a lower plate of a first sampling capacitor Cs1, and a control end is connected with a bootstrap clock CLK1_ P of the ping-pong clock CLK1. Two transmission ends of a third switch SSS1 in the first group of sampling switches are respectively grounded and the lower plate of a first sampling capacitor Cs1, and a control end is connected with a clock CLK1_ Pb which is the reverse phase of the first bootstrap clock CLK1_ P. Two transmission ends of a first switch S1 in the first group of sampling switches are respectively connected with a power supply and an upper polar plate of a first sampling capacitor Cs1, and a control end is connected with a ping-pong clock CLK1. The lower pole plate of the first sampling capacitor Cs1 is connected with a second switch SS1 and a third switch SSS1 in the first group of sampling switches, and the upper pole plate is connected with a first switch S1 in the first group of sampling switches and is simultaneously connected with the grid electrode of the first NMOS tube NMOS 1. The grid electrode of the NMOS1 is connected with the upper polar plate of the sampling capacitor Cs1, the drain electrode is connected with the power supply, the source electrode is connected to the ground through the first current source Ie1, and meanwhile, the source electrode is connected with the interleaved ADC subchannels ADC-1, ADC-3, \ 8230 \ 8230, ADC-N-1 and other odd-numbered channel ADCs. Two transmission ends of a second switch SS2 in the second group of sampling switches are respectively connected with an emitting electrode of an NPN type triode NPN and a lower pole plate of a second sampling capacitor Cs2, and a second bootstrap clock CLK2_ P of a second ping-pong clock CLK2 is connected with a control terminal; two transmission ends of a third switch SSS2 in the second group of sampling switches are respectively grounded and the lower plate of a second sampling capacitor Cs2, and control ends are connected with a second bootstrap clock CLK2_ P and an inverted clock CLK2_ Pb. Two transmission ends of a second switch S2 in the second group of sampling switches are respectively connected with a power supply and an upper polar plate of a second sampling capacitor Cs2, and a control end is connected with a second ping-pong clock CLK2. The lower pole plate of the second sampling capacitor Cs2 is connected with a second switch SS2 and a third switch SSS2 in the second group of sampling switches, and the upper pole plate is connected with a second switch S2 in the second group of sampling switches and is simultaneously connected with the grid electrode of a second NMOS transistor NMOS 2. The grid electrode of the second NMOS tube NMOS2 is connected with the upper polar plate of the second sampling capacitor Cs2, the drain electrode is connected with a power supply, the source electrode is connected to the ground through a current source Ie2, and meanwhile, the source electrode is connected with even-numbered channel ADCs such as sub-channel ADC-2, ADC-4, \ 8230 \ 8230, ADC-N and the like in the staggered ADC.

The structure provided by the invention is based on the mathematical symmetry of a ping-pong structure, the function of a full-rate pre-sampling holding buffer is realized by two physical layouts which are completely mirror-symmetrical, and ping-pong staggered half-rate pre-sampling holding buffers in time sequence, and compared with the conventional full-rate pre-sampling holding buffer, the structure has the advantages that the requirement on the pre-sampling holding buffer and the dependency of the type of architecture on an advanced process (below 28 nm) are reduced. In principle, a new error is introduced into the ping-pong pre-sampling holding buffer under the influence of process mismatch of a mirror-symmetric layout, the process mismatch which mainly influences the new error comprises mismatch of a used sampling metal finger capacitor (MoM capacitor) and mismatch of an MOS (metal oxide semiconductor) transistor, but the mismatches are in inverse proportion to the size of a device, and the influence of the process mismatch on the sampling precision of the ADC can be reduced to a required range by reasonably increasing the size of part of the circuit layout and symmetrical wiring connection. Due to the limitation of sampling KT/C noise (KT/C noise is a basic limiting condition of a sampling circuit, and a noise source generated by KT/C noise is current thermal noise of a sampling switch on-resistance, which is inversely proportional to a sampling capacitor in design), the layout sizes of the sampling MoM capacitors Cs1 and Cs2 need to be large enough to eliminate the influence of KT/C noise on an ADC signal-to-noise ratio (SNR), and the size is large enough to eliminate the influence of process mismatch, and meanwhile, the sampling switches S1/SS1/SSs1 and S2/SS2/SSs2 matched with the sampling capacitors, a bootstrap circuit (omitted in the figure) needs to be large enough layout sizes corresponding to the NPN serving as an emitter follower buffer and the NMOS1 and NMOS2 of a source follower buffer, and the size of the layout size of the circuit also needs to be large enough to eliminate the influence of process mismatch sampling precision, and generally no extra size is needed. The part needing to increase the size of the layout compared with the conventional circuit is the first frequency divider circuit and the second frequency divider circuit, and the power consumption and the area of the first frequency divider circuit and the second frequency divider circuit only account for the expense of a very small part of the system, so that the layout size of the circuit cannot be increased at a large cost. Compared with the method for eliminating the delay error (the requirement of 10fs level) by complicated calibration, the method for realizing the delay error of the high-speed and low-speed integrated circuit has the advantages that the realization is simpler, the robustness is realized, and the realization cost is much lower.

For the realization of the two-stage buffer, the invention provides a mixed structure combination of emitter follower (composed of NPN and a current source Ie) and source follower (composed of NMO1 and Ie1, and NMOS2 and Ie 2), which is realized by relying on a Bi-CMOS (process of fusing BJT and CMOS, which is a process provided by mainstream process manufacturers at present) process. An input stage following isolator is inserted between an input signal and a pre-sampling following circuit to meet the requirements of high driving capability and high linearity and ADC fixed input impedance, a source stage following isolator is inserted between an output signal and a pre-sampling holding circuit to meet the requirements of high driving capability and high linearity (due to the design of insertion loss effect and the overall linearity of a system, the linearity requirement of a rear-stage circuit is generally lower than that of a front-stage circuit), and meanwhile, because the grid stage of an NMOS (N-channel metal oxide semiconductor) tube hardly injects current, unlike the base stage of an NPN (negative-positive-negative) tube, the grid stage of the NMOS tube needs a certain injection current, the grid stage of the NMOS tube does not affect the holding of signals on a sampling capacitor. The two structures of emitter stage following and source stage following belong to the classic structure of isolators on textbooks.

The ping-pong clock generating circuit consists of a reset signal RST phase shifting circuit and two frequency dividers which are mirror images of each other. The reset signal RST is generated to be output by specific phase-shifting reset signals RST1 and RST2 through a reset signal RST phase-shifting circuit composed of two cascaded D-triggers, and the phase shift between the RST1 and the RST2 is larger than one clock period T and smaller than two clock periods 2T. Each frequency divider consists of a D-trigger with reset and an inverter, and the two frequency dividers are mirror circuits. The two-frequency division clocks output by the mirror two-frequency division circuit are perfectly 180 DEG phase-shifted from each other by phase-shifting the reset signal between T and 2T. The connection relationship is as follows: an input signal D of the first D-flip-flop is connected with a reset signal RST, a trigger clock CK is connected with a main clock CLK, and an output Q end outputs a first reset signal RST1. An input signal D of the second D-flip-flop is connected with a first reset signal RST1, a trigger clock CK is connected with a main clock CLK, and an output Q end outputs a second reset signal RST2; the output Q of the first D-flip-flop with reset is connected with the input of the first inverter, and the input D is connected with the output of the first inverter (the two are combined into a first frequency divider); the reset RST of the first two frequency dividers is connected with a first reset signal RST1, and the trigger clock CK is connected with the output of the first delay unit. The output Q of the second D-flip-flop with reset is connected with the input of the second inverter, the input D is connected with the output of the second inverter (the two inverters are combined into a second frequency divider), the reset RST of the second frequency divider is connected with the second reset signal RST2, and the trigger clock CK is connected with the output of the first delay unit. The input of the first delay unit is connected with the main clock signal, and the output of the first delay unit is connected with the CK end clock input of the first frequency divider and the second frequency divider.

According to the double initial state frequency divider structure, the reset signal RST1 with the phase shift of T + D (T is a main clock period, and D is D trigger delay) and the reset signal RST2 with the phase shift of 2 (T + D) are obtained by synchronizing the reset signal RST2 with the main clock CLK for 2 times, the two reset signals RST1 and RST2 with the phase shift of (T + D) are used for respectively resetting a frequency divider driven by the same main clock CLK, and due to the fact that the phase shift of the reset signal is larger than T, two initial state frequency divider outputs CLK1 and CLK2 can be obtained in a definite mode, and the phase shift between the two initial state frequency divider outputs is a perfect main clock period T. The mathematical interpretation is: after a clock with period T passes through a frequency divider with two times to generate a clock output with period 2T, if the phase of the reset signal is arbitrary, the phase shift is N x T (N epsilon Z), which depends on the phase of the reset signal, and they can converge to two states of 0 and T. The delay asymmetry and the delay error of the reset signal do not affect the delay error between the CLK1 and the CLK2, the delay error between the CLK1 and the CLK2 is only caused by the process mismatch between the mirror image frequency dividers, the influence of the process deviation can be robustly eliminated by increasing the layout area (a plurality of standard unit frequency dividers are connected in parallel), and the specific expression is that the standard deviation of the delay error is reduced by one time when the standard unit of the frequency divider is increased by four times.

For an N-channel interleaved ADC, if the number of channels N is 8, the ping-pong pre-sample hold clock timing and the sub-channel ADC sample hold clock timing diagram are shown in fig. 5. CLK1 and CLK2 are ping-pong two-half sampling clocks with a perfect phase shift of 180 °, CLK _ ADC1, CLK _ ADC2, \ 8230; \ 8230;, CLK _ ADC8 is an eight-divided sub-channel ADC sampling clock with a phase shift of 0 °,45 °,90 °,135 °,180 °,225 °,270 °,315 ° with some error. During the holding phase of the pre-sampling holding controlled by the clock CLK1, the CLK _ ADC3, the CLK _ ADC5 and the CLK _ ADC7 complete sampling, and during the holding phase of the pre-sampling holding controlled by the clock CLK2, the CLK _ ADC4, the CLK _ ADC6 and the CLK _ ADC8 complete sampling.

Fig. 6 is a schematic diagram illustrating the working principle of the present invention. The pre-sampling holding circuit samples and holds the changed input signals and then outputs signals with fixed level, the sampling of the sub-channel ADC is completely carried out in the holding stage, and the influence of sampling clock phase errors of the sub-channel ADC can be eliminated. The ping-pong pre-sampling holding structure uses the mirror circuit, and the sampling stage-ping and holding stage-pong and the sampling stage-pong and holding stage-ping are carried out simultaneously, so that the maximum bandwidth of the pre-sampling holding circuit can be doubled.

Claims

1. A ping-pong pre-sample hold buffer for an interleaved ADC having N sub-channel ADCs, N being a positive integer of 2 or more, the buffer comprising a ping-pong pre-sample hold buffer circuit and a ping-pong clock generation circuit in a signal chain;

the pre-sampling holding buffer circuit consists of a first-stage emitter-stage following isolator, a pre-sampling holding circuit and a second-stage source-stage following isolator; the first-stage emitter-stage following isolator consists of an NPN type triode and an initial current source; the pre-sampling holding circuit is a lower polar plate sampling circuit consisting of a first group of three sampling switches, a first sampling capacitor, a second group of three sampling switches and a second sampling capacitor which are mirrored; the second-stage source-level following isolator consists of a first NMOS tube, a first current source, a second NMOS tube and a second current source which are mirror images of the first NMOS tube and the first current source; the connection relationship is as follows: the base electrode of the NPN type triode is connected with the radio frequency signal input, the collector electrode of the NPN type triode is connected with the power supply, and the emitter electrode of the NPN type triode is connected to the ground through the initial current source; two transmission ends of a second switch in the first group of sampling switches are respectively connected with an emitting electrode of the NPN type triode and a lower polar plate of the first sampling capacitor, and a control end is connected with a first bootstrap clock of the first ping-pong clock; two transmission ends of a third switch in the first group of sampling switches are respectively grounded and a lower polar plate of the first sampling capacitor, and a control end is connected with an inverted clock of the first bootstrap clock; two transmission ends of a first switch in the first group of sampling switches are respectively connected with a power supply and an upper polar plate of a first sampling capacitor, and a control end is connected with a first ping-pong clock; the lower polar plate of the first sampling capacitor is connected with a second switch and a third switch in the first group of sampling switches, and the upper polar plate is connected with a first switch in the first group of sampling switches and is simultaneously connected with the grid electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with the upper polar plate of the first sampling capacitor, the drain electrode is connected with the power supply, the source electrode is connected to the ground through the first current source, and simultaneously the source electrode is connected with the interleaved ADC sub-channels ADC-1 and ADC-3, \ 8230 \ 8230, ADC-N-1 and odd-numbered channel ADCs; two transmission ends of a second switch in the second group of sampling switches are respectively connected with an emitting electrode of the NPN type triode and a lower polar plate of a second sampling capacitor, and a control end is connected with a second bootstrap clock of a second ping-pong clock; two transmission ends of a third switch in the second group of sampling switches are respectively grounded and a lower polar plate of a second sampling capacitor, and a control end is connected with a second bootstrap clock and an inverted clock thereof; two transmission ends of a first switch in the second group of sampling switches are respectively connected with a power supply and an upper polar plate of a second sampling capacitor, and a control end is connected with a second ping-pong clock; the lower pole plate of the second sampling capacitor is connected with a second switch and a third switch in the second group of sampling switches, and the upper pole plate is connected with a first switch in the second group of sampling switches and is simultaneously connected with the grid electrode of the second NMOS tube; the grid electrode of the second NMOS tube NMOS2 is connected with the upper polar plate of the second sampling capacitor Cs2, the drain electrode is connected with a power supply, and the source electrode passes through a current source;

the ping-pong clock generating circuit consists of a reset signal phase shift circuit and two dichotomous frequency dividers which are mirror images of each other, wherein the reset signal phase shift circuit consists of two cascaded D-triggers, each dichotomous frequency divider consists of a D-trigger with reset and an inverter, and the two dichotomous frequency dividers are mirror images of each other; the connection relationship is as follows: an input signal D of the first D-trigger is connected with an initial reset signal, a trigger clock CK is connected with a main clock, and an output Q end outputs a first reset signal; an input signal D of the second D-trigger is connected with the first reset signal, a trigger clock CK is connected with the main clock, and an output end Q outputs a second reset signal; the output Q end of the first D-flip-flop with reset is connected with the input end of the first inverter, and the input D end is connected with the output end of the first inverter; the reset rst of the first two-frequency divider is connected with a first reset signal, and the trigger clock CK is connected with the output of the first delay unit; the output Q of the second D-trigger with reset is connected with the input of the second inverter, the input D is connected with the output of the second inverter, the reset rst of the second frequency divider is connected with the second reset signal, and the trigger clock CK is connected with the output of the first delay unit; the input of the first delay unit is connected with the main clock signal, and the output of the first delay unit is connected with the CK end clock input of the first frequency divider and the second frequency divider.