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CN113113487A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN113113487A
CN113113487A CN202010032879.3A CN202010032879A CN113113487A CN 113113487 A CN113113487 A CN 113113487A CN 202010032879 A CN202010032879 A CN 202010032879A CN 113113487 A CN113113487 A CN 113113487A
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region
ohmic contact
conductivity type
layer
semiconductor device
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不公告发明人
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Sizhen Zhicheng Semiconductor Technology Shanghai Co ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions

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Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device is provided with the ohmic contact region and the diffusion region which are connected with each other, the diffusion region is close to the gate oxide layer and is in contact with the gate oxide layer relative to the ohmic contact region, and the doping concentration of the diffusion region is controlled to be smaller than that of the ohmic contact region, so that the effective grid voltage during short circuit can be effectively reduced, the saturation current is further reduced, and the short circuit time is prolonged. In addition, the invention reduces the lattice damage and improves the reliability of the gate oxide layer by arranging the diffusion region with low doping concentration.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method of manufacturing the same.
Background
Semiconductor devices are mainly large electronic devices used in power conversion and control circuits of power equipment, and metal oxide semiconductor field effect transistors ("MOSFETs"), which are well known semiconductor transistor types that can be used as switching devices in high applications, are common semiconductor devices. The MOSFET can be turned on or off by applying a gate bias to the gate electrode of the device. When the MOSFET is turned on (i.e., it is in its "on state"), current is conducted through the channel of the MOSFET. When the bias is removed from the gate electrode (or lowered below a threshold level), current stops conducting through the channel. For example, an n-type MOSFET is turned on when a gate bias sufficient to form a conductive n-type inversion layer in the p-type channel region of the device is applied. The n-type inversion layer electrically connects the n-type source and drain regions of the MOSFET, thereby allowing for majority carrier conduction therebetween.
Currently, semiconductor devices still need to be improved in terms of short-circuit time and TDDB reliability.
Disclosure of Invention
Therefore, the present invention is to solve the problem that the conventional semiconductor device still needs to be improved in short-circuit time and TDDB reliability, and further provides a semiconductor device and a method for manufacturing the same.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
the semiconductor device provided by the invention comprises:
a first conductive type semiconductor layer having a first conductive type;
a second conductivity type well region having a second conductivity type and disposed within the first conductivity type semiconductor layer;
the gate oxide layer is arranged on the first conduction type semiconductor layer and at least partially overlaps with the second conduction type well region;
the first conduction type region is arranged in the second conduction type well region and comprises an ohmic contact region and a diffusion region which are connected with each other, the doping concentration of the diffusion region is smaller than that of the ohmic contact region, and relative to the ohmic contact region, the diffusion region is close to the gate oxide layer and is in contact with the gate oxide layer.
Further, the doping concentration of the diffusion region is 1 × 1016cm-3—1×1018cm-3(ii) a The ohmic contact region has a doping concentration greater than 1 × 1016cm-3. For example, the doping concentration of the diffusion region is 1 × 1016cm-3—1×1017cm-3(ii) a The ohmic contact region has a doping concentration greater than 1 × 1017cm-3。
Further, the width H1 of the diffusion region is not less than 0.5 μm, and the width H2 of the ohmic contact region is 0.5 μm-5 μm.
Further, the dopant of the diffusion region is nitrogen or phosphorus; the dopant of the ohmic contact region is nitrogen or phosphorus.
The second conductive type region is arranged in the second conductive type well region, and is close to and in contact with the ohmic contact region;
and the ohmic contact part is arranged on the second conduction type well region and is connected with the second conduction type region and the ohmic contact region.
Further, the gate structure also comprises a gate electrode which is positioned on the gate oxide layer;
the insulating layer is arranged on the gate electrode and covers the gate electrode and the gate oxide layer;
and the source electrode is arranged on the insulating layer and is connected with the ohmic contact part.
Further, the first conductivity type semiconductor layer includes a substrate and a drift layer which are stacked in sequence, and the second conductivity type well region is disposed in the drift layer.
Optionally, the first conductivity type is an N type, and the second conductivity type is a P type; preferably, the substrate is N+A substrate, wherein the drift layer is an N drift layer, and the second conductivity type well region is P+The ohmic contact region is N+An ohmic contact region, the diffusion region being an N diffusion region, the second conductivity type region being a P+A conductive type region.
Optionally, the first conductivity type is a P type, and the second conductivity type is an N type; preferably, the substrate is P+A substrate, wherein the drift layer is a P drift layer, and the second conductivity type well region is N+The ohmic contact region is P+An ohmic contact region, the diffusion region being an N diffusion region, the second conductivity type region being N+A conductive type region.
Further, the semiconductor device further comprises a drain electrode which is arranged on one side of the substrate far away from the drift layer;
and the field limiting ring is arranged in the drift layer on one side of the drift layer far away from the substrate.
In addition, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a first conductive type semiconductor layer;
forming a second conductive type well region in the first conductive type semiconductor layer;
forming a first conductive type region in the second conductive type well region, wherein the first conductive type region comprises an ohmic contact region and a diffusion region which are connected with each other, and the doping concentration of the diffusion region is less than that of the ohmic contact region;
and forming a gate oxide layer on the first conductivity type semiconductor layer, wherein the gate oxide layer is at least partially overlapped with the second conductivity type well region, and relative to the ohmic contact region, the diffusion region is close to the gate oxide layer and is in contact with the gate oxide layer.
According to the semiconductor device provided by the invention, the ohmic contact region and the diffusion region which are connected with each other are arranged, the diffusion region is close to and in contact with the gate oxide layer relative to the ohmic contact region, and the doping concentration of the diffusion region is controlled to be smaller than that of the ohmic contact region, so that the effective voltage of the gate in short circuit can be effectively reduced, the saturation current is further reduced, and the short circuit time is prolonged. In addition, in the SiC semiconductor material, in order to obtain low N-type ohmic contact resistance, the doping concentration of an ohmic contact region is higher, which can cause extremely high lattice damage and worsen the Time-Dependent Dielectric Breakdown (TDDB) of a Dielectric layer of a gate oxide layer on the SiC semiconductor material.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic cross-sectional view of a MOSFET according to an embodiment of the present invention.
Fig. 2 is an enlarged schematic cross-sectional view of the second conductivity type well region of fig. 1.
Fig. 3 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present invention.
Description of reference numerals:
1-a first conductivity type semiconductor layer; 2-a second conductivity type well region; 3-a gate oxide layer; a 4-ohmic contact region; 5-a diffusion region; 6-a second type conductivity region; 7-a gate electrode; 8-an insulating layer; 9-a source electrode; 10-a drain electrode; 11-a substrate; 12-ohmic contact; 13-a protective layer; 14-field limiting ring; 15-drift layer.
Detailed Description
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled with" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled with" another element or layer, there are no intervening elements or layers present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout.
It will be understood that, although the terms first and second are used herein to describe various regions, layers and/or elements, these regions, layers and/or elements should not be limited by these terms. These terms are only used to distinguish one region, layer or element from another region, layer or element. Thus, a first region, layer or element discussed below could be termed a second region, layer or element, and similarly, a second region, layer or element may be termed a first region, layer or element without departing from the scope of the present invention.
Relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device on one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or an implant concentration gradient at its edges rather than a binary change from implanted to non-implanted region. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the present disclosure and relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It should be understood that the various embodiments disclosed herein may be combined. Thus, features depicted and/or described with respect to the first embodiment may equally be included in the second embodiment, and vice versa.
The description of some embodiments of the invention refers to semiconductor layers and/or regions characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration in the layer and/or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be assigned a "+" or "-" (e.g., n +, n-, p +, p-, n + +, n- -, p + +, p- -, etc.) to indicate a relatively large ("+") or small ("-") concentration of majority carriers relative to another layer or region. However, such notation does not imply the presence of a particular concentration of majority or minority carriers in a layer or region.
Fig. 1 is a schematic cross-sectional view of a MOSFET in an embodiment of the invention, as can be seen from fig. 1: the MOSFET includes a first conductivity type semiconductor layer 1 having a first conductivity type, for example, the first conductivity type is an N-type; a well region 2 of the second conductivity type, for example, the well region 2 of the second conductivity type is P+Well region, second conductorAn electric type is P type, disposed in the first conductive type semiconductor layer 1; a gate oxide layer 3 disposed on the first conductivity type semiconductor layer 1 and at least partially overlapping the second conductivity type well region 2; a first conductivity type region disposed in the second conductivity type well region 2 and including an ohmic contact region 4 and a diffusion region 5 connected to each other, wherein the doping concentration of the diffusion region 5 is less than that of the ohmic contact region 4, for example, the ohmic contact region 4 is N+And an ohmic contact region, wherein the diffusion region 5 is an N diffusion region, and the diffusion region 5 is close to and in contact with the gate oxide layer 3 relative to the ohmic contact region 4.
In the MOSFET, the ohmic contact region 4 and the diffusion region 5 which are connected with each other are arranged, the diffusion region 5 is close to the gate oxide layer 3 and is in contact with the gate oxide layer 4 relative to the ohmic contact region 4, and the doping concentration of the diffusion region 5 is controlled to be smaller than that of the ohmic contact region 4, so that the effective grid voltage during short circuit can be effectively reduced, the saturation current is further reduced, and the short circuit time is prolonged. In addition, in the SiC semiconductor material, in order to obtain a low N-type ohmic contact resistance, the doping concentration of the ohmic contact region 4 is high, which may cause extremely high lattice damage, deteriorating the Time-Dependent Dielectric Breakdown (TDDB) of the Dielectric layer of the gate oxide layer 3 thereon, and the present invention reduces the lattice damage and improves the reliability of the gate oxide layer 3 by providing the diffusion region 5 with a low doping concentration.
In some embodiments, the doping concentration of the diffusion region 5 is 1 × 1016cm-3—1×1018cm-3(ii) a The doping concentration of the ohmic contact region 4 is more than 1 x 1016cm-3This arrangement can reduce lattice damage.
As shown in fig. 2, in one embodiment, the width H1 of the diffusion region 5 is not less than 0.5 μm, and the width H2 of the ohmic contact region is 0.5 μm to 5 μm, which can reduce saturation current and increase short-circuit time.
In practical applications, the dopant of the diffusion region 5 is phosphorus or nitrogen; the dopant of the ohmic contact region 4 is phosphorus or nitrogen.
In the embodiment of the present invention, the second conductive type region 6 is further included, for example, the second conductive type region 6 is P+A conductive type region disposed in the second conductive type well region 2, and a second conductive type region 6 disposed adjacent to and in contact with the ohmic contact region 4; and an ohmic contact portion 12 disposed on the second conductive type well region 2 and connecting the second conductive type region 6 and the ohmic contact region 4.
In practical applications, the dopants of the second conductivity type well region 2 and the second conductivity type region 6 are aluminum or boron or gallium.
In one embodiment, the first conductivity type semiconductor layer 1 includes a substrate 11 and a drift layer 15 which are sequentially stacked, and the second conductivity type well region 2 is disposed in the drift layer 15; in this embodiment, the substrate is N+Substrate, e.g. N+And the drift layer is an N SiC drift layer.
As shown in fig. 1, in the embodiment of the present invention, a gate electrode 7 is further included, and is located on the gate oxide layer 3; an insulating layer 8 disposed on the gate electrode 7 and covering the gate electrode 7 and the gate oxide layer 3; a source electrode 9 disposed on the insulating layer 8 and connected to the ohmic contact 12; a drain 10 disposed on a side of the substrate 11 away from the drift layer 15, the drain 10 being specifically a P-doped SiC layer; a field limiting ring 14 disposed in the drift layer 15 at a side of the drift layer 15 away from the substrate 11, wherein the field limiting ring 14 is P heavily doped in the drift layer 15+And doping the region.
In order to better protect the drift layer 15, a protective layer 13 is provided on the drift layer 15 outside the source 9, in particular the protective layer 13 may be SiO2Layer or Si3N4Layers, and the like.
In another embodiment of the present invention, a semiconductor device includes a first conductivity type semiconductor layer 1 having a first conductivity type, for example, the first conductivity type is a P type, and more specifically, the first conductivity type semiconductor layer 1 includes a substrate 11 and a drift layer 15 which are sequentially stacked, and a second conductivity type well region 2 is disposed in the drift layer 15; in this embodiment, the substrate is P+Substrate, e.g. P+The drift layer is a P SiC drift layer; a second conductivity type well region 2 of a second conductivity type, for example, the second conductivity type well region 2 is an N-well region, and the second conductivity type is an N-type well region disposed at the first conductivity typeWithin the conductor layer 1; a gate oxide layer 3 disposed on the first conductivity type semiconductor layer 1 and at least partially overlapping the second conductivity type well region 2; a first conductivity type region disposed in the second conductivity type well region 2 and including an ohmic contact region 4 and a diffusion region 5 connected to each other, wherein the doping concentration of the diffusion region 5 is less than that of the ohmic contact region 4, for example, the ohmic contact region 4 is P+An ohmic contact region, the diffusion region 5 being an N diffusion region, the diffusion region 5 being adjacent to and in contact with the gate oxide layer 3 relative to the ohmic contact region 4, and a second conductivity type region 6, for example, the second conductivity type region 6 being P+And a conductivity type region disposed in the second conductivity type well region 2, and a second conductivity type region 6 disposed adjacent to and in contact with the ohmic contact region 4.
In addition, the present invention provides a method of manufacturing a semiconductor device, as shown in fig. 3, comprising:
providing a first conductive type semiconductor layer;
forming a second conductive type well region in the first conductive type semiconductor layer;
forming a first conductive type region in the second conductive type well region, wherein the first conductive type region comprises an ohmic contact region and a diffusion region which are connected with each other, and the doping concentration of the diffusion region is less than that of the ohmic contact region;
and forming a gate oxide layer on the first conductivity type semiconductor layer, wherein the gate oxide layer is at least partially overlapped with the second conductivity type well region, and relative to the ohmic contact region, the diffusion region is close to the gate oxide layer and is in contact with the gate oxide layer.
For example, taking the MOSFET structure in fig. 1 as an example, P can be formed by multiple ion implantations during the specific manufacturing process+The well region, the channel, the second conductivity type region 6, the ohmic contact region 4, and the diffusion region 5 may also be formed by ion implantation. The ion implantation energy, the implantation dose, and the temperature at the time of high-energy ion implantation are selected in accordance with the kind of the object to be implanted, and specifically, on the drift layer 15, a desired resist pattern is formed as a mask, and a P-type dopant, for example, boron ions are selectively ion-implanted from the opening of the resist maskTo P+The well region and the second type conductivity type region 6 can change the concentration of the P-type dopant in a gradual or abrupt manner, and the implantation depth is smaller than the thickness of the drift layer 15. After the implantation is completed, the mask is removed. Then, using the additionally formed desired resist pattern as a mask, selectively performing ion implantation of N-type dopants, such as phosphorus ions, from the openings of the resist mask to form the ohmic contact region 4 and the diffusion region 5, the concentration of the N-type dopants being changed in a gradual or abrupt manner, the depth of implantation being smaller than the depth of the drift layer 15; preferably, the ohmic contact region 4 is implanted with phosphorus and the diffusion region 5 is implanted with nitrogen, which sets the implantation process to be less damaging, which is beneficial to reduce saturation current and increase short-circuit time.
The first conductive type semiconductor layer preparation may form the drift layer 15 on the substrate 11 using epitaxial growth or ion implantation.
In addition, the P-type MOSFET device and the n-type MOSFET device can be mutually switched, the P-type IGBT and the n-type IGBT can be mutually switched, and the P-type MOSFET device, the n-type MOSFET device, the P-type IGBT and the n-type IGBT are all within the protection scope of the invention.
Although the foregoing embodiments have been described with reference to specific figures, it should be understood that some embodiments of the invention may include additional and/or intervening layers, structures, or elements, and/or may be deleted or omitted. Although a few exemplary embodiments of this invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of the present invention and that the invention is not to be considered limited to the specific embodiments disclosed and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The invention is defined by the following claims, with equivalents of the claims to be included therein.

Claims (11)

1.一种半导体器件，包括：1. A semiconductor device comprising: 第一导电类型半导体层，具有第一导电类型；a first conductivity type semiconductor layer having a first conductivity type; 第二导电类型阱区，具有第二导电类型，设置在所述第一导电类型半导体层内；A second conductivity type well region, having a second conductivity type, is disposed in the first conductivity type semiconductor layer; 栅氧化层，设置于所述第一导电类型半导体层上且与所述第二导电类型阱区至少部分重叠；a gate oxide layer, disposed on the first conductive type semiconductor layer and at least partially overlapping with the second conductive type well region; 第一导电类型区，设置于所述第二导电类型阱区内，其包括彼此连接的欧姆接触区和扩散区，所述扩散区的掺杂浓度小于所述欧姆接触区的掺杂浓度，相对于所述欧姆接触区，所述扩散区靠近所述栅氧化层且与其接触。The first conductive type region is disposed in the second conductive type well region, and includes an ohmic contact region and a diffusion region connected to each other, and the doping concentration of the diffusion region is smaller than that of the ohmic contact region, relative to the doping concentration of the ohmic contact region. In the ohmic contact region, the diffusion region is close to and in contact with the gate oxide layer. 2.根据权利要求1所述的半导体器件，其特征在于，所述扩散区的掺杂浓度为1×1016cm-3—1×1018cm-3；所述欧姆接触区的掺杂浓度大于1×1016cm-3。2 . The semiconductor device according to claim 1 , wherein the doping concentration of the diffusion region is 1×10 16 cm −3 to 1×10 18 cm −3 ; the doping concentration of the ohmic contact region is 1×10 16 cm −3 . 3 . More than 1×10 16 cm -3 . 3.根据权利要求1或2所述的半导体器件，其特征在于，所述扩散区的宽度H1不小于0.5μm，所述欧姆接触区的宽度H2为0.5μm-5μm。3 . The semiconductor device according to claim 1 , wherein the width H1 of the diffusion region is not less than 0.5 μm, and the width H2 of the ohmic contact region is 0.5 μm-5 μm. 4 . 4.根据权利要求1-3中任一项所述的半导体器件，其特征在于，所述扩散区的掺杂物为氮或磷；所述欧姆接触区的掺杂物为氮或磷。4 . The semiconductor device according to claim 1 , wherein the dopant of the diffusion region is nitrogen or phosphorus; and the dopant of the ohmic contact region is nitrogen or phosphorus. 5 . 5.根据权利要求1-4中任一项所述的半导体器件，其特征在于，还包括第二类导电类型区，设置于所述第二导电类型阱区内，且第二类导电类型区靠近所述欧姆接触区并与其接触设置；5. The semiconductor device according to any one of claims 1-4, further comprising a second conductivity type region disposed in the second conductivity type well region, and the second conductivity type region close to and in contact with the ohmic contact area; 欧姆接触部，设置于所述第二导电类型阱区上且连接所述第二类导电类型区与欧姆接触区。The ohmic contact portion is disposed on the second conductive type well region and connects the second conductive type region and the ohmic contact region. 6.根据权利要求1-5中任一项所述的半导体器件，其特征在于，还包括栅电极，位于所述栅氧化层上；6. The semiconductor device according to any one of claims 1-5, further comprising a gate electrode, located on the gate oxide layer; 绝缘层，设置于所述栅电极上，且覆盖所述栅电极和栅氧化层；an insulating layer, disposed on the gate electrode and covering the gate electrode and the gate oxide layer; 源极，设置于所述绝缘层上，并与所述欧姆接触部连接。The source electrode is arranged on the insulating layer and connected with the ohmic contact part. 7.根据权利要求1-6中任一项所述的半导体器件，其特征在于，所述第一导电类型半导体层包括依次层叠设置的衬底和漂移层，所述第二导电类型阱区设置于所述漂移层内。7 . The semiconductor device according to claim 1 , wherein the first conductive type semiconductor layer comprises a substrate and a drift layer that are stacked in sequence, and the second conductive type well region is provided in the drift layer. 8.根据权利要求7所述的半导体器件，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型；优选地，所述衬底为N+衬底，所述漂移层为N漂移层，所述第二导电类型阱区为P+阱区，所述欧姆接触区为N+欧姆接触区，所述扩散区为N扩散区，所述第二导电类型区为P+导电类型区。8. The semiconductor device according to claim 7, wherein the first conductivity type is N-type, and the second conductivity type is P-type; preferably, the substrate is an N + substrate, and the The drift layer is an N drift layer, the second conductivity type well region is a P + well region, the ohmic contact region is an N + ohmic contact region, the diffusion region is an N diffusion region, and the second conductivity type region is the P + conductivity type region. 9.根据权利要求7所述的半导体器件，其特征在于，所述第一导电类型为P型，所述第二导电类型为N型；优选地，所述衬底为P+衬底，所述漂移层为P漂移层，所述第二导电类型阱区为N+阱区，所述欧姆接触区为P+欧姆接触区，所述扩散区为N扩散区，所述第二导电类型区为N+导电类型区。9 . The semiconductor device according to claim 7 , wherein the first conductivity type is P-type, and the second conductivity type is N-type; preferably, the substrate is a P + substrate, and the The drift layer is a P drift layer, the second conductivity type well region is an N + well region, the ohmic contact region is a P + ohmic contact region, the diffusion region is an N diffusion region, and the second conductivity type region is the N + conductivity type region. 10.根据权利要求7-9中任一项所述的半导体器件，其特征在于，还包括漏极，设置于所述衬底远离所述漂移层的一侧上；10. The semiconductor device according to any one of claims 7 to 9, further comprising a drain, disposed on a side of the substrate away from the drift layer; 限场环，设置于所述漂移层远离所述衬底一侧的漂移层内。The field confinement ring is arranged in the drift layer on the side of the drift layer away from the substrate. 11.一种半导体器件的制备方法，包括：11. A preparation method of a semiconductor device, comprising: 提供第一导电类型半导体层；providing a first conductivity type semiconductor layer; 在所述第一导电类型半导体层内形成第二导电类型阱区；forming a second conductivity type well region in the first conductivity type semiconductor layer; 在第二导电类型阱区内形成第一导电类型区，其包括彼此连接的欧姆接触区和扩散区，所述扩散区的掺杂浓度小于所述欧姆接触区的掺杂浓度；A first conductive type region is formed in the second conductive type well region, which includes an ohmic contact region and a diffusion region connected to each other, and the doping concentration of the diffusion region is smaller than that of the ohmic contact region; 在第一导电类型半导体层上形成栅氧化层，所述栅氧化层与所述第二导电类型阱区至少部分重叠，且相对于所述欧姆接触区，所述扩散区靠近所述栅氧化层且与其接触。A gate oxide layer is formed on the first conductive type semiconductor layer, the gate oxide layer at least partially overlaps with the second conductive type well region, and the diffusion region is close to the gate oxide layer relative to the ohmic contact region and contact with it.
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