CN113128141B - Median filtering system based on error-free random calculation - Google Patents

Abstract

The invention discloses a median filter system based on error-free random calculation, which is applied to the field of digital image processing optimization design. Aiming at the problem of large resource consumption in the prior art, the median filter system of the invention includes: forward Conversion module, random comparator and backward conversion module; The forward conversion module includes a concentrated sequence generation unit and a uniform sequence generation unit, and the concentrated sequence generation unit and the uniform sequence generation unit are used to convert the binary signal into a uniform distribution sequence and a uniform sequence generation unit respectively. Centralized distribution sequence; the output end of the concentrated sequence generation unit is connected to the input end of the random comparator, the output end of the uniform sequence generation unit is connected to the selection end of the random comparator, and the output end of the random comparator is connected to the backward conversion module; the backward conversion The module converts the random sequence output by the random comparator into a binary value; the median filter of the present invention can be well applied to fields such as digital image median filtering and noise reduction.

Description

A Median Filtering System Based on Error-free Stochastic Calculation

technical field

The invention belongs to the field of digital image processing optimization design, in particular to a realization technology of a median filtering system.

Background technique

Due to the current requirements of high computing performance, small integrated area, and low power consumption of integrated circuits. With the continuous development of science and technology, the size of transistors is continuously reduced, and more and more transistors can be integrated on a unit area. However, with the invalidation of Dennard's scaling law, the field of computing has been challenged unprecedentedly. According to Moore's law, shrinking the size of the transistor will increase the leakage current, which will increase the power consumption of the integrated circuit, but the performance improvement is not ideal. The reliability of complex and sophisticated chips has become the most concerned issue for designers at this stage. This drives the development of new computing technologies.

In the digital circuit design of random computing, the commonly used forward conversion unit uses a linear feedback shift register (LFSR) to generate a random number source, set different initial values of the linear feedback shift register (LFSR), and the output of the forward conversion The sequence is different, not only can generate a pseudo-random bit stream, but also can well reduce the autocorrelation of the bit stream sequence itself, but each path of the random circuit needs to be driven by an independent initial random number, which will greatly increase Circuit area and resource occupation of the forward conversion unit.

Contents of the invention

In order to solve the above technical problems, the present invention proposes a median filter system based on error-free random calculation.

The technical solution adopted by the present invention is: a median filtering system based on error-free random calculation, including: a forward conversion module, a random comparator module and a backward conversion module;

The forward conversion module includes a concentrated sequence generation unit and a uniform sequence generation unit, and the concentrated sequence generation unit and the uniform sequence generation unit are used to convert the binary signal into a concentrated distribution sequence and a uniform distribution sequence, respectively;

The output end of the concentrated sequence generation unit is connected to the input end of the random comparator, the output end of the uniform sequence generation unit is connected to the selection end of the random comparator, and the output end of the random comparator is connected to the backward conversion module; the backward conversion module will randomly compare The random sequence output by the converter is converted into a binary value.

A clock cycle module is also included, and the clock cycle module and the forward conversion module share an up counter.

The generation process of described centralized distribution sequence is: compare the weighted binary number with the up counter value of current clock cycle, if greater than the up counter value of current clock cycle, then output bit stream is " 1 "; Otherwise output bit stream is " 0", since the current clock cycle is equal to the self-increment of 1 in the previous clock cycle, it can output "1" all at the head of the sequence, and the rest of the bits are "0" and the concentrated distribution sequence at the end of the sequence.

The generation process of the uniform sequence generation unit is as follows: the value of the up-counter in the current clock cycle and the binary complement of the value of the up-counter in the previous clock cycle are ANDed, and the output of each bit obtained is ANDed with each bit in the binary weighted number , the obtained outputs are respectively connected to OR gates, and finally a uniformly distributed sequence of weighted binary numbers is obtained.

Consists of three binary signals.

The random comparator module is a cascaded structure of three random comparators. Correspondingly, the three random comparators are sequentially recorded as the first random comparator, the second random comparator, and the third random comparator. The three binary signal The three concentrated sequences after the forward conversion module, two of which are used as the input of the first random comparator, and the larger output of the other concentrated sequence and the first random comparator is used as the input of the second random comparator. The smaller output of a random comparator and the smaller output of the second random comparator are used as the input of the third random comparator, the larger output of the second random comparator is used as the maximum sequence output of the random comparator module, and the third random comparator The larger output of the comparator is used as the median sequence output of the random comparator module, and the smaller output of the third random comparator is used as the minimum sequence output of the random comparator module; the uniform distribution sequence is used as the input of the selection terminal of the three random comparators .

A single random comparator includes: a first random comparison module, a stanh module, a second random comparison module, and a third random comparison module; two input terminals of the three random comparison modules are used as two input terminals of the random comparator, and the random The input of the two input terminals of the comparator is inverting, and the selection terminal of the first random comparison module is used as the selection terminal of the random comparator; the output terminal of the first random comparison module is connected to the input terminal of the stanh module, and the output terminal of the stanh module Respectively connect the second random comparison module and the selection end of the third random comparison module; the output of the second random comparison module is used as the larger output terminal of the random comparator, and the output of the third random comparison module is used as the comparison of the random comparator small output.

The stanh module is specifically a stanh function based on a finite state machine, specifically:

The conversion principle of the state transition diagram is: N states, namely S ₀ , S ₁ , ..., S _n-1 , X is the initial input value of the state machine, and the output Y is only related to the current state S _i , 0<i< N-1, if 0<i≤N/2-1, the output value Y=0; otherwise, the output value Y=1.

Beneficial effects of the present invention: random calculation is a representation of approximate or inaccurate calculation, the present invention can realize the error-free output result of the random comparator, and its structure includes a forward conversion module, a random comparator, a backward conversion module, The random comparator can be cascaded, the forward conversion module, the random comparator and the backward conversion module are sequentially connected in circuit, the input binary signal generates a uniform distribution sequence and a concentrated distribution sequence through a probability sequence generator, and the concentrated distribution sequence is used as a random The input terminal of the comparator, the uniform distribution sequence is used as the selection terminal of the random comparator, and the output terminal of the random comparator is connected to the backward conversion module to complete the conversion from random sequence to traditional binary value, and can be well applied to digital images Fields such as value filtering noise reduction; The median filtering system based on error-free random calculation of the present invention includes the following advantages:

1. The conversion unit based on the adding counter reduces cross-correlation through fixed probability distribution, and the improved random comparator model realizes random calculation results without inherent errors.

2. The clock cycle module can share an up counter with the forward conversion module to reduce resource consumption.

3. Realized the function that random calculation can be well applied in the fields of median filtering and noise reduction.

Description of drawings

Fig. 1 is the structural block diagram of median filtering system among the present invention;

Fig. 2 is a schematic diagram of a median filter 3*3 sliding window in the present invention;

Fig. 3 is a schematic diagram of the centralized sequence generation unit in the present invention;

Fig. 4 is a schematic diagram of a uniform sequence generation unit in the present invention;

Fig. 5 is the transfer diagram based on the finite state machine among the present invention;

Fig. 6 is a random comparator internal structure diagram among the present invention;

Fig. 7 is the random comparator cascade diagram among the present invention;

Fig. 8 is a diagram of the experimental results of the present invention applied to image median filtering;

Among them, Fig. 8(a) is the original image, Fig. 8(b) is the median filtering result realized by the traditional method, and Fig. 8(c) is the median filtering result realized based on random calculation.

Detailed ways

In order to facilitate those skilled in the art to understand the technical content of the present invention, the content of the present invention will be further explained below in conjunction with the accompanying drawings.

As shown in Fig. 1, a kind of median filtering system based on error-free random calculation of the present invention includes: a forward conversion module, a random comparator and a backward conversion module; The sequence generation unit is used to convert the binary signal into a centralized distribution sequence and a uniform distribution sequence respectively; the random comparator is used to output the maximum centralized distribution sequence and the minimum centralized distribution sequence; the backward conversion module is used to convert the output random sequence Convert back to a binary value.

The forward conversion unit in this embodiment uses a linear feedback shift register (LFSR) to generate a random number source, and different linear feedback shift register (LFSR) initial values are set, and the output sequence of the forward conversion is different, not only can A pseudo-random bit stream is generated, and the autocorrelation of the bit stream sequence itself can be well reduced.

As shown in Figure 2, the schematic diagram of the median filter 3*3 sliding window output value, when using software to implement, first compare the pixel values of each column (row), sorted according to the maximum value, median value and minimum value; then compare the maximum Take the minimum value in the column (row) of the value, take the middle value in the column (row) that compares the middle value, and take the maximum value in the column (row) that compares the minimum value; finally compare the three values in the previous step and take the middle value Value, this intermediate value is the statistical median value in the required window, as the output of the window, the specific example comparison process shown in Figure 2 is as follows:

Step 1 First compare the pixel values of each column, and sort {{50, 37, 19}, {98, 36, 24}, {80, 64, 23}} according to the maximum, median and minimum values;

Step 2 Then take the minimum value in the line with the maximum value, take the middle value in the line with the middle value, and take the maximum value in the line with the minimum value {min{50, 98, 80}, med{37, 36, 64}, max{ 19, 24, 23}};

In step 3, compare the three values obtained at the end, and take the middle value, which is the statistical median med{50, 37, 24} in the desired window, that is, the output value of the 37-bit window.

As shown in Figure 3, the centralized distribution sequence generation unit, the centralized distribution sequence unit compares the binary weighted number X[n-1:0] with the up counter value cnt of the current clock cycle, the reason why the up counter based The forward conversion unit can reduce the cross-correlation between sequences through the distribution of fixed probability, which can not only realize circuit multiplexing, but also reduce resource consumption. Moreover, the up counter in the forward conversion unit can also be shared with the up counter in the clock cycle module, so as to further improve the operating efficiency of the circuit. Wherein the up counter can be shared by all forward converters, if X>cnt, then the output bit stream is "1"; if X≤cnt, then the output bit stream is "0", because each clock cycle cnt=cnt+1 , so it can output "1" all at the head of the sequence, and the remaining bits are "0" and the centralized distribution sequence at the end of the sequence, for example, the number 5 to be converted, the 8-bit centralized distribution sequence 11111000 generated by the centralized conversion unit.

X[n-1:0] represents the binary sequence to be converted, and X represents the binary weighted number of n bits.

As shown in Figure 4, the uniformly distributed sequence generation unit, wherein the up counter is shared by all forward converters, the up counter value cnt of the current clock cycle, and the binary complement of the up counter value of the previous clock cycle, its The function acts as a rising edge detector, and the output of each bit obtained is respectively ANDed with the binary weighted number X[n-1:0], and the output is respectively connected to the OR gate, that is, the weighted binary number X[n-1:0] is obtained uniformly distributed series.

In FIG. 4, X ₀ , ..., Xi _i , ..., X _n-1 represent n bits in X[n-1:0] respectively.

As shown in Figure 5, the state transition diagram based on the finite state machine consists of a group of N states arranged in a linear form (saturation counter). Usually, N=2 ^K states are selected, where K is a positive integer, and the transition from the first state to the last state must be realized through successive transitions of all intermediate states. Wherein, the conversion principle of the state transition diagram is that N states are respectively S ₀ , S ₁ , ..., S _i , ..., S _N-1 , X is used as the initial input value of the state machine, and the output Y is only consistent with the current The state S _i has (0<i<N-1) off, if 0<i≤N/2-1, the output value Y=0; otherwise the output value Y=1, thus constructing a stanh based on a finite state machine function, on the basis of the existing model, the present invention not only realizes error-free calculation results by inputting concentratedly distributed A, B and uniformly distributed R, but also reduces the original number of states to only four states. Functions are realized, and the circuit area and resource occupation are greatly reduced.

进而得到，0≤P_X＜0.5时，P_Y＝0；P_X＝0.5时，P_Y＝1/2；0.5＜P_X≤1时，P_Y＝1。所以若A＞B，则P_X＞0.5，S＝1，stanh模块倾向于保持在高状态侧，最右边的数据器选择A；若A＜B，则P_X＜0.5，S＝0，stanh模块倾向于保持在低状态侧，最右边的数据选择器选择B，由此分别输出最大集中分布序列和最小集中分布序列。这里的S表示stanh模块的输出。As shown in Figure 6, the internal structure diagram of the random comparator, where A and B are the input terminals of the random comparator, which are concentrated distribution sequences, R is the selection terminal of the data selector, which is a uniform distribution sequence, and the generated random bit stream difference The value is sent to the stanh module, which can be seen from the configuration of the stanh module,

Furthermore, when 0≤P _X <0.5, P _Y =0; when P _X =0.5, P _Y =1/2; when 0.5<P _X ≤1, P _Y =1. So if A>B, then P _X >0.5, S=1, the stanh module tends to remain on the high state side, and the rightmost data device chooses A; if A<B, then P _X <0.5, S=0, stanh The module tends to remain on the low state side, and the rightmost data selector selects B, thereby outputting the sequence of maximum concentration distribution and sequence of minimum concentration distribution, respectively. Here S represents the output of the stanh module.

表示在输入概率P_X下，当前状态为i的概率；N表示总的状态数。P _Y represents the probability that each bit in the output bit stream is 1; P _X represents the probability that each bit in the input bit stream is 1;

Indicates the probability that the current state is i under the input probability P _X ; N represents the total number of states.

As shown in Figure 7, the random comparator cascade diagram is composed of the above-mentioned random comparator cascaded, and its working principle is briefly introduced: the binary signals are respectively a, b, and c, and are converted into Random bit stream to get three sequences A, B, and C; first compare the sizes of the two sequences B and C, store the larger sequence in MAX1, and store the smaller sequence in MIN1; then compare the sizes of the two sequences MAX1 and A, The larger sequence is stored in MAX, and the smaller sequence is stored in MIN2; finally, the size of the two sequences MINi and MIN2 is compared, the larger sequence is stored in MID, and the smaller sequence is stored in MIN, thereby outputting the largest sequence MAX and the median sequence respectively MID, minimum sequence MIN.

As shown in Figure 8, the above-mentioned cascaded random comparator can be applied to the field of digital image processing such as median filtering, and the whole process is realized by random bit stream. In the tested IEEE gallery, the pixel value of each pixel They are all represented by gray values represented by 8-bit weighted binary, where Fig. 8(a) is the original image, Fig. 8(b) is the median filtering result achieved by the traditional method, and Fig. 8(c) is the result based on random calculation From the results of median filtering, it can be found that the median filter based on random calculation of the present invention has no inherent probability value error compared with the median filter under the weighted binary system.

Those skilled in the art will appreciate that the embodiments described here are to help readers understand the principles of the present invention, and it should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Various modifications and variations of the present invention will occur to those skilled in the art. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of the claims of the present invention.

Claims (4)

1. A median filtering system based on error-free random calculation, comprising: a forward conversion module, a random comparator module and a backward conversion module; The forward conversion module includes a concentrated sequence generation unit and a uniform sequence generation unit, and the concentrated sequence generation unit and the uniform sequence generation unit are used to convert the binary signal into a uniform distribution sequence and a concentrated distribution sequence, respectively; The generation process of described centralized distribution sequence is: compare the weighted binary number with the up counter value of current clock cycle, if greater than the up counter value of current clock cycle, then output bit stream is " 1 "; Otherwise output bit stream is " 0", since the current clock cycle is equal to the previous clock cycle plus 1, so the output "1" is all at the head of the sequence, and the rest of the bits are "0" and the concentrated distribution sequence at the end of the sequence; The generation process of the uniform sequence generation unit is as follows: the value of the up-counter in the current clock cycle and the binary complement of the value of the up-counter in the previous clock cycle are ANDed, and the output of each bit obtained is ANDed with each bit in the binary weighted number , the obtained outputs are respectively connected to the OR gate, and finally a uniformly distributed sequence of weighted binary numbers is obtained; The output end of the concentrated sequence generation unit is connected to the input end of the random comparator, the output end of the uniform sequence generation unit is connected to the selection end of the random comparator, and the output end of the random comparator is connected to the backward conversion module; the backward conversion module will randomly compare The random sequence output by the device is converted into a binary value; A clock cycle module is also included, and the clock cycle module and the forward conversion module share an up counter. 2. A kind of median filtering system based on error-free random calculation according to claim 1, wherein the random comparator module is a cascaded structure of three random comparators, and the three random comparators record successively It is the first random comparator, the second random comparator, and the third random comparator. Each random comparator includes two inputs. By comparing the two inputs, the larger one of the two inputs is used as the random The larger output of the comparator, the smaller of the two inputs is used as the smaller output of the random comparator, correspondingly including three binary signals, three concentrated sequences after the three binary signals pass through the forward conversion module, Two of the concentrated sequences are used as the input of the first random comparator, the other concentrated sequence and the larger output of the first random comparator are used as the input of the second random comparator, and the smaller output of the first random comparator is compared with the second random comparator. The smaller output of the comparator is used as the input of the third random comparator, the larger output of the second random comparator is used as the maximum sequence output of the random comparator module, and the larger output of the third random comparator is used as the random comparator module The median sequence output of the third random comparator is used as the minimum sequence output of the random comparator module; the uniform distribution sequence is used as the input of the selection end of the three random comparators. 3. A kind of median filtering system based on error-free random calculation according to claim 2, wherein a single random comparator comprises: a first random comparison module, a stanh module, a second random comparison module, a third random Comparison module; the two input terminals of the three random comparison modules are used as the two input terminals of the random comparator, the input of the two input terminals of the random comparator is reversed, and the selection terminal of the first random comparison module is used as the random comparator The selection terminal of the comparator; the output terminal of the first random comparison module is connected to the input terminal of the stanh module, and the output terminal of the stanh module is respectively connected to the respective selection terminals of the second random comparison module and the third random comparison module; the second random comparison module The output is used as a larger output terminal of the random comparator, and the output of the third random comparison module is used as a smaller output terminal of the random comparator. 4. a kind of median filter system based on error-free random calculation according to claim 3, is characterized in that, described stanh module is specifically the stanh function based on finite state machine, specifically: The conversion principle of the state transition diagram is: N states, namely S ₀ , S ₁ , , , S _N-1 , X is the initial input value of the state machine, and the output Y is only related to the current state S _i , 0<i< N-1, if 0<i≤N/2-1, the output value Y=0; otherwise, the output value Y=1.

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