CN113131876B

CN113131876B - A CMOS ultra-wideband low noise amplifier

Info

Publication number: CN113131876B
Application number: CN202110526514.0A
Authority: CN
Inventors: 岳宏卫; 杨华光
Original assignee: Guilin University of Electronic Technology
Current assignee: Guilin University of Electronic Technology
Priority date: 2021-05-14
Filing date: 2021-05-14
Publication date: 2025-05-02
Anticipated expiration: 2041-05-14
Also published as: CN113131876A

Abstract

The present invention discloses a CMOS ultra-wideband low-noise amplifier, including an input-stage complementary common-source circuit, an intermediate-stage common-source negative feedback circuit, and an output-stage common-source buffer circuit. The present invention innovatively introduces resistance feedback, inductance peaking technology, source degeneration inductance technology, and pseudo-resistance structure on the basis of the complementary common-source stage, and combines the common-source negative feedback circuit, the common-source buffer circuit, and the current multiplexing technology, so that the overall circuit has a wide bandwidth while achieving good gain, noise figure, power consumption and other indicators. The present invention can operate in the 0.15-11GHz frequency band, covering the 5G low- and medium-frequency bands (450MHz-6GHz) and the IMT service in the 6GHz candidate frequency band (5925-7125MHz), and is also compatible with the UWB standard frequency band (3.1-10.6GHz).

Description

CMOS ultra-wideband low noise amplifier

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a CMOS ultra-wideband low noise amplifier.

Background

With the rapid development of wireless technology, the development of mobile communication technology has been toward higher frequency and wider band, and the use of various wireless standards (e.g., bluetooth, zigbee, WLAN, wiFi, UWB, GPS, and 2G/3G/4G/5G cellular phones) has been increasing. However, spectrum resources are limited, so as to meet the demands of people for higher-speed and larger-capacity communication, ultra-wideband communication technology capable of being compatible with multiple communication standards is becoming an important research direction.

The ultra-wideband low noise amplifier circuit is a core circuit module of an ultra-wideband receiver, is used as a first stage amplifying circuit of an ultra-wideband receiving link, basically determines the overall noise of the receiving link according to a noise cascade formula, has index requirements of gain, matching, power consumption, bandwidth, linearity and the like, has a relationship of trade-off, and is required to be planned according to application requirements.

Common broadband low noise amplifier structures include distributed structures, resistive parallel feedback structures, common gate amplifier structures, and source inductance degeneration structures. The distributed amplifier structure adopts a multi-stage amplifying structure, utilizes a delay transmission line to realize broadband, requires large power consumption and is not suitable for integration and low-power consumption application. In the parallel feedback structure of resistors, the parallel feedback resistor is connected to the gate and drain of the transistor, so that the Q value of the input impedance is reduced, and broadband input matching can be realized. In the common gate amplifier structure, the input impedance is approximately 1/gm, and because the input impedance of the common gate structure is constant, the common gate amplifier structure has broadband matching performance incomparable with other structures, has no feedback capacitance, has the characteristics of good isolation, stability, high linearity, low power consumption and the like, but has high noise coefficient, and other approaches are needed to reduce noise. In the source-level inductance degradation structure, noise and input matching are realized by adjusting source inductance and gate-source capacitance Cgs, but the method can only meet a certain frequency range, and in order to expand the excellent characteristics of noise and matching of the structure in a frequency band, an additional inductance and capacitance element are added to form a band-pass filter together to realize broadband matching.

Disclosure of Invention

The invention solves the problems of ultra-wideband, low noise, low power consumption and the like existing in the background technology, and provides a CMOS ultra-wideband low noise amplifier.

In order to solve the problems, the invention is realized by the following technical scheme:

A CMOS ultra-wideband low noise amplifier comprises an input stage complementary common source circuit, an intermediate stage common source negative feedback circuit and an output stage common source buffer circuit.

The input-stage complementary common-source circuit comprises a PMOS transistor M1, an NMOS transistor M2, a coupling capacitor C1, a feedback resistor R1, a peaking inductor L1, a source degeneration inductor L2, a peaking inductor L3 and a dummy resistor R _pseudo, wherein the source electrode and the substrate of the PMOS transistor M1 are connected with a power supply VDD, the grid electrode of the PMOS transistor M1 is connected with an input end Vin through the coupling capacitor C1, the drain electrode of the PMOS transistor M1 is connected with the grid electrode of the NMOS transistor M2 through the feedback resistor R1, the drain electrode of the PMOS transistor M1 is connected with the drain electrode of the NMOS transistor M2, the source electrode of the NMOS transistor M2 is grounded through the source degeneration inductor L2, and the substrate of the NMOS transistor M2 is grounded through the dummy resistor R _pseudo.

The intermediate-stage common-source negative feedback circuit comprises NMOS transistors M3-M4, a parallel peaking inductor L4, a negative feedback resistor R2, a load resistor R3 and a capacitor C2, wherein the drain electrode of the NMOS transistor M3 is connected with a power supply VDD through the load resistor R3 and the parallel peaking inductor L4 which are connected in series, the grid electrode of the NMOS transistor M3 is connected with the drain electrode of the PMOS transistor M1 through the peaking inductor L3, the source electrode of the NMOS transistor M3 is grounded through the negative feedback resistor R2 and the capacitor C2 which are connected in parallel, the substrate of the NMOS transistor M3 is grounded, the grid electrode of the NMOS transistor M4 is connected with the grid electrode of the NMOS transistor M3, and the source electrode of the NMOS transistor M4 and the substrate are grounded.

The output stage common-source buffer circuit comprises an NMOS transistor M5, a coupling capacitor C3 and an inductor L5, wherein the drain electrode of the NMOS transistor M5 is connected with a power supply VDD, the grid electrode of the NMOS transistor M5 is connected with the drain electrode of the NMOS transistor M3, the source electrode of the NMOS transistor M5 is connected with an output end Vout through the coupling capacitor C3 and is connected with the drain electrode of the NMOS transistor M4 through the inductor L5, and the substrate of the NMOS transistor M5 is grounded.

In the scheme, the dummy resistor R _pseudo consists of two PMOS transistors M6 and M7 of the same type, wherein the source electrode of the PMOS transistor M6 is connected with the substrate of the NMOS transistor M2, the substrate and the source electrode of the PMOS transistor M6 are connected with the substrate of the NMOS transistor M2 in parallel, the grid electrode and the drain electrode of the PMOS transistor M6 are connected with the substrate and the source electrode of the PMOS transistor M7, and the grid electrode and the drain electrode of the PMOS transistor M7 are connected with the ground.

Compared with the prior art, the invention has the following characteristics:

1. The invention innovatively introduces resistance feedback, inductance peaking technology, source degeneration inductance technology and pseudo resistance structure on the basis of complementary common source stage, and simultaneously combines a common source negative feedback circuit, a common source buffer circuit and a current multiplexing technology, so that the whole circuit has wide bandwidth and achieves good indexes such as gain, noise coefficient, power consumption and the like.

2. The pseudo resistance structure introduced by the ultra-wideband low noise amplifier can effectively reduce the noise coefficient of the circuit.

3. The invention can work in the frequency band of 0.15-11 GHz, covers the range of 5G medium-low frequency band (450 MHz-6 GHz) and the range of 6GHz candidate frequency band (5925-7125 MHz) of IMT service, and is compatible with UWB standard frequency band (3.1-10.6 GHz).

Drawings

FIG. 1 is a circuit diagram of a CMOS ultra wideband low noise amplifier;

FIG. 2 is a diagram of a pseudo-resistance circuit used in a CMOS ultra wideband low noise amplifier;

FIG. 3 shows the S-parameter simulation result of a CMOS ultra wideband low noise amplifier;

FIG. 4 shows the result of noise simulation of a CMOS ultra wideband low noise amplifier;

Fig. 5 is a simulation result of stability of a CMOS ultra wideband low noise amplifier.

Detailed Description

The present invention will be described in further detail with reference to the following embodiments and the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.

A CMOS ultra-wideband low noise amplifier is shown in figure 1, adopts a single-ended input-output structure, and consists of an input stage complementary common-source circuit, an intermediate stage common-source negative feedback circuit and an output stage common-source buffer circuit. The input stage complementary common-source circuit is connected with the intermediate stage common-source negative feedback circuit, and the output end of the intermediate stage common-source negative feedback circuit is connected with the output stage common-source buffer circuit.

The input stage complementary common source circuit comprises a PMOS transistor M1, an NMOS transistor M2, an input coupling capacitor C1, a feedback resistor R1, a peaking inductor L1, a source degeneration inductor L2, a peaking inductor L3 and a dummy resistor R _pseudo. The source and substrate of PMOS transistor M1 are connected to power supply VDD. The gate of the PMOS transistor M1 is connected to the input terminal Vin through an input coupling capacitor C1, to the drain of the PMOS transistor M1 through a feedback resistor R1, and to the gate of the NMOS transistor M2 through a peaking inductor L1. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M2. The source of the NMOS transistor M2 is grounded through the source degeneration inductance L2. The substrate of the NMOS transistor M2 is grounded through the dummy resistor R _pseudo. The dummy resistor R _pseudo is composed of two PMOS transistors M6 and M7 of the same type, as shown in fig. 2. The source of PMOS transistor M6 is connected to the substrate of NMOS transistor M2. The substrate of PMOS transistor M6 is connected to the source and in parallel with the substrate of NMOS transistor M2. The gate and drain of PMOS transistor M6 are connected to the substrate and source of PMOS transistor M7. The gate and drain of PMOS transistor M7 are connected to ground. The input stage adopts complementary common-source stage structures (M1 and M2) to double the current efficiency, and the introduction of the feedback resistor R1 also provides bias for the circuit while realizing broadband input matching. The input stage gain AV ₁ is approximately- (gm1+gm2) x Zout1, so that larger M1 and M2 can be selected to reduce noise and increase the gain of the input stage, while a large-sized transistor increases the output parasitic capacitance, resulting in a narrower frequency band of the input stage output. L1 and L2 introduced in fig. 1 can reduce parasitic capacitance to enhance the bandwidth of the circuit and improve input matching. The substrate of M2 is grounded through the dummy resistor R _pseudo to form an open circuit state, so that the isolation between the isolation radio-frequency transistor and the ground is achieved, the leakage of signals and noise coupling are avoided, and the noise and gain of the circuit are improved. The input coupling capacitor C1 serves to isolate the dc component.

The intermediate-stage common-source negative feedback circuit comprises NMOS transistors M3-M4, a parallel peaking inductor L4, a negative feedback resistor R2, a load resistor R3 and a capacitor C2. The drain electrode of the NMOS transistor M3 is connected with a power supply VDD through a load resistor R3 and a parallel peaking inductor L4 which are connected in series. The gate of the NMOS transistor M3 is connected to the drain of the PMOS transistor M1 through the peaking inductor L3. The source of the NMOS transistor M3 is grounded through a negative feedback resistor R2 and a capacitor C2 which are connected in parallel. The substrate of the NMOS tube M3 is grounded. The gate of the NMOS transistor M4 is connected to the gate of the NMOS transistor M3. The source and substrate of NMOS transistor M4 are grounded. The signal in the intermediate stage passes through two paths, including upper paths M3 and M5 and lower path M4. The output parasitic capacitance of the first stage and the input parasitic capacitance of the second stage form a pi-type matching network with the lead-in inductance L3, so that interstage matching can be realized. The inductor L4 and the resistor R3 form a parallel peaking structure which is used for expanding the bandwidth of the circuit, and the source negative feedback structure consists of the resistor R2 and the capacitor C2 and is used for expanding the bandwidth of the circuit and stabilizing the circuit. M4 is an auxiliary amplifier stage for increasing the gain of the intermediate stage.

The output stage common-source buffer circuit comprises an NMOS transistor M5, an output coupling capacitor C3 and an inductor L5. The drain of the NMOS transistor M5 is connected to the power supply VDD. The gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M3. The source of the NMOS transistor M5 is connected to the output terminal Vout through the output coupling capacitor C3, and to the drain of the NMOS transistor M4 through the inductor L5. The substrate of the NMOS transistor M5 is grounded. The output coupling capacitor C3 plays a role of isolating the direct current component. The output stage common source buffer circuit is used for realizing broadband output matching.

The embodiment adopts a TSMC 0.18um RF CMOS process to realize the CMOS ultra-wideband low noise amplifier. Fig. 3 shows the S-parameter simulation result of the present embodiment, and it can be seen from the figure that the 3dB bandwidth of the present CMOS ultra wideband low noise amplifier reaches 11.9GHz. The gain is 13.8-14.5 dB in the frequency band of 0.15-11 GHz, the in-band gain flatness is good, S11 and S22 are smaller than-10 dB, a good input/output matching effect is achieved, and S12 is smaller than-25 dB, so that a good reverse isolation effect is achieved. The noise simulation result of the embodiment is shown in fig. 4, and it can be seen from the graph that the noise coefficient of the ultra-wideband low noise amplifier of the CMOS is less than or equal to 3dB in the frequency range of 0.15-11 ghz, and the noise comparison before and after the introduction of the pseudo resistor is given, and from the graph, the noise coefficient of the circuit is obviously optimized after the introduction of the pseudo resistor, and the average noise of the circuit is optimized by 0.37dB through calculation, and the optimizing effect reaches 13%. Fig. 5 shows the stability simulation result of the embodiment, and it can be seen from the graph that the stability coefficient of the CMOS ultra-wideband low noise amplifier is greater than 1 in the frequency range of 0.15-11 ghz. And under the condition that the power supply voltage is 1.5V, the overall power consumption of the circuit is 6.4mW. In summary, under the TSMC 0.18um RF CMOS process, the invention can realize the working bandwidth of 0.15-11 GHz, S11 and S22 are smaller than-10 dB, the gain is 13.8-14.5 dB, the noise coefficient is 2.7-3 dB, the power consumption is 6.4mW, and the simulation results prove that the invention is effective.

The CMOS ultra-wideband low noise amplifier provided by the invention adopts a current multiplexing structure, and the input stage introduces a resistance feedback, an inductance peaking technology, a source degeneration inductance technology and a pseudo resistance structure on the basis of complementary common source stages, so that the circuit bandwidth can be expanded, the gain of the circuit can be improved, and the circuit noise can be reduced. The intermediate stage introduces a gain auxiliary stage and a parallel inductance peaking technology based on a common source stage with source negative feedback, so that the circuit bandwidth can be expanded and the circuit gain can be increased. The output stage adopts a common source buffer circuit, so that broadband output matching can be realized.

It should be noted that, although the examples described above are illustrative, this is not a limitation of the present invention, and thus the present invention is not limited to the above-described specific embodiments. Other embodiments, which are apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein, are considered to be within the scope of the invention as claimed.

Claims

1. A CMOS ultra-wideband low noise amplifier, characterized in that it includes an input-stage complementary common-source circuit, an intermediate-stage common-source negative feedback circuit and an output-stage common-source buffer circuit;

The input stage complementary common source circuit includes a PMOS transistor M1, an NMOS transistor M2, a coupling capacitor C1, a feedback resistor R1, a peaking inductor L1, a source degeneration inductor L2, a peaking inductor L3 and a pseudo resistor R _pseudo ; the source and substrate of the PMOS transistor M1 are connected to a power supply VDD; the gate of the PMOS transistor M1 is connected to an input terminal Vin through a coupling capacitor C1, is connected to a drain of the PMOS transistor M1 through a feedback resistor R1, and is connected to a gate of the NMOS transistor M2 through a peaking inductor L1; the drain of the PMOS transistor M1 is connected to a drain of the NMOS transistor M2; the source of the NMOS transistor M2 is grounded through the source degeneration inductor L2; and the substrate of the NMOS transistor M2 is grounded through the pseudo resistor R _pseudo ;

The intermediate common source negative feedback circuit includes NMOS transistors M3-M4, a parallel peaking inductor L4, a negative feedback resistor R2, a load resistor R3 and a capacitor C2; the drain of the NMOS transistor M3 is connected to the power supply VDD through the series load resistor R3 and the parallel peaking inductor L4; the gate of the NMOS transistor M3 is connected to the drain of the PMOS transistor M1 through the peaking inductor L3; the source of the NMOS transistor M3 is grounded through the parallel negative feedback resistor R2 and the capacitor C2; the substrate of the NMOS tube M3 is grounded; the gate of the NMOS transistor M4 is connected to the gate of the NMOS transistor M3; the source and substrate of the NMOS transistor M4 are grounded;

The output stage common source buffer circuit includes an NMOS transistor M5, a coupling capacitor C3 and an inductor L5; the drain of the NMOS transistor M5 is connected to the power supply VDD; the gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M3; the source of the NMOS transistor M5 is connected to the output terminal Vout through the coupling capacitor C3, and is connected to the drain of the NMOS transistor M4 through the inductor L5; the substrate of the NMOS transistor M5 is grounded.

2. A CMOS ultra-wideband low noise amplifier according to claim 1, characterized in that the pseudo resistor R _pseudo is composed of two PMOS transistors M6 and PMOS transistor M7 of the same type; the source of the PMOS transistor M6 is connected to the substrate of the NMOS transistor M2;

The substrate and source of the PMOS transistor M6 are connected and connected to the substrate of the NMOS transistor M2; the gate and drain of the PMOS transistor M6 are connected to the substrate and source of the PMOS transistor M7; the gate and drain of the PMOS transistor M7 are connected and grounded.