CN113223999A - Wafer bonding method and wafer bonding structure - Google Patents
Wafer bonding method and wafer bonding structure Download PDFInfo
- Publication number
- CN113223999A CN113223999A CN202110358013.6A CN202110358013A CN113223999A CN 113223999 A CN113223999 A CN 113223999A CN 202110358013 A CN202110358013 A CN 202110358013A CN 113223999 A CN113223999 A CN 113223999A
- Authority
- CN
- China
- Prior art keywords
- wafer
- bonding
- hole
- layer
- adhesive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 78
- 239000012790 adhesive layer Substances 0.000 claims abstract description 57
- 239000010410 layer Substances 0.000 claims abstract description 57
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052802 copper Inorganic materials 0.000 claims abstract description 45
- 239000010949 copper Substances 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 27
- 238000009713 electroplating Methods 0.000 claims abstract description 21
- 239000011248 coating agent Substances 0.000 claims abstract description 8
- 238000000576 coating method Methods 0.000 claims abstract description 8
- 230000000149 penetrating effect Effects 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 10
- 239000002861 polymer material Substances 0.000 claims description 10
- 238000000708 deep reactive-ion etching Methods 0.000 claims description 9
- 238000004891 communication Methods 0.000 claims description 8
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 238000003486 chemical etching Methods 0.000 claims description 3
- 238000010329 laser etching Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 2
- 238000005260 corrosion Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 abstract description 267
- 230000008646 thermal stress Effects 0.000 abstract description 9
- 241001391944 Commicarpus scandens Species 0.000 abstract description 4
- 238000010923 batch production Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 238000010586 diagram Methods 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004080 punching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a wafer bonding structure and a wafer bonding method, wherein the bonding method comprises the following three steps: the first method comprises the following steps: bonding the first wafer and the second wafer through the bonding layer, manufacturing a through silicon via of the second wafer and a through hole of the bonding layer, and electroplating to form copper through hole connection between the two wafers; the second method comprises the following steps: manufacturing a second wafer through silicon via, coating an adhesive layer on a first wafer, manufacturing a through hole of the adhesive layer on the first wafer, combining the first wafer and the second wafer through the adhesive layer, and electroplating to form copper through hole connection between the two wafers; the third method comprises the following steps: and manufacturing a second wafer through silicon via, coating an adhesive layer on the first wafer, combining the first wafer and the second wafer through the adhesive layer, manufacturing a through hole of the adhesive layer through etching the second wafer through silicon via, and electroplating to form copper through hole connection between the two wafers. The invention has the advantages that the wafer copper through hole connection is completed in batch production at room temperature, the wafer shape is reduced at room temperature, the thermal stress is small, and the wafer is not easy to break. The bonding of the multilayer wafer can be simply achieved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a wafer bonding method and a wafer bonding structure.
Background
Wafer bonding technology can bond wafers of different materials together, and wafer bonding refers to bonding the surfaces of two wafers to realize electrical and mechanical connection between wafer chips. Common bonding techniques are: silicon-silicon direct bonding, silicon-glass direct bonding, metal diffusion bonding, polymer bonding and the like, which have been applied to a plurality of semiconductor fields, such as 3D-TSV (3D through silicon via technology), HB-LED (white light high brightness light emitting diode), SOI (silicon on insulator technology), MEMS (micro electro mechanical system) and the like, are one of important technologies for the development of the semiconductor industry in the future. In addition, Through-Silicon-Via (TSV) refers to a method of making vertical conduction between chips and between wafers.
At present, the process parameters of wafer bonding are different according to different application fields, but the basic principles are similar. As shown in fig. 1(a) and 1(b), two wafer bonding methods in the prior art are shown, in which fig. 1(a) shows a conventional wafer solder bonding, and fig. 1(b) shows a conventional wafer copper direct bonding. There are a number of drawbacks in the prior art bonding process described above. For example, conventional wafer solder bonding requires higher temperatures, such as the 240 ℃. — (260 ℃) soldering temperature of lead-free solder. Copper direct bonding requires relatively high temperatures and pressures, with high temperatures typically being 350-450 ℃. The wafer is easy to deform at high temperature and high pressure, the bonding yield is reduced, and the mechanical pressure and thermal stress of the bonded wafer are increased due to the high temperature and high pressure, so that the wafer may be broken. In addition, in the existing wafer bonding process, the bonding process time is long, the process time in bonding equipment is long, the efficiency is low, and the bottleneck of the process efficiency is formed. In addition, the process cost is high, and besides the high cost caused by long bonding time, the bonding equipment is expensive due to the requirements of high precision, high pressure and high temperature, and the process cost is also increased.
Therefore, it is necessary to provide a wafer bonding method and a wafer bonding structure to solve the above-mentioned problems in the prior art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a wafer bonding method and a bonding structure, which are used to solve the problems of wafer deformation, cracking, low bonding yield, residual thermal stress, etc. caused by the high temperature and high pressure required for wafer bonding in the prior art.
In order to achieve the above and other related objects, the present invention provides a wafer bonding structure, which includes a first wafer and a second wafer on the first wafer, wherein an adhesion layer is disposed between the first wafer and the second wafer, and the wafer bonding structure further includes a copper via connection structure penetrating through the second wafer and the adhesion layer.
Optionally, the copper via connection structure electrically connects corresponding bonding pads on the first wafer and the second wafer to achieve electrical connection between the first wafer and the second wafer.
Optionally, the bonding structure further includes a third wafer to an nth wafer, N is greater than or equal to 3, and a corresponding connection structure penetrating through upper and lower surfaces is formed in the third wafer to the nth wafer and electrically connected to the first wafer and the second wafer through the connection structure.
The invention also provides a wafer bonding method, wherein the wafer bonding structure provided by the invention is preferably manufactured by adopting the wafer bonding method provided by the invention, and the wafer bonding method comprises the following steps: providing a first wafer and a second wafer; the first wafer and the second wafer are combined through an adhesive layer, and through holes are formed in the second wafer and the adhesive layer; and forming a copper through hole connecting structure penetrating through the second wafer and the bonding layer by an electroplating process.
Optionally, the method specifically includes the following steps:
bonding the first wafer and the second wafer through the bonding layer;
manufacturing a communication hole penetrating through the second wafer and the bonding layer;
and electroplating to form the copper through hole connecting structure in the communication hole.
Optionally, the method specifically includes the following steps:
manufacturing a silicon through hole on the second wafer;
coating the first wafer to form the bonding layer;
forming an adhesive layer through hole in the adhesive layer;
the first wafer and the second wafer are combined through the bonding layer, and the through silicon via corresponds to the through silicon via of the bonding layer;
and electroplating in the corresponding through hole to form the copper through hole connecting structure.
Optionally, the method specifically includes the following steps:
manufacturing a silicon through hole on the second wafer;
coating the first wafer to form the bonding layer;
bonding the first wafer and the second wafer through the bonding layer;
corroding the silicon through holes in the second wafer in the bonding layer to manufacture bonding layer through holes;
and electroplating to form the copper through hole connecting structure in the through hole formed by corrosion.
Optionally, the through hole in the second wafer is manufactured by a deep reactive ion etching method.
Optionally, the material of the adhesive layer includes a polymer material, and the polymer material includes epoxy resin.
Optionally, the adhesive layer is formed on the first wafer in a manner that the adhesive layer is attached to the first wafer by dry film bonding and heating, or the adhesive layer is formed on the first wafer by spin coating.
Optionally, the through hole in the bonding layer is manufactured by deep reactive ion etching, laser etching or chemical etching.
Optionally, the copper via connection structure electrically connects corresponding bonding pads on the first wafer and the second wafer to achieve electrical connection between the first wafer and the second wafer.
Optionally, the bonding method further includes a step of providing a third wafer to an nth wafer, where N is greater than or equal to 3, where a corresponding connection structure penetrating through upper and lower surfaces is formed in the third wafer to the nth wafer, and the third wafer and the nth wafer are electrically connected to the first wafer and the second wafer through the connection structure.
As described above, the wafer bonding method and the wafer bonding structure of the present invention have the advantages that the wafer copper through hole electroplating connection is completed by batch production at room temperature, the wafer shape becomes smaller at room temperature, which is beneficial to improving the wafer bonding yield, and the bonded wafer has small thermal stress at room temperature, and the wafer is not easy to break. The traditional wafer solder bonding and copper direct bonding require higher temperature and pressure, the wafer deforms at high temperature, the bonding yield is reduced, and the mechanical pressure and thermal stress of the bonded wafer are increased due to high temperature and high pressure, so that the wafer can be broken. Based on the bonding mode of the invention, the bonding of the multilayer wafer can be simply and effectively realized.
Drawings
Fig. 1(a) and 1(b) show a wafer bonding structure in the prior art.
Fig. 2(a) -2 (e) represent schematic views of structures obtained at respective steps in the first production process in example two.
Fig. 3(a) -3 (g) represent schematic diagrams of structures obtained at respective steps in the second production process in example three.
Fig. 4(a) -4 (g) represent schematic diagrams of structures obtained at respective steps in the third production process in example four.
Description of the element reference numerals
100. 200, 300 first wafer
101. 201, 301 first bond pad
102. 202, 302 second wafer
103. 203, 303 second bonding pad
104. 205, 305 bonding layer
105 communication hole
106. 207, 307 copper through hole connection structure
204. 304 through silicon via
206. 306 bonding layer via hole
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In addition, "between … …" as used herein includes both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As described in the background section, there are many problems in wafer bonding in the prior art, for example, the conventional wafer solder bonding and copper direct bonding require higher temperature and higher pressure, the wafer deforms at high temperature, the bonding yield is reduced, and the wafer may break due to the increased mechanical stress and thermal stress of the bonded wafer caused by the high temperature and high pressure, wherein fig. 1(a) is a schematic diagram of a conventional wafer solder bonding structure, and fig. 1(b) is a schematic diagram of a conventional wafer copper direct bonding structure. In addition, in the existing wafer bonding process, the problems of long bonding process time and the like exist, the process time in bonding equipment is long, the efficiency is low, and the bottleneck of the process efficiency is formed. In addition, the process cost is high, and besides the high cost caused by long bonding time, the bonding equipment is expensive due to the requirements of high precision, high pressure and high temperature, and the process cost is also increased.
The invention provides a wafer bonding method and a bonding structure obtained by the same, which can solve the problems in the prior art.
In the wafer bonding structure, a mechanical bonding layer and a copper through hole electrical connection structure penetrating through the second wafer and the bonding layer are arranged between the first wafer and the second wafer. The wafer bonding method of the invention comprises the following steps: providing a first wafer and a second wafer; the first wafer and the second wafer are combined through an adhesive layer, and through holes are formed in the second wafer and the adhesive layer; and forming a copper through hole connecting structure penetrating through the second wafer and the bonding layer by an electroplating process. That is to say, the invention forms the mechanical bonding layer and the copper through hole electrical connection structure penetrating through the second wafer and the bonding layer between the first wafer and the second wafer, the invention has the advantages that the wafer copper through hole electroplating connection is completed by batch production at room temperature, the wafer shape becomes smaller at room temperature, which is beneficial to improving the wafer bonding yield, and meanwhile, the thermal stress of the bonded wafer at room temperature is small, and the wafer is not easy to break. Based on the bonding mode of the invention, the bonding of the multilayer wafer can be simply and effectively realized.
The wafer bonding structure and method of the present invention will be described separately below. In the first embodiment, the wafer bonding structure of the present invention is described, and in the second to fourth embodiments, the wafer bonding method of the present invention is described. Specifically, different wafer bonding processes may be provided according to different manufacturing sequences, and the bonding method of the present invention may include three processes: FIGS. 2(a) -2 (e) are schematic diagrams of structures obtained at various steps in the first preparation process in the first example; FIGS. 3(a) -3 (g) are schematic diagrams representing structures obtained at steps in the second preparation process in example two; fig. 4(a) to 4(g) are schematic diagrams showing structures obtained at respective steps in the third production process in example three. In addition, it should be noted that the wafer bonding structure in the first embodiment is described by taking the wafer bonding method as described in the second embodiment as an example.
The first embodiment is as follows: and bonding the wafer to obtain the structure.
The invention provides a wafer bonding structure, which comprises a first wafer 100 and a second wafer 102 positioned on the first wafer 100, wherein an adhesive layer 104 is arranged between the first wafer 100 and the second wafer 102, and the wafer bonding structure further comprises a copper through hole connecting structure 106 penetrating through the second wafer 102 and the adhesive layer 104. Here, it is understood by those skilled in the art that the through-penetration herein refers to the structure on the first wafer 100 shown through the adhesive layer 104, such as the first bonding pad 101 on the first wafer 100 shown, to achieve the electrical connection.
As an example, the copper via connection structure 105 electrically connects corresponding bonding pads on the first wafer 100 and the second wafer 102, i.e., the first bonding pad 101 and the second bonding pad 103, to achieve an electrical connection between the first wafer 100 and the second wafer 102.
In one example, the first bonding pad 101 may be selected to be a copper pad, but may be other bonding pads. The number and arrangement of the first bonding pads 101 can be designed according to actual requirements. Similarly, the structure and material of the second bonding pad 103 may be the same as those of the first bonding pad 101. In one example, the first bonding pads 101 correspond to the second bonding pads 102 one to one for electrical connection between wafers.
As an example, the material of the adhesive layer 104 may be a polymer material, and in a further example, the polymer material may be selected to be epoxy resin. Of course, other materials for the adhesive layer 104 may be selected according to the actual process. In one example, the adhesive, i.e., the resulting bonding layer 104, has a thickness between 1-20 μm, such as 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm.
As an example, the method further includes the step of providing a third wafer to an nth wafer, where N is greater than or equal to 3, where the third wafer to the nth wafer have corresponding connection structures formed therein and penetrate through the upper surface, and are electrically connected to the first wafer and the second wafer through the connection structures. In this example, a structure of three or more wafer bonds may be formed, for example, for three wafer bonds, after the first wafer and the second wafer are completed, the third wafer may be formed on the second wafer in the above manner, and similarly, other wafers may also be formed to obtain a desired stacked bonded structure.
Example two: wafer bonding method for bonding wafers and then punching
Fig. 2(a) -2 (e) are schematic diagrams of structures obtained in the steps of the first manufacturing process in the second embodiment. The wafer bonding method comprises the following steps:
1) bonding a first wafer 100 and a second wafer 102 through an adhesive layer 104;
2) forming a via hole 105 penetrating the second wafer 102 and the adhesive layer 104;
3) a copper via connection structure 106 is formed in the via hole 105 by electroplating.
In step 1), first, as shown in fig. 2(a), a first wafer 100 is provided, and in an example, a first bonding pad 101 is formed on the first wafer 100. Next, as shown in fig. 2(b), a second wafer 102 is provided, and in an example, a second bonding pad 103 is formed on the second wafer 102. Then, as shown in fig. 2(c), the second wafer 102 is placed on the adhesive layer 104 and bonded to the first wafer 100 below through the adhesive layer 104.
As an example, the material of the adhesive layer 104 may be a polymer material, and in a further example, the polymer material may be selected to be epoxy resin. Of course, other materials for the adhesive layer 104 may be selected according to the actual process.
As an example, the adhesion layer (e.g., polymer material layer) 104 may be formed on the first wafer 100 by: the adhesive layer 104 is attached to the first wafer 100 by dry film attachment and heating. In another example, the adhesion layer (e.g., polymer material layer) 104 may be formed on the first wafer 100 by: the adhesive layer 104 is formed on the first wafer 100 by spin coating.
In one example, the upper surface of the adhesive layer 104 is higher than the upper surface of the first bonding pad 101.
In step 2), as shown in fig. 2(d), a via hole 105 penetrating both the second wafer 102 and the adhesive layer 104 is formed. In an example, the communication hole 105 exposes a surface of the first bonding pad 101 of the first wafer 100.
As an example, the second wafer 102 and the adhesion layer 104 are etched simultaneously based on the same process to form the communication hole 105 penetrating through the stacked structure of the second wafer 102 and the adhesion layer 104 in both, wherein, in an example, the communication hole 105 is preferably manufactured by Deep Reactive Ion Etching (DRIE).
In step 3), as shown in fig. 2(e), a copper via-hole connection structure 106 is formed in the via hole 105 by electroplating. In an example, the copper via connection structure 106 electrically connects corresponding bonding pads on the first wafer 100 and the second wafer 102, i.e., electrically connects the first bonding pad 101 and the second bonding pad 103, thereby achieving an electrical connection between the first wafer 100 and the second wafer 102.
Example three: one of the wafer bonding methods of punching and bonding
Fig. 3(a) -3 (g) are schematic diagrams of structures obtained in the steps of the second manufacturing process in the third embodiment. The difference between the second embodiment and the first embodiment mainly lies in the difference of the step sequence in the manufacturing process of the wafer bonding structure, and the material selection and the specific process of other related structural layers can refer to the first embodiment, which is not described herein again.
The wafer bonding method in the second embodiment includes the steps of:
1) manufacturing a through silicon via 204 on the second wafer 202;
2) coating the first wafer 200 to form the adhesive layer 205;
3) forming an adhesive layer through hole 206 in the adhesive layer 205;
4) the first wafer 200 and the second wafer 202 are bonded by the adhesive layer 205, and the through-silicon via 204 corresponds to the adhesive layer via 206;
5) the copper via connection structure 207 is formed by electroplating in the corresponding via hole.
In step 1), first, as shown in fig. 3(a), a first wafer 200 is provided, and in an example, a first bonding pad 201 is formed on the first wafer 200. Next, as shown in fig. 3(b), a second wafer 202 is provided, and in an example, a second bonding pad 203 is formed on the second wafer 202. Then, as shown in fig. 3(c), a through-silicon via 204 is formed in the second wafer 202. In one example, the through-silicon-via 204 is preferably fabricated by deep reactive ion etching.
In step 2), as shown in fig. 3(d), the adhesive layer 205 is formed on the first wafer 200; of course, in other examples, a dry film may be attached to the first wafer 200 by heating.
In step 3), as shown in fig. 3(e), an adhesive layer through-hole 206 is formed in the adhesive layer 205;
as an example, the adhesive layer through hole 206 in the adhesive layer 205 is manufactured by using a deep reactive ion etching, laser etching, or chemical etching method.
In step 4), as shown in fig. 3(f), the first wafer 200 and the second wafer 202 are bonded by the adhesive layer 205, and the through-silicon-via 204 corresponds to the adhesive layer via 206.
In one example, the bond layer via 206 is designed to have a diameter greater than the diameter of the through silicon via 204. Preferably, the centers of the adhesive layer through hole 206 and the through silicon hole 204 are controlled to coincide during the bonding process based on the adhesive layer 205.
In step 5), as shown in fig. 3(g), the copper via connection structure 207 is formed in the corresponding via by electroplating. That is, after the adhesive layer via 206 and the through-silicon via 204 are aligned, a through via is formed, which exposes the first wafer bonding pad 201, and further, a copper via connection structure 207 is formed in the through via.
In an example, the copper via connection structure 207 electrically connects corresponding bonding pads on the first wafer 200 and the second wafer 202, i.e., electrically connects the first bonding pad 201 and the second bonding pad 203, thereby achieving an electrical connection between the first wafer 200 and the second wafer 202.
Example four: another wafer bonding method of punching and then bonding
Fig. 4(a) -4 (g) are schematic diagrams illustrating structures obtained in the steps of the third manufacturing process in the fourth embodiment. The third embodiment is different from the second and third embodiments mainly in the step sequence in the wafer bonding structure manufacturing process, and the material selection and specific processes of other related structural layers may refer to the description in the first and second embodiments, and will not be described herein again.
The wafer bonding method in the second embodiment includes the steps of:
1) fabricating a through silicon via 304 on the second wafer 302;
2) coating the first wafer 300 to form the adhesive layer 305;
3) bonding the first wafer 300 and the second wafer 302 by the adhesive layer 305;
4) etching a bonding layer via 306 in the bonding layer through the through silicon via 304 in the second wafer 302;
5) the copper via connection structure 307 is formed by electroplating in the via hole formed by etching.
In step 1), first, as shown in fig. 4(a), a first wafer 300 is provided, and in one example, a first bonding pad 301 is formed on the first wafer 300. Next, as shown in fig. 4(b), a second wafer 302 is provided, and in an example, a second bonding pad 303 is formed on the second wafer 302. Then, as shown in fig. 3(c), a through silicon via 304 is fabricated in the second wafer 302. In one example, the through-silicon-via 304 is preferably fabricated by deep reactive ion etching.
In step 2), as shown in fig. 4(d), the adhesive layer 305 is formed on the first wafer 300; of course, in other examples, a dry film may be attached to the first wafer 300 by heating.
In step 3), as shown in fig. 4(e), the first wafer 300 and the second wafer 302 are bonded by the adhesive layer 305.
In an example, the size of the through silicon via 304 is designed to be smaller than the size of the first bonding pad 301, and it may be that projections of the outer edge of the through silicon via 304 on the first bonding pad 301 all fall on the first bonding pad 301 to facilitate alignment of subsequent processes.
In step 4), as shown in fig. 4(f), an adhesion layer via 306 is etched in the adhesion layer 305 through the through-silicon via 304 in the second wafer 302.
In step 5), as shown in fig. 4(g), the copper via connection structure 307 is formed by electroplating in the via hole formed by etching. That is, the bond layer via 306 formed in the bond layer and the through-silicon-via 304 form a communicating via that exposes the first wafer bond pad 301, and further, the copper via connection structure 207 is formed in the via.
In an example, the copper via connection structure 307 electrically connects corresponding bonding pads on the first wafer 300 and the second wafer 302, i.e., electrically connects the first bonding pad 301 and the second bonding pad 303, thereby achieving an electrical connection between the first wafer 300 and the second wafer 302.
It should be noted that the three bonding methods are illustrated as back-to-back wafer bonding, and those skilled in the art will understand that the three methods are also applicable to face-to-face wafer bonding. In addition, as an example, the multi-layer wafer bonding structure can be formed according to actual requirements in any of the three ways. That is, in an example, the bonding method further includes a step of providing third to nth wafers, N is greater than or equal to 3, wherein corresponding connection structures penetrating through upper and lower surfaces are formed in the third to nth wafers, and are electrically connected with the first and second wafers through the connection structures.
In conclusion, the wafer bonding method and the wafer bonding structure have the advantages that the wafer copper through hole electroplating connection is completed through batch production at room temperature, the wafer shape becomes small at room temperature, the wafer bonding yield is improved, meanwhile, the thermal stress of the bonded wafer at room temperature is small, and the wafer is not easy to break. The traditional wafer solder bonding and copper direct bonding require higher temperature and high pressure, the wafer deforms at high temperature, the bonding yield is reduced, and the mechanical pressure and the thermal stress of the bonded wafer are increased due to the high temperature and the high pressure, so that the wafer can be broken. Based on the bonding mode of the invention, the bonding of the multilayer wafer can be simply and effectively realized. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (13)
1. A wafer bonding structure is characterized by comprising a first wafer and a second wafer located on the first wafer, wherein an adhesion layer is arranged between the first wafer and the second wafer, and the wafer bonding structure further comprises a copper through hole connecting structure penetrating through the second wafer and the adhesion layer.
2. The wafer bonding structure of claim 1, wherein the copper via connection structure electrically connects corresponding bonding pads on the first wafer and the second wafer to enable electrical connection between the first wafer and the second wafer.
3. The wafer bonding structure of any one of claims 1 to 2, wherein the bonding structure further comprises a third wafer to an nth wafer, N is greater than or equal to 3, and a corresponding connection structure penetrating through upper and lower surfaces is formed in the third wafer to the nth wafer and electrically connected with the first wafer and the second wafer through the connection structure.
4. A wafer bonding method is characterized by comprising the following steps: providing a first wafer and a second wafer; the first wafer and the second wafer are combined through an adhesive layer, and through holes are formed in the second wafer and the adhesive layer; and forming a copper through hole connecting structure penetrating through the second wafer and the bonding layer by an electroplating process.
5. The wafer bonding method according to claim 4, wherein the method specifically comprises the steps of:
bonding the first wafer and the second wafer through the bonding layer;
manufacturing a communication hole penetrating through the second wafer and the bonding layer;
and electroplating to form the copper through hole connecting structure in the communication hole.
6. The wafer bonding method according to claim 4, wherein the method specifically comprises the steps of:
manufacturing a silicon through hole on the second wafer;
coating the first wafer to form the bonding layer;
forming an adhesive layer through hole in the adhesive layer;
the first wafer and the second wafer are combined through the bonding layer, and the through silicon via corresponds to the through bonding layer;
and electroplating in the corresponding through hole to form the copper through hole connecting structure.
7. The wafer bonding method according to claim 4, wherein the method specifically comprises the steps of:
manufacturing a silicon through hole on the second wafer;
coating the first wafer to form the bonding layer;
bonding the first wafer and the second wafer through the bonding layer;
corroding the silicon through holes in the second wafer in the bonding layer to manufacture bonding layer through holes;
and electroplating to form the copper through hole connecting structure in the through hole formed by corrosion.
8. The wafer bonding method of claim 4, wherein the through hole in the second wafer is manufactured by deep reactive ion etching.
9. The wafer bonding method according to claim 4, wherein the material of the adhesive layer comprises a polymer material, and the polymer material comprises epoxy resin.
10. The wafer bonding method according to claim 4, wherein the adhesive layer is formed on the first wafer by applying the adhesive layer onto the first wafer by dry film bonding or by spin coating.
11. The wafer bonding method according to claim 4, wherein the through hole in the bonding layer is manufactured by deep reactive ion etching, laser etching or chemical etching.
12. The wafer bonding method of claim 4, wherein the copper via connection structure electrically connects corresponding bonding pads on the first wafer and the second wafer to enable electrical connection between the first wafer and the second wafer.
13. The wafer bonding method according to any one of claims 4 to 12, further comprising a step of providing a third wafer to an nth wafer, wherein N is greater than or equal to 3, wherein corresponding connection structures penetrating through upper and lower surfaces are formed in the third wafer to the nth wafer and are electrically connected with the first wafer and the second wafer through the connection structures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110358013.6A CN113223999A (en) | 2021-04-01 | 2021-04-01 | Wafer bonding method and wafer bonding structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110358013.6A CN113223999A (en) | 2021-04-01 | 2021-04-01 | Wafer bonding method and wafer bonding structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113223999A true CN113223999A (en) | 2021-08-06 |
Family
ID=77086325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110358013.6A Pending CN113223999A (en) | 2021-04-01 | 2021-04-01 | Wafer bonding method and wafer bonding structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113223999A (en) |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010006257A1 (en) * | 1999-09-24 | 2001-07-05 | Chian-Gauh Shih | Method of fabricating a three-dimensional system-on-chip and its structure |
| CN101542701A (en) * | 2008-06-05 | 2009-09-23 | 香港应用科技研究院有限公司 | Bonding method of three-dimensional wafer lamination based on silicon through hole |
| CN101834159A (en) * | 2010-04-23 | 2010-09-15 | 中国科学院上海微系统与信息技术研究所 | BCB-Assisted Bonding for Through-Silicon Via Packaging Manufacturing Process |
| CN102050418A (en) * | 2010-09-30 | 2011-05-11 | 北京大学 | Three-dimensional integrated structure and production methods thereof |
| CN102420200A (en) * | 2011-11-15 | 2012-04-18 | 中国科学院微电子研究所 | Adapter board with metal vertical interconnection structure and method of making same |
| US20130093091A1 (en) * | 2010-10-12 | 2013-04-18 | Peking University | Three-Dimensional Vertical Interconnecting Structure and Manufacturing Method Thereof |
| US20130264720A1 (en) * | 2012-04-09 | 2013-10-10 | Samsung Electronics Co., Ltd. | Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages |
| US20150123270A1 (en) * | 2013-11-06 | 2015-05-07 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the semiconductor device |
| CN105826243A (en) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
| CN106098535A (en) * | 2016-07-12 | 2016-11-09 | 武汉新芯集成电路制造有限公司 | Bonding wafer manufacturing method |
| CN108346588A (en) * | 2017-09-30 | 2018-07-31 | 中芯集成电路（宁波）有限公司 | A kind of wafer scale system packaging method and encapsulating structure |
| CN109243974A (en) * | 2018-08-02 | 2019-01-18 | 中国电子科技集团公司第五十五研究所 | A method of reducing wafer bonding deviation of the alignment |
| CN109860064A (en) * | 2018-12-21 | 2019-06-07 | 中芯集成电路（宁波）有限公司 | A kind of wafer scale system packaging method and encapsulating structure |
| CN110085528A (en) * | 2019-05-31 | 2019-08-02 | 苏州福唐智能科技有限公司 | A kind of laser processing of wafer bonding |
| CN210015853U (en) * | 2019-04-02 | 2020-02-04 | 长鑫存储技术有限公司 | semiconductor interconnect structure |
| US20210090952A1 (en) * | 2019-09-25 | 2021-03-25 | Micromaterials Llc | Fully Self-Aligned Via |
-
2021
- 2021-04-01 CN CN202110358013.6A patent/CN113223999A/en active Pending
Patent Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010006257A1 (en) * | 1999-09-24 | 2001-07-05 | Chian-Gauh Shih | Method of fabricating a three-dimensional system-on-chip and its structure |
| CN101542701A (en) * | 2008-06-05 | 2009-09-23 | 香港应用科技研究院有限公司 | Bonding method of three-dimensional wafer lamination based on silicon through hole |
| CN101834159A (en) * | 2010-04-23 | 2010-09-15 | 中国科学院上海微系统与信息技术研究所 | BCB-Assisted Bonding for Through-Silicon Via Packaging Manufacturing Process |
| CN102050418A (en) * | 2010-09-30 | 2011-05-11 | 北京大学 | Three-dimensional integrated structure and production methods thereof |
| US20130093091A1 (en) * | 2010-10-12 | 2013-04-18 | Peking University | Three-Dimensional Vertical Interconnecting Structure and Manufacturing Method Thereof |
| CN102420200A (en) * | 2011-11-15 | 2012-04-18 | 中国科学院微电子研究所 | Adapter board with metal vertical interconnection structure and method of making same |
| US20130264720A1 (en) * | 2012-04-09 | 2013-10-10 | Samsung Electronics Co., Ltd. | Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages |
| US20150123270A1 (en) * | 2013-11-06 | 2015-05-07 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the semiconductor device |
| CN105826243A (en) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
| CN106098535A (en) * | 2016-07-12 | 2016-11-09 | 武汉新芯集成电路制造有限公司 | Bonding wafer manufacturing method |
| CN108346588A (en) * | 2017-09-30 | 2018-07-31 | 中芯集成电路（宁波）有限公司 | A kind of wafer scale system packaging method and encapsulating structure |
| CN108666264A (en) * | 2017-09-30 | 2018-10-16 | 中芯集成电路（宁波）有限公司 | Wafer scale system encapsulating method and structure |
| CN109243974A (en) * | 2018-08-02 | 2019-01-18 | 中国电子科技集团公司第五十五研究所 | A method of reducing wafer bonding deviation of the alignment |
| CN109860064A (en) * | 2018-12-21 | 2019-06-07 | 中芯集成电路（宁波）有限公司 | A kind of wafer scale system packaging method and encapsulating structure |
| CN210015853U (en) * | 2019-04-02 | 2020-02-04 | 长鑫存储技术有限公司 | semiconductor interconnect structure |
| CN110085528A (en) * | 2019-05-31 | 2019-08-02 | 苏州福唐智能科技有限公司 | A kind of laser processing of wafer bonding |
| US20210090952A1 (en) * | 2019-09-25 | 2021-03-25 | Micromaterials Llc | Fully Self-Aligned Via |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7683459B2 (en) | Bonding method for through-silicon-via based 3D wafer stacking | |
| EP2172089B1 (en) | Method for manufacturing a multilayer wiring element having pin interface | |
| US8030208B2 (en) | Bonding method for through-silicon-via based 3D wafer stacking | |
| CN101379892B (en) | Silicon through hole and pulse laser bonding method for stacking electronic elements based on silicon through hole | |
| US8273603B2 (en) | Interposers, electronic modules, and methods for forming the same | |
| CN106206509B (en) | Electronic package, manufacturing method thereof and substrate structure | |
| CN106935563B (en) | Electronic package, manufacturing method thereof and substrate structure | |
| JP5619236B2 (en) | Connection component with hollow insert and method for manufacturing the same | |
| US6998703B2 (en) | Thin package for stacking integrated circuits | |
| CN101542701B (en) | Bonding method of three-dimensional wafer lamination based on silicon through hole | |
| CN107452689A (en) | The embedded fan-out-type silicon pinboard and preparation method of three-dimensional systematic package application | |
| KR101750713B1 (en) | Interposer with microspring contacts and methods of making and using same | |
| CN109196638A (en) | Barrier layer for the interconnection piece in 3D integrated device | |
| JP2007260866A (en) | Semiconductor device and manufacturing method thereof | |
| JP2006108236A (en) | Method for manufacturing substrate with through electrode | |
| KR20140001210A (en) | Interposers, electronic modules, and methods for forming the same | |
| US10916507B2 (en) | Multiple chip carrier for bridge assembly | |
| US20160126110A1 (en) | Method for manufacturing three-dimensional integrated circuit | |
| JP2021197431A (en) | Manufacturing method of semiconductor device | |
| KR20230161449A (en) | Method of manufacturing a semiconductor device, semiconductor device, integrated circuit element, and method of manufacturing an integrated circuit element | |
| CN114455536B (en) | Wafer-level three-dimensional packaging method and structure of MEMS gas sensor | |
| JPS62219954A (en) | 3D IC manufacturing method | |
| Li et al. | Study of annular copper-filled TSVs of sensor and interposer chips for 3-D integration | |
| CN113223999A (en) | Wafer bonding method and wafer bonding structure | |
| JP7688190B2 (en) | Organic interposer structure, method for fabricating same, and packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210806 |