CN113241937B - Ripple adjustable chip and power chip system - Google Patents
Ripple adjustable chip and power chip system Download PDFInfo
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- CN113241937B CN113241937B CN202110781838.9A CN202110781838A CN113241937B CN 113241937 B CN113241937 B CN 113241937B CN 202110781838 A CN202110781838 A CN 202110781838A CN 113241937 B CN113241937 B CN 113241937B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from DC input or output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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Abstract
本发明的纹波可调芯片及电源芯片系统中，纹波可调芯片包括第一功率管、第二功率管、纹波接收模块、纹波处理模块、步进控制模块、振荡器模块、误差比较模块及逻辑控制模块。通过纹波接收模块实时获取负载电压后输出相对应的纹波电压，通过纹波处理模块实时检测纹波电压的幅值，并将幅值与设计阈值进行比较，在幅值大于设计阈值时通过步进控制模块输出对应的步进频率的步进控制信号，使得振荡器模块自适应地调整输出的振荡电压的振荡频率，从而改变误差比较模块输出的驱动信号的驱动频率，驱使逻辑控制模块调整第一功率管和第二功率管的开关频率，进而降低纹波电压的幅值，直到幅值不超过设计阈值，如此可以向终端用电设备提供平稳的负载电压。
In the ripple adjustable chip and the power supply chip system of the present invention, the ripple adjustable chip includes a first power tube, a second power tube, a ripple receiving module, a ripple processing module, a stepping control module, an oscillator module, an error Comparison module and logic control module. The ripple receiving module obtains the load voltage in real time and outputs the corresponding ripple voltage. The ripple processing module detects the amplitude of the ripple voltage in real time, and compares the amplitude with the design threshold. When the amplitude is greater than the design threshold, pass The stepping control module outputs a stepping control signal corresponding to the stepping frequency, so that the oscillator module adaptively adjusts the oscillation frequency of the output oscillating voltage, thereby changing the driving frequency of the driving signal output by the error comparison module, and driving the logic control module to adjust The switching frequency of the first power tube and the second power tube is further reduced to reduce the amplitude of the ripple voltage until the amplitude does not exceed the design threshold, so that a stable load voltage can be provided to the terminal electrical equipment.
Description
Technical Field
The invention relates to the technical field of power chips, in particular to a ripple adjustable chip and a power chip system.
Background
In the switching power supply chip field, the terminal consumer of buck converter includes single chip module, digital-to-analog conversion chip etc. foretell terminal consumer is the ripple voltage control that requires the power chip system output in the buck converter usually in certain within range, the ripple voltage of output can influence the normal work of terminal consumer excessively, the ripple voltage size of the power chip system output of buck converter depends on inductance value and capacitance value in the LC filter network of output in this buck converter's the power chip system usually.
When the terminal electric devices enter a large-scale mass production process, for the terminal electric devices with the same working voltage, a buck converter configured by a power chip system with a single fixed output voltage (e.g., 3.3V, 5V) is usually used to supply power to the terminal electric devices. The buck converter configured by using the power chip system with a single fixed output voltage can reduce the cost, but inevitably causes the capacitance value of the LC filter network in the power chip system to deviate from the originally designed value after the power chip system is used for a long time. Specifically, after the buck converter is used for a period of time, the capacitance characteristic of the LC filter network in the power chip system changes, which is specifically shown in that a parasitic resistance (ESR) of a capacitor in the LC filter network increases (generally, the amplitude of the change is not severe) with the increase of the service time of the buck converter, so that the ripple voltage output by the power chip system also increases correspondingly, the power supply performance of the buck converter decreases, and the working state of the terminal electric equipment is affected.
In view of this, how to improve the difference of the ripple voltages output by the power chip systems of the respective buck converters and reduce the loss caused in the processing and production links is a problem that designers need to face in consideration of mass production of buck converters with the same supply voltage. Therefore, how to design a chip so that a power chip system designed based on the chip can adaptively adjust the output ripple voltage to improve the power supply performance of the buck converter is a problem to be solved.
Disclosure of Invention
The invention aims to provide a ripple adjustable chip and a power supply chip system, and aims to solve the problem that the ripple voltage output by the power supply chip system in the prior art is increased along with the increase of the working time of the power supply chip system, and the working state of terminal electric equipment is finally influenced.
To solve the above technical problem, according to an aspect of the present invention, the present invention provides a ripple adjustable chip applied in a power chip system, where the ripple adjustable chip includes:
the input end of the first power tube is connected to the input end of the ripple adjustable chip; the output end of the first power tube is connected with the output end of the second power tube and is jointly connected to the output end of the ripple adjustable chip; the input end of the second power tube is grounded;
the ripple receiving module is configured to acquire a load voltage output by the power supply chip system in real time, perform direct current operation on the load voltage to obtain a ripple voltage, and then perform level shift processing on the ripple voltage;
the ripple processing module is configured to acquire the ripple voltage processed by the ripple receiving module in real time, perform low-pass filtering processing on the ripple voltage according to a preset pass frequency, and output a comparison signal after performing comparison operation according to the voltage amplitude of the ripple voltage and a preset design threshold; the comparison signal is confirmed to be valid when the voltage amplitude of the ripple voltage is greater than the design threshold;
the stepping control module is internally provided with a control value and is configured to detect the comparison signal when each pulse of a periodic pulse signal arrives, increase the control value by a stepping value when the comparison signal is detected to be effective, and convert the increased control value into a stepping control signal with a corresponding stepping frequency according to a preset mapping relation and output the stepping control signal;
the oscillator module is configured to acquire the stepping control signal in real time and adjust the oscillation frequency of oscillation voltage output by the oscillator module according to the stepping frequency corresponding to the stepping control signal, wherein the signal waveform of the oscillation voltage is a sawtooth wave;
the error comparison module is configured to acquire the load voltage and the oscillating voltage in real time, generate an error amplification voltage according to the load voltage and an internal preset reference voltage, and output a driving signal according to a comparison value of the error amplification voltage and the oscillating voltage;
the logic control module is respectively connected to the control end of the first power tube and the control end of the second power tube; the logic control module is configured to acquire the driving signal in real time to control the first power tube and the second power tube to be alternately turned on and off at a switching frequency; wherein the logic control module is configured to adaptively adjust the switching frequency according to a driving frequency of the driving signal.
Optionally, the ripple processing module includes a filtering processing unit, and the filtering processing unit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first amplifier, and a second amplifier;
the first end of the first resistor is configured as an input end of the filtering processing unit and used for obtaining the ripple voltage, and the second end of the first resistor is connected to the first end of the second resistor and the first end of the second capacitor at the same time; the second end of the second capacitor is connected to the output end of the first amplifier and is connected with the inverting input end of the first amplifier; a second end of the second resistor is connected with a first end of the first capacitor and then is connected to a non-inverting input end of the first amplifier, and a second end of the first capacitor is grounded; a first end of the third resistor is connected to an output end of the first amplifier, a second end of the third resistor is connected with a first end of the fourth resistor, and a first end of the third capacitor is led out from a common end of the third resistor and the fourth resistor; the second end of the third capacitor is connected to the output end of the second amplifier and is connected with the inverting input end of the second amplifier; a second end of the fourth resistor and a first end of the fourth capacitor are connected and then are jointly connected to a non-inverting input end of the second amplifier, and a second end of the fourth capacitor is grounded; the output of the second amplifier is configured as the output of the filter processing unit.
Optionally, the ripple processing module includes an amplitude threshold comparing unit, where the amplitude threshold comparing unit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first phase shifting subunit, a second phase shifting subunit, a third amplifier, a constant current source, and a first comparator;
the input end of the first phase shifting subunit and the input end of the second phase shifting subunit are commonly connected and then serve as the input end of the amplitude threshold comparison unit, and the input end of the first phase shifting subunit and the input end of the second phase shifting subunit are used for acquiring the ripple voltage after low-pass filtering processing; at least one of the first phase shifting subunit and the second phase shifting subunit is configured to perform phase shifting on the ripple voltage after the low-pass filtering processing, so that the first phase shifting subunit outputs a trough of the ripple voltage at the same time, and the second phase shifting subunit outputs a peak of the ripple voltage; the output end of the first phase shift subunit is connected to the inverting input end of the third amplifier through the sixth resistor, the first end of the fifth resistor is led out from the common end of the sixth resistor and the third amplifier, and the second end of the fifth resistor is connected to the output end of the third amplifier; the output end of the second phase shift subunit is connected to the non-inverting input end of the third amplifier through the eighth resistor, the first end of the seventh resistor is led out from the common end of the eighth resistor and the third amplifier, and the second end of the seventh resistor is grounded; the inverting input end of the first comparator is connected with the output end of the third amplifier, the constant current source and the first end of the ninth resistor are connected and then are jointly connected to the non-inverting input end of the first comparator, the second end of the ninth resistor is grounded, and the output end of the first comparator is configured as the output end of the amplitude-threshold comparison unit.
Optionally, the step control module includes a counter, a pulse generator, a step MAP table, and a step controller;
the pulse generator is used for sending the periodic pulse signal to the counter so that the counter detects the comparison signal when each pulse arrives;
the counter is used for increasing the stepping value from the control value when the comparison signal is effective, and converting the increased control value into a preset binary format for output;
the step MAP table is configured with the step control frequency corresponding to the control value after the self-increment in the preset binary format;
the step controller is configured to output the corresponding step control signal according to the step control frequency.
Optionally, the preset binary system includes a binary system, the initial value of the control value is 0, and the step value is 1.
Optionally, the error comparing module includes a tenth resistor, an eleventh resistor, an error amplifier, a reference voltage source, and a second comparator; a first end of the tenth resistor is configured as an input end of the error comparison module to obtain the load voltage; a second end of the tenth resistor and a first end of the eleventh resistor are connected and then are connected to the inverting input end of the error amplifier, and a second end of the eleventh resistor is grounded; the reference voltage source is connected to the non-inverting input end of the error amplifier to provide the reference voltage; the inverting input end of the second comparator is connected to the output end of the error amplifier, the non-inverting input end of the second comparator is connected to the oscillator module to obtain the oscillating voltage, and the output end of the second comparator is configured as the output end of the error comparison module.
Optionally, the switching frequency is a sum of a preset initial frequency and the stepping frequency.
Based on another aspect of the present invention, the present invention further provides a power chip system, which includes an input capacitor circuit, an output capacitor circuit, an inductor, and the ripple adjustable chip as described above; the first end of the input capacitor circuit is connected to the input end of the ripple adjustable chip, and the second end of the input capacitor circuit is grounded; the first end of the inductor is connected with the output end of the ripple adjustable chip, the second end of the inductor is connected with the first end of the output capacitor circuit, and the second end of the output capacitor circuit is grounded; when the first power tube is started and the second power tube is stopped, the input capacitor circuit, the first power tube, the inductor and the output capacitor circuit form a first loop; when the first power tube is cut off and the second power tube is opened, the second power tube, the inductor and the output capacitor circuit form a second loop.
Optionally, the power chip system includes a clamping capacitor, the ripple adjustable chip is provided with a clamping capacitor end connected to the logic control module, and the clamping capacitor is coupled between the input end of the ripple adjustable power chip and the clamping capacitor end.
In summary, in the ripple adjustable chip and the power chip system provided by the present invention, the ripple adjustable chip includes a first power transistor, a second power transistor, a ripple receiving module, a ripple processing module, a step control module, an oscillator module, an error comparison module, and a logic control module. The invention obtains the load voltage output by the power supply chip system in real time through the ripple receiving module and then outputs the corresponding ripple voltage, detects the amplitude of the ripple voltage in real time through the ripple processing module, compares the amplitude of the ripple voltage with a design threshold value, outputs a step control signal of corresponding step frequency to the oscillator module through the step control module when the amplitude is larger than the design threshold value, so that the oscillator module adaptively adjusts the oscillation frequency of the output oscillation voltage, thereby changing the driving frequency of the driving signal output by the error comparison module, drives the logic control module to adjust the switching frequency of the first power tube and the second power tube after receiving the driving signal, further reduces the amplitude of the ripple voltage until the amplitude does not exceed the design threshold value, thus providing stable load voltage for the terminal electric equipment, and ensuring the consistency of the range of the ripple voltage required by the terminal electric equipment in large-scale batch production and long-term work, the reliability, the practicability and the applicability of the ripple adjustable chip are improved.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention.
Fig. 1 is a schematic diagram of a power chip system according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a ripple adjustable chip according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a ripple processing module of the ripple adjustable chip according to an embodiment of the invention.
Fig. 4 is a schematic diagram of a step control module of a ripple adjustable chip according to an embodiment of the present invention.
In the drawings:
100-a ripple adjustable chip; p1-power input pin; p2-power output pin; p3-clamp capacitor terminal pin; P4-GND terminal pin; p5-feedback input pin; p6-ripple voltage threshold configuration terminal pin;
ca-input capacitance; cb-output capacitance; parasitic resistance-ESR of the output capacitor; cc-clamp capacitance; an L-inductor;
110-ripple receiving module;
120-ripple processing module; STAGE 1-filtering processing unit; r1 — first resistance; r2 — second resistance; r3 — third resistance; r4-fourth resistor; c1 — first capacitance; c2 — second capacitance; c3 — third capacitance; c4-fourth capacitance; 121-a first amplifier; 122-a second amplifier; STAGE 2-amplitude threshold comparison unit; r5-fifth resistor; r6-sixth resistance; r7 — seventh resistor; r8 — eighth resistance; r9 — ninth resistor; 123-a third amplifier; 124-a first phase shifting subunit; 125-a second phase shifting subunit; 126-a constant current source; 127-a first comparator;
130-step control module; 131-a counter; 132-step MAP table; 133-step controller; 134-a pulse generator;
140-an oscillator module;
150-an error comparison module; r10 — tenth resistance; r11 — eleventh resistor; 151-error amplifier; 152-a second comparator; 153-reference voltage source;
160-a logic control module; q1-first power tube; q2-second power tube;
200-an input power module; 300-load module.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, "one end" and "the other end" and "proximal end" and "distal end" generally refer to the corresponding two parts, which include not only the end points, but also the terms "mounted", "connected" and "connected" should be understood broadly, e.g., as a fixed connection, as a detachable connection, or as an integral part; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. Furthermore, as used in the present invention, the disposition of an element with another element generally only means that there is a connection, coupling, fit or driving relationship between the two elements, and the connection, coupling, fit or driving relationship between the two elements may be direct or indirect through intermediate elements, and cannot be understood as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation inside, outside, above, below or to one side of another element, unless the content clearly indicates otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The invention provides a ripple adjustable chip and a power supply chip system, which aim to solve the problem that the ripple voltage output by the power supply chip system in the prior art is increased along with the increase of the working time of the power supply chip system, and finally the working state of terminal electric equipment is influenced.
The ripple tunable chip and the power chip system of the present embodiment are described with reference to the drawings.
As shown in fig. 1, fig. 1 is a schematic diagram of a power chip system according to an embodiment of the present invention, where the power chip system provided by the present invention may be applied to a buck converter, and the power chip system includes an input capacitor circuit, an output capacitor circuit, an inductor L, and a ripple adjustable chip 100; referring to fig. 2, fig. 2 is a schematic diagram of a ripple adjustable chip according to an embodiment of the present invention, a first power tube Q1 and a second power tube Q2 are disposed in the ripple adjustable chip 100, and an input end of the first power tube Q1 is connected to an input end of the ripple adjustable chip 100; the output end of the first power tube Q1 is connected with the output end of the second power tube Q2, and is commonly connected to the output end of the ripple adjustable chip 100; the input end of the second power tube Q2 is grounded; a first end of the input capacitor circuit is connected to the input end of the ripple adjustable chip 100, and a second end of the input capacitor circuit is grounded; a first end of the inductor L is connected to an output end of the ripple adjustable chip 100, a second end of the inductor L is connected to a first end of the output capacitor circuit, and a second end of the output capacitor circuit is grounded; when the first power tube Q1 is turned on and the second power tube Q2 is turned off, the input capacitor circuit, the first power tube Q1, the inductor L and the output capacitor circuit form a first loop; when the first power tube Q1 is turned off and the second power tube Q2 is turned on, the second power tube Q2, the inductor L and the output capacitor circuit form a second loop. Specifically, an input power module 200 may be adopted to provide a power supply voltage to the power supply chip system, a first end of the input power module 200 is connected to a first end of the input capacitor circuit and an input end of the ripple adjustable chip 100, and a second end of the input power module 200 is connected to a second end of the input capacitor circuit; the power supply chip system processes the input power supply voltage and outputs the load voltage to the load module 300 for power supply, the load module 300 may be, for example, a single chip module, a digital-to-analog conversion chip, etc., a first end of the load module 300 is simultaneously connected to a second end of the inductor L and a first end of the output capacitor circuit, and a second end of the load module 300 is connected to a second end of the output capacitor circuit. In the first loop, normal input and output of the power voltage can be realized, and the second loop can be understood as a freewheeling loop, which can continuously supply power to the load module 300 after the first power transistor Q1 is turned off. For the power chip system of this embodiment, the power voltage provided by the input power module 200 is filtered by the input capacitor circuit and then input to the inside of the ripple adjustable chip 100 from the input end of the ripple adjustable chip 100, the controllable pulse power switch voltage is output from the output end of the ripple adjustable chip 100 after being processed by the ripple adjustable chip 100, and the constant load voltage (dc voltage) is output to the load module 300 after being stored in the inductor L and filtered by the output capacitor circuit, so as to satisfy the load carrying characteristics of the load module 300. In this embodiment, the input capacitor circuit may be the input capacitor Ca shown in fig. 1, and the output capacitor circuit may be the output capacitor Cb shown in fig. 1, and of course, in this embodiment, a plurality of input capacitors Ca may be connected in parallel to form the input capacitor circuit, and a plurality of output capacitors Cb may be connected in parallel to form the output capacitor circuit.
The power chip system adopted by the buck converter in the prior art can substantially refer to the circuit structure shown in fig. 1 of the present embodiment, and the structure of each part in the prior art is still described in the naming manner of the present embodiment, for example, the ripple-adjustable chip still represents the corresponding chip in the power chip system in the prior art. When the power supply chip system outputs a load voltage (direct current voltage), it can be understood in a narrow sense that the output ripple voltage is an alternating current component superimposed on a direct current steady quantity, and the load voltage is seen to slightly fluctuate up and down on an oscilloscope, similar to water ripples. The ripple voltage output by the power chip system of the conventional buck converter is mainly determined by the parasitic resistance (equivalent to ESR in fig. 1) of the output capacitor circuit, and specifically, can be expressed by the following formula:
wherein:
ΔVESRrepresents the ripple voltage output by the power supply chip system;
d is the duty ratio of the ripple adjustable chip;
l is the inductance value of the LC filter network (corresponding to the value of L in fig. 1);
VOUT is a fixed output voltage of the ripple adjustable chip (as in the background art, when a terminal electric device enters a large-scale batch production process, for the terminal electric device with the same working voltage, a buck converter configured with a power chip system with a single fixed output voltage (e.g., 3.3V or 5V) is usually used to supply power to the terminal electric device, so as to reduce cost), it should be noted that a load voltage output by the power chip system of this embodiment is constant);
RESRa parasitic resistance ESR (corresponding to a parasitic resistance with the output capacitor Cb in fig. 1) of the output capacitor circuit;
FS is the switching frequency of the first power transistor Q1 and the second power transistor Q2 inside the ripple-adjustable chip, that is, the frequency of the first power transistor Q1 and the second power transistor Q2 which are alternately turned on and off.
According to the formula, when the output voltage is fixed and unchanged, the input voltage of the ripple adjustable chip is also unchanged, the duty ratio D is fixed, the inductor is fixed in the actual working process by welding, the inductance value cannot be changed, and only the parasitic resistance ESR and the switching frequency FS of the output capacitor circuit are variable. After the power supply chip system works for a period of time, the output capacitor circuit will increase its parasitic resistance ESR due to aging or fatigue, and the above formula shows that R isESRAfter the increase, the amplitude of the ripple voltage can be reduced by increasing the value of the switching frequency FS, so that the amplitude of the ripple voltage is within the range of the actual operation requirement.
In view of the above, the present embodiment provides a ripple adjustable chip 100 based on the relationship between the ripple voltage and the parasitic capacitance ESR and the switching frequency FS of the output capacitor circuit, and the ripple adjustable chip 100 is applied to the power supply chip system.
Referring to fig. 1, the ripple adjustable chip 100 further has six pins, which are a power input terminal pin P1, a power output terminal pin P2, a clamp capacitor terminal pin P3, a GND terminal pin P4, a feedback input terminal pin P5, and a ripple voltage threshold configuration terminal pin P6. The function of some of the pins will be described below, and the function of the pin that is not mentioned will be described later with reference to an actual configuration scenario, where the power input terminal pin P1 is used to obtain the power voltage provided by the input power module 200, and the power output terminal pin P2 is used to output the controllable pulse-type power switch voltage (the high level amplitude is the same as the amplitude of the power voltage, and the GND terminal pin P4 is connected to ground) that is processed by the ripple adjustable chip 100 and then output.
The ripple adjustable chip 100 provided in this embodiment is preferably a synchronous rectification power switching power supply integrated circuit chip using an advanced integrated circuit manufacturing process. Referring to fig. 2, in addition to the first power transistor Q1 and the second power transistor Q2 being disposed inside the ripple adjustable chip 100 provided in the present embodiment, the ripple adjustable chip 100 further includes: the ripple receiving module 110, the ripple processing module 120, the step control module 130, the oscillator module 140, the error comparison module 150, and the logic control module 160, which will be described below.
The ripple receiving module 110 in this embodiment is configured to obtain the load voltage output by the power supply chip system in real time, perform dc operation on the load voltage to obtain a ripple voltage VA, and perform level shift processing on the ripple voltage VA. Specifically, the ripple receiving module 110 obtains the load voltage through the feedback input terminal pin P5. The ripple receiving module 110 removes a dc component from the load voltage to obtain an ac component, i.e., a ripple voltage VA, and then level shifts the ripple voltage VA, which is understood to shift a signal curve of the ripple voltage VA longitudinally (generally, to sink) in an oscilloscope, so that a trough of the ripple voltage VA approaches 0 (including being equal to 0).
The ripple processing module 120 in this embodiment is configured to obtain the ripple voltage VA processed by the ripple receiving module 110 in real time, perform low-pass filtering processing on the ripple voltage VA according to a preset pass frequency, and output a comparison signal VB after performing comparison operation according to a voltage amplitude VF of the ripple voltage VA and a preset design threshold VG; when the voltage amplitude VF of the ripple voltage VA is greater than the design threshold VG, the comparison signal VB is determined to be valid. The ripple voltage VA is subjected to low-pass filtering processing, unnecessary burr interference signals can be filtered, a complete waveform of the ripple voltage VA is obtained, and subsequent false actions are avoided. In an exemplary embodiment, the pass frequency for low pass filtering can be set to pass band-3 dB @300KHz, stop band-40 dB @1000KHz, i.e. setting the pass frequency to 300KHz, the signal attenuation is 3 dB; the signal attenuation is set to 40dB when the passing frequency is set to 1000 KHz.
In a specific embodiment, referring to fig. 3, fig. 3 is a schematic diagram of the ripple processing module 120 of the ripple adjustable chip 100 according to an embodiment of the present invention, in which the ripple processing module 120 of the embodiment provides a filtering processing unit STAGE1 for the process of the ripple voltage low-pass filtering processing, and provides an amplitude-threshold comparison unit STAGE2 for the process of comparing the voltage amplitude of the ripple voltage with a preset design threshold. The filter processing unit STAGE1 and the amplitude threshold comparison unit STAGE2 will be explained separately below.
The filtering processing unit STAGE1 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first amplifier 121, and a second amplifier 122; a first end of the first resistor R1 is configured as an input end of a filtering processing unit STAGE1 (that is, an input end of the ripple processing module 120) to obtain the ripple voltage VA (a ripple voltage processed by the ripple receiving module 110), a second end of the first resistor R1 is simultaneously connected to the first end of the second resistor R2 and the first end of the second capacitor C2, a second end of the second capacitor C2 is connected to the output end of the first amplifier 121 and is connected to the inverting input end of the first amplifier, a second end of the second resistor R2 is connected to the first end of the first capacitor C1 and then is connected to the non-inverting input end of the first amplifier 121, and a second end of the first capacitor C1 is grounded; a first end of the third resistor R3 is connected to an output end of the first amplifier 121, a second end of the third resistor R3 is connected to a first end of the fourth resistor R4, a first end of the third capacitor C3 is led out from a common end of the third resistor R3 and the fourth resistor R4, a second end of the third capacitor C3 is connected to an output end of the second amplifier 122 and is connected to an inverting input end of the second amplifier, a second end of the fourth resistor R4 is connected to a first end of the fourth capacitor C4 and then is connected to a non-inverting input end of the second amplifier 122, and a second end of the fourth capacitor C4 is grounded; an output of the second amplifier 122 is configured as an output of the filtering processing unit STAGE 1. The filtering processing unit STAGE1 forms a low-pass filter, and outputs the ripple signal VH after performing low-pass filtering processing on the ripple voltage VA.
The amplitude threshold comparison unit STAGE2 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first phase shift subunit 124, a second phase shift subunit 125, a third amplifier 123, a constant current source 126, and a first comparator 127; wherein, the input terminal of the first phase shifting subunit 124 and the input terminal of the second phase shifting subunit 125 are connected together and then are used as the input terminal of the amplitude threshold comparing unit STAGE2, and are configured to obtain the ripple voltage VA (which can be understood as the ripple signal VH output by the filter processing unit STAGE 1) after being subjected to the low-pass filtering processing, at least one of the first phase shifting subunit 124 and the second phase shifting subunit 125 is configured to perform phase shifting on the ripple voltage VA (which can be understood as the ripple signal VH output by the filter processing unit STAGE 1) after being subjected to the low-pass filtering processing, so that the first phase shifting subunit 124 outputs the trough of the ripple voltage VA at the same time, and the second phase shifting subunit 125 outputs the peak of the ripple voltage VA, that is, at the same time, the first phase shifting subunit 124 outputs the peak of the ripple voltage VA after being subjected to the low-pass filtering processing, the second phase shifting subunit 125 outputs the trough of the ripple voltage VA after the low-pass filtering, which may be further considered as the crest of the ripple signal VH (i.e., the signal obtained after the ripple voltage VA is subjected to the low-pass filtering) output by the first phase shifting subunit 124 at the same time, and the trough of the ripple signal VH (i.e., the signal obtained after the ripple voltage VA is subjected to the low-pass filtering) output by the second phase shifting subunit 125; the output terminal of the first phase shifting subunit 124 is connected to the inverting input terminal of the third amplifier 123 through the sixth resistor R6, and a first terminal of the fifth resistor R5 is led out from the common terminal of the sixth resistor R6 and the third amplifier 123, and a second terminal of the fifth resistor R5 is connected to the output terminal of the third amplifier 123; the output end of the second phase shift subunit 125 is connected to the non-inverting input end of the third amplifier 123 through the eighth resistor R8, and a first end of the seventh resistor R7 is led out from the common end of the eighth resistor R8 and the third amplifier 123, and a second end of the seventh resistor R7 is grounded; the inverting input terminal of the first comparator 127 is connected to the output terminal of the third amplifier 123, the first terminals of the constant current source 126 and the ninth resistor R9 are connected and then commonly connected to the non-inverting input terminal of the first comparator 127, the second terminal of the ninth resistor R9 is grounded, and the output terminal of the first comparator 127 is configured as the output terminal of the amplitude-threshold comparison unit STAGE2 (i.e., the output terminal of the ripple processing module 120). Specifically, the amplitude-threshold comparison unit STAGE2 obtains the ripple voltage VA after low-pass filtering (which can be understood as the ripple signal VH output by the filtering processing unit STAGE 1), and divides the ripple signal VH into two signals (equivalent to duplicating one ripple signal VH) to be respectively transmitted to the first phase shifting subunit 124 and the second phase shifting subunit 125, at least one of the first phase shifting subunit 124 and the second phase shifting subunit 125 is used for respectively outputting a signal VD and a signal VE after performing phase shifting on the respective corresponding ripple signal VH, so that at the same moment the signal VD output by the first phase shifting subunit 124 corresponds to the trough of the ripple signal VH, the signal VE output by the second phase shifting subunit 125 corresponds to the peak of the ripple signal VH, then, the third amplifier 123 performs differential amplification operation on the signal VE and the signal VD to obtain the amplitude VF of the ripple voltage (i.e., peak-to-valley reduction). In this embodiment, the first phase shifting subunit 124 and the second phase shifting subunit 125 both perform phase shifting processing on the input ripple signal VH, and make the phase of the output signal VE lag behind the phase of the signal VD. In addition, the constant current source 126 outputs a constant current, and the design threshold VG is configured by the product of the constant current and the ninth resistor R9. Preferably, referring to fig. 1, the ninth resistor R9 is externally disposed on the ripple adjustable chip 100, so that a technician can adjust the resistance of the ninth resistor R9 to adjust the size of the design threshold VG.
In an exemplary embodiment, the threshold VG = r9x0.01mv/Ω is designed, the ripple voltage VA of the output of the power supply chipset is set not to exceed 150mV, and the resistance value of the ninth resistor R9 is configured to be 15K Ω accordingly. In practice, the output ripple voltage VA cannot be infinitely reduced, and too small a ripple voltage VA means that the parasitic capacitance ESR is too small, which may cause other derivative problems in the circuit, and the ripple voltage VA is adjusted moderately, typically between 80mV and 200 mV.
The step control module 130 in this embodiment is provided with a control value therein, and the step control module 130 is configured to detect the comparison signal VB when each pulse of a periodic pulse signal arrives, increase the control value by one step value when detecting that the comparison signal VB is valid, convert the increased control value into a step control signal VC with a corresponding step frequency according to a preset mapping relationship, and output the step control signal VC. It should be understood herein that the detection of the comparison signal VB at the arrival of each pulse of the periodic pulse signal refers to the detection of the comparison signal VB at the time when the periodic pulse signal is active at a high level of each pulse. Specifically, the control value after the self-increment is referred to as the operation value, and it is set that when the first pulse arrives, the comparison signal VB is detected to be valid, then the operation value = the control value + the step value, and the step frequency of the step control signal VC corresponds to the frequency to which the operation value is mapped at this time; when the second pulse arrives, it is still detected that the comparison signal VB is valid, then the operating value = control value + step value x2, the step frequency of the step control signal VC corresponds to the frequency to which the operating value is mapped at this time; at the arrival of the third pulse, it is still detected that the comparison signal VB is valid, then the operating value = control value + step value x3, the step frequency of the step control signal VC corresponding to the frequency … … to which the operating value is mapped at this time. The frequency of the periodic pulse signal is not illustrated here, and can be set by those skilled in the art according to actual requirements.
In an embodiment, please refer to fig. 4, fig. 4 is a schematic diagram of a step control module of a ripple adjustable chip according to an embodiment of the present invention, where the step control module 130 includes a counter 131, a pulse generator 134, a step MAP table 132, and a step controller 133; the pulse generator 134 is used for sending the periodic pulse signal to the counter 131, so that the counter 131 detects the comparison signal VB when each pulse arrives; the counter 131 is configured to increment the step value from the control value when the comparison signal VB is valid, and convert the control value after the increment into a preset binary format for output, that is, the counter 131 can count the valid times of the comparison signal; the step MAP table 132 is configured with the step control frequency corresponding to the control value (in combination with the foregoing, it may be understood as an operation value) after self-increment in the preset binary format, that is, it may be understood that a mapping relationship between the control value after self-increment and the step frequency is represented by a pre-configured MAP table; the step controller 133 is configured to output the corresponding step control signal VC according to the step control frequency.
In an exemplary embodiment, the predetermined binary is set to binary, the initial value of the control value is 0, and the step value is 1. Specifically, when each pulse arrives, the counter 131 detects whether the comparison signal is valid, and when the control value is an initial value 0, the step MAP table 132 supplies the step controller 133 with a step frequency corresponding to binary 0000; when the comparison signal is detected to be valid for the first time, the control value is changed from 1 to 1 for the first time, and the step MAP table 132 provides the step controller 133 with a step frequency corresponding to the binary value 0001; when the comparison signal is detected to be valid for the second time, the control value is changed from self-increment 1 to 2 for the second time, and the step MAP table 132 provides the step frequency corresponding to binary 0010 to the step controller 133; when the comparison signal is detected to be valid for the third time, the control value is changed from 1 to 3 for the third time, and the step MAP table 132 provides the step frequency … … corresponding to binary value 0011 to the step controller 133. Then, the step controller 133 outputs a corresponding step control signal according to each step frequency. In this embodiment, the frequency of the step control signal is set as the step frequency. Further, a table of mapping relationship between the converted control value after the self-increment and the step frequency is provided in this example, please refer to table 1, in which Ft represents the step frequency.
TABLE 1 binary step MAP Table
| VC_3 | VC_2 | VC_1 | VC_0 | Ft（ KHz ） |
| 0 | 0 | 0 | 0 | Negative value ≦ Ft<3.3 |
| 0 | 0 | 0 | 1 | 3.3≤Ft<7.6 |
| 0 | 0 | 1 | 0 | 7.6≤Ft<10.3 |
| 0 | 0 | 1 | 1 | 10.3≤Ft<13.2 |
| 0 | 1 | 0 | 0 | 13.2≤Ft<16.3 |
| 0 | 1 | 0 | 1 | 16.3≤Ft<19.9 |
| 0 | 1 | 1 | 0 | 19.9≤Ft<22.7 |
| 0 | 1 | 1 | 1 | 22.7≤Ft<25.1 |
| 1 | 0 | 0 | 0 | 25.1≤Ft<27.5 |
| 1 | 0 | 0 | 1 | 27.5≤Ft<29.7 |
| 1 | 0 | 0 | 0 | 29.7≤Ft<31.9 |
| 1 | 0 | 0 | 1 | 31.9≤Ft<34.0 |
| 1 | 1 | 0 | 0 | 34.0≤Ft<36.0 |
| 1 | 1 | 0 | 1 | 36.0≤Ft<37.8 |
| 1 | 1 | 1 | 0 | 37.8≤Ft<39.7 |
| 1 | 1 | 1 | 1 | 39.7≤Ft |
It should be noted that, in an actual engineering, a batch of ripple adjustable chips are usually produced in a large scale or in a large batch, and due to objective conditions such as a production process and process parameters, the step frequencies corresponding to the control values after the respective increments in each ripple adjustable chip are different and approximately present a normal distribution, so a range is generally set for the step frequencies of the ripple adjustable chips in a large batch, and values are taken from the range during actual calculation, and errors of calculation results can be ignored, so that the step frequency in table 1 is given as a range, and the range is applied to actual production.
In other embodiments, the preset scale may also be a quaternary scale, an octal scale or a hexadecimal scale, the initial value of the control value may be 1, 2, 3 … …, and the step value may be 1, 2, 3 … …, which may be configured according to practical situations by those skilled in the art and will not be described herein.
The oscillator module 140 in this embodiment is configured to obtain the step control signal VC in real time, and adjust an oscillation frequency of an oscillation voltage output by the oscillator module according to the step frequency corresponding to the step control signal VC, where a signal waveform of the oscillation voltage is a sawtooth wave. Specifically, the oscillation frequency increases correspondingly with an increase in the step frequency. The oscillator module 140 may be an oscillator or an oscillating circuit, which is not limited by the invention.
The error comparing module 150 in this embodiment is configured to obtain the load voltage and the oscillating voltage in real time, generate an error amplifying voltage VEA according to the load voltage and an internal preset reference voltage VREF, and output a driving signal according to a comparison value between the error amplifying voltage VEA and the oscillating voltage.
In one specific implementation, the error comparison module 150 includes a tenth resistor R10, an eleventh resistor R11, an error amplifier 151, a reference voltage source 153, and a second comparator 152; a first terminal of the tenth resistor R10 is configured as an input terminal of the error comparison module 150 to obtain the load voltage; a second end of the tenth resistor R10 and a first end of the eleventh resistor R11 are connected and then commonly connected to the inverting input terminal of the error amplifier 151, and a second end of the eleventh resistor R11 is grounded; the reference voltage source 153 is connected to the non-inverting input terminal of the error amplifier 151 to provide the reference voltage; the inverting input terminal of the second comparator 152 is connected to the output terminal of the error amplifier 151, the non-inverting input terminal of the second comparator 152 is connected to the oscillator module 140 to obtain the oscillating voltage, and the output terminal of the second comparator 152 is configured as the output terminal of the error comparison module 150. Specifically, the load voltage is divided and detected in real time through the tenth resistor R10 and the eleventh resistor R11 to form a load detection voltage VFB, the error amplifier 151 performs differential amplification operation on the load detection voltage VFB and the reference voltage VREF provided by the reference voltage source 153 to output an error amplification voltage VEA, and the error amplification voltage VEA is also a direct current signal because the load voltage is a direct current signal; then, the error amplified voltage VEA and the oscillating voltage provided by the oscillator module 140 are differentiated by the second comparator 152 to output the driving signal, and since the error amplified voltage VEA is a dc signal and the waveform of the oscillating voltage is a sawtooth wave, the waveform of the driving signal is a square wave, it can be understood that the frequency of the square wave corresponds to (is equal to) the frequency of the oscillating voltage.
The logic control module 160 in this embodiment is respectively connected to the control terminal of the first power transistor Q1 and the control terminal of the second power transistor Q2; the logic control module 160 is configured to obtain the driving signal in real time to control the operating state of the first power transistor Q1 and the operating state of the second power transistor Q2, so that the first power transistor Q1 and the second power transistor Q2 are alternately turned on and off at a switching frequency; wherein the logic control module 160 is configured to adaptively adjust the switching frequency according to the driving frequency of the driving signal. Specifically, the logic control module 160 obtains the driving signal, and adjusts the switching frequency of the first power transistor Q1 and the second power transistor Q2 according to the driving frequency of the driving signal, so as to adjust the ripple voltage according to the foregoing formula. Referring to fig. 1, the setting logic control module 160 of the present embodiment adjusts the alternate on and off of the two power transistors according to the driving frequency of the driving signal, which can be considered as a real-time value of the switching frequency being equal to a real-time value of the driving frequency (square wave frequency).
In an exemplary embodiment, the first power transistor Q1 is a PMOS transistor, the input terminal of the first power transistor Q1 is a source terminal of the PMOS transistor, the output terminal of the first power transistor Q1 is a drain terminal of the PMOS transistor, and the control terminal of the first power transistor Q1 is a gate terminal of the PMOS transistor; the second power tube Q2 is an NMOS tube, the output end of the second power tube Q2 is the drain of the NMOS tube, the input end of the second power tube Q2 is the source of the NMOS tube, and the control end of the second power tube Q2 is the gate of the NMOS tube. Further, the logic control module 160 sends the control signal to the first power transistor Q1 as a first control signal, and sends the control signal to the second power transistor Q2 as a second control signal, so that the first control signal and the second control signal are non-overlapping in order to avoid the simultaneous turn-on of the first power transistor Q1 and the second power transistor Q2. When the first control signal is at a low level, the voltage of the first control signal is lower than the source voltage of the first power tube Q1, the absolute value of the voltage difference between the grid source and the grid source is greater than the minimum starting voltage of the first power tube Q1, the second control signal is at a low level, and the voltage difference between the grid source and the grid source is less than the minimum starting voltage of the second power tube Q2, so that the first power tube Q1 is started, and the second power tube Q2 is cut off; the first control signal is at high level, the absolute value of the difference between the first control signal and the source voltage of the first power tube Q1 is smaller than the minimum turn-on voltage of the first power tube Q1, the second control signal is at high level, the voltage of the second control signal is higher than the source voltage of the second power tube Q2, and the voltage difference between the gate and the source is larger than the minimum turn-on voltage of the second power tube Q2, so that the first power tube Q1 is turned off, and the second power tube Q2 is turned on.
In this embodiment, the switching frequency is the sum of the preset initial frequency and the step frequency, and when the switching frequency is set to be equal to the driving frequency, the oscillation frequency is actually equal to the sum of the preset initial frequency and the step frequency. Specifically, after detecting that the comparison signal VB is valid, the switching frequency is equal to the preset initial frequency plus the step frequency corresponding to the self-increased control value.
In an exemplary embodiment, please refer to table 1 in combination, the preset initial frequency is set to 150KHz, the control value is 0 at this time, the range of the step frequency corresponding to the binary conversion is between a negative value and 3.3KHz (the step frequency is 0), the switching frequency is equal to 150KHz at this time, that is, the first power transistor Q1 and the second power transistor Q2 are alternately turned on and off at 150KHz at the beginning stage; after the comparison signal VB is detected to be effective for the first time, the switching frequency is equal to 150KHz plus the stepping frequency (between 3.3KHz and 7.6 KHz) corresponding to binary conversion with the control value of 1; after the comparison signal VB is detected to be effective for the second time, the switching frequency is equal to 150KHz plus the stepping frequency (the value between 7.6KHz and 10.3 KHz) … … corresponding to the binary conversion of which the control value is 2
As a preferable solution of this embodiment, the power chip system includes a clamping capacitor Cc, the ripple adjustable chip 100 is provided with a clamping capacitor terminal (a clamping capacitor terminal pin P3) connected to the logic control module 160, and the clamping capacitor Cc is coupled between the input terminal of the ripple adjustable chip 100 and the clamping capacitor terminal. The clamp capacitor Cc, which has one end connected to the power input terminal pin P1 and the other end connected to the logic control module 160 through the clamp capacitor terminal pin P3, provides a gate-to-source driving Voltage (VGS) for an internal power transistor (e.g., a P-type metal-oxide-semiconductor transistor (PMOS transistor)). Referring to fig. 1, the clamping capacitor is externally disposed on the ripple adjustable chip 100, the first power transistor Q1 is a PMOS transistor, and the clamping capacitor Cc provides a stable voltage for turning on the first power transistor Q1 through a clamping capacitor terminal pin P3.
The specific working principle of the ripple adjustable chip 100 of this embodiment is as follows:
the ripple receiving module 110 detects the load voltage of the power supply chip system in real time and processes the load voltage to obtain a ripple voltage VA; obtaining an amplitude VF of the ripple voltage through the ripple processing module 120, comparing the amplitude VF with a preset design threshold VG, and outputting a comparison signal VB, where after the power chip system operates for a period of time, a parasitic resistance ESR of the output capacitor gradually increases, so as to increase the ripple voltage VA, and after the ripple processing module 120 detects that the amplitude VF of the ripple voltage is greater than the design threshold VG, the comparison signal VB is valid (for example, it may be considered as a high-level valid), so as to adjust a step frequency of the step control signal VC output by the step control module 130, and further adjust an oscillation frequency of the oscillation voltage provided by the oscillator module 140, specifically, after the comparison signal VB is valid, the step frequency is increased to a frequency corresponding to the control value after the control value is first self-increased, and the oscillation frequency is correspondingly increased, so as to increase the switching frequency and reduce the ripple voltage VA; after the ripple voltage VA is reduced for the first time, it is still detected that the amplitude VF is greater than the design threshold VG, that is, the comparison signal VB is still valid, then the step control frequency is increased to a frequency corresponding to the control value after the second self-increase, the switching frequency is correspondingly increased, the ripple voltage VA is reduced for the second time … …, the process is circulated until the amplitude VF of the ripple voltage is detected not to exceed the design threshold VG, and the comparison signal VB is considered to be invalid.
In addition, it should be noted that, in practical engineering applications, the control value cannot increase by itself all the time, so that the ripple voltage VA is smaller than a certain value, which may cause other derivative problems to the circuit. When the control value is increased to a certain maximum value, the amplitude VF of the ripple voltage is still greater than the design threshold VG, then the technician may consider that the output capacitor Cb is already in the aging stage, and if the output capacitor Cb is still used, the operation of the terminal electric device may be unstable, and may consider replacing the original output capacitor Cb with a new one. That is, the ripple adjustable chip 100 of this embodiment not only can adjust the ripple voltage VA, but also can detect the state lifetime of the output capacitor Cb. To explain further, referring to table 1, the binary step is 16 bits, after the ripple voltage VA is stepped down by the previous fifteen times, the ripple processing module 120 still detects that the amplitude VF of the ripple voltage is greater than the design threshold VG at the sixteenth time, at this time, the step frequency is increased to the maximum value, the corresponding switching frequency is also the maximum value, and the first power transistor Q1 and the second power transistor Q2 are driven to operate at the maximum switching frequency at this time; the ripple processing module 120 still detects that the amplitude VF of the ripple voltage is greater than the design threshold VG at the seventeenth time, at this time, because there is no corresponding step frequency output, the switching frequency is maintained at the maximum switching frequency corresponding to the sixteenth detection output, the ripple voltage VA will not be reduced, the ripple voltage VA output thereafter will be maintained at the value reduced after the sixteenth detection, and the technician may consider to update the output capacitor Cb.
In summary, in the ripple adjustable chip and the power chip system provided by the present invention, the ripple adjustable chip includes a first power transistor, a second power transistor, a ripple receiving module, a ripple processing module, a step control module, an oscillator module, an error comparison module, and a logic control module. The invention obtains the load voltage output by the power supply chip system in real time through the ripple receiving module and then outputs the corresponding ripple voltage, detects the amplitude of the ripple voltage in real time through the ripple processing module, compares the amplitude of the ripple voltage with a design threshold value, outputs a step control signal of corresponding step frequency to the oscillator module through the step control module when the amplitude is larger than the design threshold value, so that the oscillator module adaptively adjusts the oscillation frequency of the output oscillation voltage, thereby changing the driving frequency of the driving signal output by the error comparison module, drives the logic control module to adjust the switching frequency of the first power tube and the second power tube after receiving the driving signal, further reduces the amplitude of the ripple voltage until the amplitude does not exceed the design threshold value, thus providing stable load voltage for the terminal electric equipment, and ensuring the consistency of the range of the ripple voltage required by the terminal electric equipment in large-scale batch production and long-term work, the reliability, the practicability and the applicability of the ripple adjustable chip are improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
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| CN101931334A (en) * | 2009-06-18 | 2010-12-29 | 快捷韩国半导体有限公司 | Frequency modulation controller, switch mode power supply, and switching operation frequency modulation method |
| CN105958820A (en) * | 2016-06-07 | 2016-09-21 | 广东希荻微电子有限公司 | Control method of hysteresis controller in PWM and PFM modes |
| CN112072977A (en) * | 2020-08-10 | 2020-12-11 | 南京航空航天大学 | A High Efficiency Low Ripple Frequency Conversion Modulation Method |
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| CN101931334A (en) * | 2009-06-18 | 2010-12-29 | 快捷韩国半导体有限公司 | Frequency modulation controller, switch mode power supply, and switching operation frequency modulation method |
| CN105958820A (en) * | 2016-06-07 | 2016-09-21 | 广东希荻微电子有限公司 | Control method of hysteresis controller in PWM and PFM modes |
| CN112072977A (en) * | 2020-08-10 | 2020-12-11 | 南京航空航天大学 | A High Efficiency Low Ripple Frequency Conversion Modulation Method |
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