CN113257894A - GaN-based HEMT chip with high conduction efficiency and preparation method thereof - Google Patents
GaN-based HEMT chip with high conduction efficiency and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims abstract description 52
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims description 54
- 239000002184 metal Substances 0.000 claims description 54
- 230000008569 process Effects 0.000 claims description 45
- 238000000151 deposition Methods 0.000 claims description 30
- 238000001259 photo etching Methods 0.000 claims description 26
- 238000002955 isolation Methods 0.000 claims description 10
- 238000000206 photolithography Methods 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000002994 raw material Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 10
- 229910002601 GaN Inorganic materials 0.000 description 89
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 71
- 230000015556 catabolic process Effects 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
- H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
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Abstract
本发明公开了一种高导电效率的GaN基HEMT芯片及其制备方法，包括硅基衬底，外延层，所述外延层包括GaN外延层和AlGaN外延层，所述GaN外延层表面均匀开设有沟槽，所述AlGaN外延层固定连接于GaN外延层表面开设的沟槽中，其中，所述GaN外延层固定连接于硅基衬底顶端表面；本发明通过采用GaN外延层刻蚀沟槽的方法实现了凹凸不平的AlGaN/GaN外延层设计，增加了AlGaN外延层和GaN外延层接触面积，增加了外延层中的二维电子气密度，提高了芯片导通的电流密度，提高了GaN基HEMT芯片的导电效率；同时该设计也增加了AlGaN外延层和GaN外延层接触面积，增加了外延层中的二维电子气面积，在兼顾了芯片的耐压能力下，该设计可节省部分芯片面积，可降低GaN基HEMT芯片的成本。
The invention discloses a GaN-based HEMT chip with high electrical conductivity and a preparation method thereof, comprising a silicon-based substrate and an epitaxial layer, wherein the epitaxial layer includes a GaN epitaxial layer and an AlGaN epitaxial layer, and the surface of the GaN epitaxial layer is uniformly opened with The AlGaN epitaxial layer is fixedly connected to the trench opened on the surface of the GaN epitaxial layer, wherein the GaN epitaxial layer is fixedly connected to the top surface of the silicon base substrate; the present invention uses the GaN epitaxial layer to etch the grooves. The method realizes the design of the uneven AlGaN/GaN epitaxial layer, increases the contact area between the AlGaN epitaxial layer and the GaN epitaxial layer, increases the two-dimensional electron gas density in the epitaxial layer, improves the current density of the chip conduction, and improves the GaN base layer. The conductive efficiency of the HEMT chip; at the same time, the design also increases the contact area between the AlGaN epitaxial layer and the GaN epitaxial layer, and increases the two-dimensional electron gas area in the epitaxial layer. Taking into account the voltage withstand capability of the chip, this design can save some chips. area, which can reduce the cost of GaN-based HEMT chips.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a GaN-based HEMT chip with high conduction efficiency and a preparation method thereof.
Background
Silicon power MOSFETs offer many advantages to circuit designers, making them an obvious choice for many applications. It provides high switching speed and low on-resistance, unlike previous bipolar transistors, MOSFETs are not subject to thermal runaway. Further advances in manufacturing technology have made it possible to use devices with multiple transistors in parallel in a vertical configuration, further reducing on-resistance.
Over the course of decades, manufacturers have developed improvements to the basic design, setting new standards for on-resistance and breakdown voltage. However, these parameters often require compromises with each other in the MOSFET design. Techniques that increase the breakdown voltage tend to push the on-resistance high. Accordingly, competing devices such as Insulated Gate Bipolar Transistors (IGBTs) have been developed whose applications require higher breakdown voltage ratings than MOSFETs.
One option is to replace the material. Gallium nitride (GaN) and silicon carbide are potential alternatives to silicon, which can support a large increase in breakdown voltage without affecting on-resistance due to the higher band gap of these materials. Both SiC and GaN have higher critical electric field strengths than silicon, giving them a superior relationship between on-resistance and breakdown voltage. This allows the device to be made smaller and the electrical terminals to be more closely tied together for a given breakdown voltage requirement.
AlGaN/GaN HEMTs are representative of GaN-based devices, and have high efficiency due to the characteristics of direct band gap and wide band gap (3.4eV), high thermal conductivity and high-temperature radiation resistance, and can be applied to severe environments. Because AlGaN/GaN HEMTs which are mainstream at present are all grown along a Ga surface, because the forbidden bandwidths of AlGaN and GaN materials are different, the forbidden bandwidth of AlGaN is higher than that of GaN, the conduction band bottoms of AlGaN and GaN have a band step difference, the band step difference of the conduction band and a large amount of positive charges at the interface analyzed above can bend the energy band at the conduction band bottom, and the energy band bending can form a two-dimensional potential well at the heterojunction interface. This two-dimensional potential well will confine the previously discussed polarization-induced electrons in the well in only two dimensions along a plane parallel to the abrupt junction interface, and is therefore referred to as a two-dimensional electron gas (2 DEG). Therefore, in the Al (Ga) N/GaN abrupt heterojunction structure, even if the AlGaN barrier layer is not doped at all, the surface density of the induced 2DEG can be as high as 2 x 1013cm < -2 > by virtue of the huge amount of polarized positive charges.
However, when the AlGaN/GaN HEMT device is subjected to a large gate voltage bias during operation, the energy band of the AlGaN barrier is pulled low, and the 2DEG at the heterojunction interface directly crosses the barrier and enters the AlGaN barrier layer to move through tunneling or thermal excitation.
Disclosure of Invention
The invention aims to provide a GaN-based HEMT chip with high conductive efficiency and a preparation method thereof, wherein the GaN-based HEMT chip has the advantages that on the premise of the same chip area, the voltage resistance of the chip is considered, the conductive efficiency of the chip is improved, and the cost of the chip can be reduced.
In order to achieve the purpose, the invention provides the following technical scheme: a high conduction efficiency GaN-based HEMT chip, comprising:
a silicon-based substrate;
the epitaxial layer comprises a GaN epitaxial layer and an AlGaN epitaxial layer, grooves are uniformly formed in the surface of the GaN epitaxial layer, and the AlGaN epitaxial layer is fixedly connected in the grooves formed in the surface of the GaN epitaxial layer;
and the GaN epitaxial layer is fixedly connected to the top end surface of the silicon-based substrate.
Preferably, the AlGaN epitaxial layer surface is formed with a P-GaN Gate, a source contact and a drain contact by deposition, photolithography and other processes.
Preferably, the AlGaN epitaxial layer forms a source contact hole and a drain contact hole through the first metal layer and the second metal layer.
Preferably, the AlGaN epitaxial layer is formed by an isolation oxide layer through an implantation process.
Preferably, a first insulating layer is deposited on the P-GaN Gate, the source contact and the drain contact.
Preferably, the surface of the P-GaN Gate is fixedly connected with a Gate metal, and a second insulating layer is deposited on the surface of the Gate metal.
Preferably, a third insulating layer is deposited on the surface of the first metal layer, and a passivation layer is arranged on the surface of the second metal layer.
Preferably, the grooves are uniformly distributed on the surface of the GaN epitaxial layer.
Preferably, the depth of the groove on the surface of the GaN epitaxial layer is less than 20 nm.
A preparation method of a GaN-based HEMT chip with high conduction efficiency comprises the following steps:
s1, selecting a raw material silicon-based substrate as preparation;
s2, growing a GaN epitaxial layer on the silicon-based substrate, wherein the thickness of the GaN epitaxial layer is about 1-2um, and performing a first photoetching process on the surface of the GaN epitaxial layer to form uniform grooves;
s3, growing an AlGaN epitaxial layer on the surface of the GaN epitaxial layer, wherein uneven GaN epitaxial layer and AlGaN epitaxial layer designs are formed due to the grooves;
s4, depositing doped P-GaN on the AlGaN epitaxial layer and performing a second photoetching Process (PG) to form P-GaN Gate so as to form an E-mode GaN-based device;
s5, depositing Ohmic Contact metal on the AlGaN epitaxial layer and carrying out a third photoetching process (OC) to form a source Contact and a drain Contact;
s6, performing a fourth photoetching process (IS) on the AlGaN epitaxial layer, forming an isolation oxide layer through an injection process, and depositing a first insulating layer on the P-GaN Gate, the source contact and the drain contact as a unit cell isolation function;
s7, carrying out a fifth photoetching process (GS) on the first insulating layer to expose the P-GaN Gate so as to lead out the grid electrode;
s8, depositing metal on the surface of the chip, carrying out a sixth photoetching process (GT) at the position of the P-GaN Gate to form Gate metal, and leading out the Gate through the Gate metal;
s9, depositing a second insulating layer on the gate metal and performing a seventh photolithography process (V0) to expose the source contact and the drain contact;
s10, depositing a first metal layer on the surface of the chip, carrying out an eighth photoetching process (M1), and leading out the source contact and the drain contact through the first metal layer;
s11, depositing a third insulating layer on the surface of the chip and performing a ninth photolithography process (V1) to expose the first metal layer on the source and the drain;
s12, depositing a second metal layer on the surface of the chip, performing a tenth photoetching process (M2), and leading out the source metal and the drain metal;
and S13, depositing a passivation layer on the surface of the chip, performing a tenth photoetching process (TP), forming a chip front surface protection layer, and exposing the routing areas of the grid electrode, the source electrode and the drain electrode to obtain the GaN-based HEMT chip with high conduction efficiency.
Compared with the prior art, the invention has the beneficial effects that:
1. on the premise of the same chip area, the invention improves the current density of the chip conduction, improves the chip conduction efficiency and simultaneously reduces the chip cost under the consideration of the voltage endurance capability of the chip.
2. According to the invention, the grooves are uniformly formed on the surface of the GaN epitaxial layer, and the growth of the ALGaN epitaxial layer is carried out after the grooves are etched, so that the uneven AlGaN/GaN epitaxial layer design is formed, the two-dimensional electron gas density of the interface of the AlGaN epitaxial layer and the GaN epitaxial layer is increased, the current density of the chip conduction is improved, and the conduction efficiency of the GaN-based HEMT chip is improved.
3. According to the invention, the uneven AlGaN/GaN epitaxial layer design is realized by adopting the method of etching the groove on the GaN epitaxial layer, the contact area of the AlGaN epitaxial layer and the GaN epitaxial layer is increased, the two-dimensional electron gas area in the epitaxial layer is increased, and the design can save part of the chip area and reduce the cost of the GaN-based HEMT chip under the consideration of the pressure resistance of the chip.
Drawings
FIG. 1 is a schematic view of the overall structure of the present invention;
fig. 2 is a partial structural schematic diagram of the present invention.
In the figure: a 10-silicon based substrate; 20-GaN epitaxial layer; 21-isolation oxide layer; 22-a trench; a 30-AlGaN epitaxial layer; 31-source contact; 32-drain contact; 33-P-GaN Gate; 34-gate metal; 40-a first insulating layer; 50-a second insulating layer; 60-a first metal layer; 70-a third insulating layer; 80-a second metal layer; 90-a passivation layer; 91-source contact hole; 92-a drain contact hole.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
referring to fig. 1-2, the present invention provides a technical solution: a high conduction efficiency GaN-based HEMT chip, comprising: a silicon-based substrate 10 and an epitaxial layer.
The epitaxial layer comprises a GaN epitaxial layer 20 and an AlGaN epitaxial layer 30, grooves 22 are uniformly formed in the surface of the GaN epitaxial layer 20, and the AlGaN epitaxial layer 30 is fixedly connected to the grooves 22 formed in the surface of the GaN epitaxial layer 20.
In this embodiment, specifically, the trenches 22 are uniformly distributed on the surface of the GaN epitaxial layer 20.
In this embodiment, specifically, the depth of the trench 22 on the surface of the GaN epitaxial layer 20 is less than 20 nm.
Furthermore, the GaN epitaxial layer 20 adopts the groove 22 design to increase the two-dimensional electron gas density of the AlGaN/GaN interface, improve the current density of the chip conduction, and improve the conduction efficiency of the GaN-based HEMT chip; meanwhile, the design also increases the contact area of the AlGaN epitaxial layer and the GaN epitaxial layer, increases the two-dimensional electron gas area in the epitaxial layer, and can save part of the chip area and reduce the cost of the GaN-based HEMT chip under the consideration of the voltage endurance capability of the chip.
Wherein, the GaN epitaxial layer 20 is fixedly connected to the top surface of the silicon-based substrate 10.
The AlGaN epitaxial layer 30 is formed with a P-gan gate33, a source contact 31, and a drain contact 32 by deposition, photolithography, and other processes.
Further, the grooves 22 are uniformly formed in the whole surface of the GaN epitaxial layer 20, and it can be seen that the GaN epitaxial layer 20, the AlGaN epitaxial layer 30, the P-GaN Gate33, the source contact 31 and the drain contact 32 are all designed to be the uniform grooves 22, so that the two-dimensional electron gas density between the GaN epitaxial layer 20 and the AlGaN epitaxial layer 30 is increased, the on-current density is improved, and the conduction efficiency of the E-mode GaN-based HEMT chip is improved while the Gate control speed and the source and drain conduction speeds are ensured.
Wherein the AlGaN epitaxial layer 30 forms a source contact hole 91 and a drain contact hole 92 through the first metal layer 60 and the second metal layer 80.
Wherein, the AlGaN epitaxial layer 30 forms an isolation oxide layer 21 through an implantation process.
Wherein a first insulating layer 40 is deposited on the P-GaN Gate33, the source contact 31 and the drain contact 32.
The surface of the P-GaN Gate33 is fixedly connected with a Gate metal 34, and a second insulating layer 50 is deposited on the surface of the Gate metal 34.
Wherein, a third insulating layer 70 is deposited on the surface of the first metal layer 60, and a passivation layer 90 is disposed on the surface of the second metal layer 80.
According to the embodiment, the grooves are uniformly formed in the surface of the GaN epitaxial layer, the growth of the ALGaN epitaxial layer is carried out after the grooves are etched, the uneven AlGaN/GaN epitaxial layer design is formed, the two-dimensional electron gas density of the interface of the AlGaN epitaxial layer and the GaN epitaxial layer is increased, the current density of the conduction of the chip is improved, and the conduction efficiency of the GaN-based HEMT chip is improved; meanwhile, the contact area of the AlGaN epitaxial layer and the GaN epitaxial layer is increased, the two-dimensional electron gas area in the epitaxial layer is increased, part of the area of the chip can be saved by the design under the condition of considering the voltage endurance capability of the chip, and the cost of the GaN-based HEMT chip can be reduced.
The flow sheet process steps of the embodiment:
referring to fig. 1-2, the present invention provides a technical solution: a preparation method of a GaN-based HEMT chip with high conduction efficiency comprises the following steps:
s1, selecting the raw material silicon-based substrate 10 as preparation;
s2, growing a GaN epitaxial layer 20 on the silicon-based substrate 10, wherein the thickness of the GaN epitaxial layer 20 is about 1-2um, and performing a first photoetching process on the surface of the GaN epitaxial layer 20 to form uniform grooves 22;
s3, growing the AlGaN epitaxial layer 30 on the surface of the GaN epitaxial layer 20, wherein the uneven GaN epitaxial layer 20 and the AlGaN epitaxial layer 30 are designed due to the grooves 22;
s4, depositing doped P-GaN on the AlGaN epitaxial layer 30, and performing a second photoetching Process (PG) to form P-GaN Gate33 to form an E-mode GaN-based device;
s5, depositing Ohmic Contact metal on the AlGaN epitaxial layer 30 and performing a third photolithography process (OC) to form a source Contact 31 and a drain Contact 32;
s6, performing a fourth photolithography process (IS) on the AlGaN epitaxial layer 30, forming an isolation oxide layer 21 through an implantation process, and depositing a first insulating layer 40 on the P-GaN Gate33, the source contact 31 and the drain contact 32 as a unit cell isolation function;
s7, carrying out a fifth photoetching process (GS) on the first insulating layer 40 to expose the P-GaN Gate33 so as to lead out the Gate;
s8, depositing metal on the surface of the chip, carrying out a sixth photoetching process (GT) at the position of the P-GaN Gate33 to form a Gate metal 34, and leading out the Gate through the Gate metal 34;
s9, depositing the second insulating layer 50 on the gate metal 34 and performing a seventh photolithography process (V0) to expose the source contact 31 and the drain contact 32;
s10, depositing the first metal layer 60 on the chip surface and performing an eighth photolithography process (M1), and drawing the source contact 31 and the drain contact 32 through the first metal layer 60;
s11, depositing a third insulating layer 70 on the chip surface and performing a ninth photolithography process (V1) to expose the first metal layer 60 on the source and drain;
s12, depositing a second metal layer 80 on the surface of the chip, performing a tenth photoetching process (M2), and leading out the source metal and the drain metal;
and S13, depositing a passivation layer 90 on the surface of the chip, performing a tenth photoetching process (TP), forming a chip front surface protection layer, and exposing routing areas of the grid electrode, the source electrode and the drain electrode to obtain the GaN-based HEMT chip with high conduction efficiency.
The design of the invention is illustrated by taking the structure of the E-mode GaN-based HEMT device of the P-GaN Gate as an example, but other designed structures of the E-mode GaN-based HEMT device are also applicable, for example, the E-mode GaN-based HEMT device of the trench Gate design is also applicable, and other structures of the D-mode GaN-based HEMT device are also applicable.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A GaN-based HEMT chip with high conduction efficiency, comprising:
a silicon-based substrate (10);
the GaN epitaxial layer comprises a GaN epitaxial layer (20) and an AlGaN epitaxial layer (30), grooves (22) are uniformly formed in the surface of the GaN epitaxial layer (20), and the AlGaN epitaxial layer (30) is fixedly connected to the grooves (22) formed in the surface of the GaN epitaxial layer (20);
the GaN epitaxial layer (20) is fixedly connected to the top end surface of the silicon-based substrate (10).
2. The high conduction efficiency GaN-based HEMT chip according to claim 1, wherein: and forming a P-GaN Gate (33), a source contact (31) and a drain contact (32) on the surface of the AlGaN epitaxial layer (30) by processes such as deposition, photoetching and the like.
3. The high conduction efficiency GaN-based HEMT chip according to claim 1, wherein: the AlGaN epitaxial layer (30) forms a source contact hole (91) and a drain contact hole (92) through a first metal layer (60) and a second metal layer (80).
4. The high conduction efficiency GaN-based HEMT chip according to claim 1, wherein: the AlGaN epitaxial layer (30) forms an isolation oxide layer (21) through an implantation process.
5. The high conduction efficiency GaN-based HEMT chip according to claim 2, wherein: a first insulating layer (40) is deposited over the P-GaN Gate (33), source contact (31), and drain contact (32).
6. The high conduction efficiency GaN-based HEMT chip according to claim 2, wherein: the surface of the P-GaN Gate (33) is fixedly connected with a Gate metal (34), and a second insulating layer (50) is deposited on the surface of the Gate metal (34).
7. The high conduction efficiency GaN-based HEMT chip according to claim 3, wherein: and a third insulating layer (70) is deposited on the surface of the first metal layer (60), and a passivation layer (90) is arranged on the surface of the second metal layer (80).
8. The high conduction efficiency GaN-based HEMT chip according to claim 1, wherein: the grooves (22) are uniformly distributed on the surface of the GaN epitaxial layer (20).
9. The high conduction efficiency GaN-based HEMT chip according to claim 1, wherein: the depth of the groove (22) on the surface of the GaN epitaxial layer (20) is less than 20 nm.
10. The method for producing a high conduction efficiency GaN-based HEMT chip according to any one of claims 1 to 9, wherein: the method comprises the following steps:
s1, selecting a raw material silicon-based substrate (10) as a preparation;
s2, growing a GaN epitaxial layer (20) on the silicon-based substrate (10), wherein the thickness of the GaN epitaxial layer (20) is about 1-2um, and performing a first photoetching process on the surface of the GaN epitaxial layer (20) to form uniform grooves (22);
s3, growing the AlGaN epitaxial layer (30) on the surface of the GaN epitaxial layer (20), wherein the uneven GaN epitaxial layer (20) and the AlGaN epitaxial layer (30) are designed due to the groove (22);
s4, depositing doped P-GaN on the AlGaN epitaxial layer (30), and performing a second photoetching Process (PG) to form P-GaN Gate (33) so as to form an E-mode GaN-based device;
s5, depositing Ohmic Contact metal on the AlGaN epitaxial layer (30) and carrying out a third photoetching process (OC) to form a source Contact (31) and a drain Contact (32);
s6, performing a fourth photoetching process (IS) on the AlGaN epitaxial layer (30), forming an isolation oxide layer (21) through an injection process, and depositing a first insulating layer (40) on the P-GaN Gate (33), the source contact (31) and the drain contact (32) for serving as unit cell isolation;
s7, carrying out a fifth photoetching process (GS) on the first insulating layer (40) to expose the P-GaN Gate (33) so as to lead out the Gate;
s8, depositing metal on the surface of the chip, carrying out a sixth photoetching process (GT) at the position of the P-GaN Gate (33) to form a Gate metal (34), and leading out the Gate through the Gate metal (34);
s9, depositing a second insulating layer (50) on the gate metal (34) and performing a seventh photolithography process (V0) to expose the source contact (31) and the drain contact (32);
s10, depositing a first metal layer (60) on the surface of the chip, carrying out an eighth photoetching process (M1), and leading out the source contact (31) and the drain contact (32) through the first metal layer (60);
s11, depositing a third insulating layer (70) on the surface of the chip and carrying out a ninth photoetching process (V1) to expose the first metal layer (60) on the source electrode and the drain electrode;
s12, depositing a second metal layer (80) on the surface of the chip, performing a tenth photoetching process (M2), and leading out the source metal and the drain metal;
and S13, depositing a passivation layer (90) on the surface of the chip, performing a tenth photoetching process (TP), making a chip front surface protection layer, and exposing routing areas of the grid electrode, the source electrode and the drain electrode to obtain the GaN-based HEMT chip with high conduction efficiency.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120074911A (en) * | 2010-12-28 | 2012-07-06 | 전자부품연구원 | Nitride semiconductor device having floated gate electrode and method for manufacturing thereof |
| CN110392929A (en) * | 2016-11-24 | 2019-10-29 | 剑桥企业有限公司 | Gallium Nitride Transistor |
| CN111554742A (en) * | 2020-05-11 | 2020-08-18 | 南方科技大学 | Preparation method of GaN HEMT device |
| WO2020181548A1 (en) * | 2019-03-14 | 2020-09-17 | 中国科学院微电子研究所 | Gan-based super-junction vertical power transistor and manufacturing method therefor |
| CN214753771U (en) * | 2021-06-07 | 2021-11-16 | 淄博汉林半导体有限公司 | GaN-based HEMT chip with high conductive efficiency |
-
2021
- 2021-06-07 CN CN202110631801.8A patent/CN113257894A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120074911A (en) * | 2010-12-28 | 2012-07-06 | 전자부품연구원 | Nitride semiconductor device having floated gate electrode and method for manufacturing thereof |
| CN110392929A (en) * | 2016-11-24 | 2019-10-29 | 剑桥企业有限公司 | Gallium Nitride Transistor |
| WO2020181548A1 (en) * | 2019-03-14 | 2020-09-17 | 中国科学院微电子研究所 | Gan-based super-junction vertical power transistor and manufacturing method therefor |
| CN111554742A (en) * | 2020-05-11 | 2020-08-18 | 南方科技大学 | Preparation method of GaN HEMT device |
| CN214753771U (en) * | 2021-06-07 | 2021-11-16 | 淄博汉林半导体有限公司 | GaN-based HEMT chip with high conductive efficiency |
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